JPH0758629A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the feedback capacitance due to the Miller effect between input and output terminals to increase the switching speed and to easily make a device work in high-frequency range by turning on an output MOS transistor TR and making the gate acting as a shield electrode. CONSTITUTION:P-channel MOS TRs 11 and 12 are connected in series between a power VDD terminal 17 and an output terminal 16 and N-channel MOS TRs 13 and 14 are connected in series between a GND terminal 18 and the output terminal 16 to constitute complementary inverter circuit. The gate 13G of the TR 13 is connected to a VDD line, and the gate 12G of the TR 12 is connected to a GND line, and each gate is set to the completely turn-on state, and the impedance is reduced. Consequently, these gates act as shield electrodes, and the feedback capacitance due to the Miller effect between gates 11G and 14G and drains 11D and 14D of TRs 11 and 14 connected to an input terminal 15 is reduced not to increase the switching speed and to make the device work in high-frequency range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a C-MOS used in a complementary inverter circuit or the like.
The present invention relates to a semiconductor device such as an IC.

[0002]

2. Description of the Related Art A conventional example of a C-MOS IC used in a complementary inverter circuit will be described with reference to FIG.

The complementary inverter circuit shown in FIG. 1 has a P-channel MOS transistor 3 between one [V _DD ] terminal 5 of the power supply and the output terminal 2 and the other [GND] terminal 6 of the power supply and the output terminal. 2, an N-channel MOS transistor 4 is connected between the two and the gates of both transistors are commonly connected to the input terminal 1. Specifically, the gates of both MOS transistors 3 and 4 are commonly connected to the input terminal 1, and their drains are commonly connected to the output terminal 2. Further, the source of the P-channel MOS transistor 3 is connected to the power supply terminal 5, and the source of the N-channel MOS transistor 4 is connected to the ground terminal 6.

The mask wiring pattern of this complementary inverter circuit is formed on the surface of the substrate as follows, as shown in FIG. That is, the gates 3G and 4G of the P-channel MOS transistor 3 and the N-channel MOS transistor 4
Is commonly connected to the input line 1L, and the drains 3D and 4D of both MOS transistors 3 and 4 arranged inside the gates 3G and 4G are commonly connected to the output line 2L. Further, the source 3S arranged outside the gate 3G of the P-channel MOS transistor 3 is connected to the _VDD line 5L.
Connected to the gate 4 of the N-channel MOS transistor 4.
The source 4S arranged outside G is connected to the GND line 6L.

[0005]

By the way, in recent years, C-
Despite the demand for higher switching speed and higher frequency of MOS ICs, the above-mentioned conventional CM
In the OS IC, the feedback capacitance due to the Miller effect between the gates 3G and 4G and the drains 3D and 4D of both the MOS transistors 3 and 4 is large, and as a result, the input capacitance is large and the above-mentioned switching speed is improved and the frequency is increased. Was difficult.

Therefore, the present invention has been proposed in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of easily improving the switching speed and increasing the frequency.

[0007]

As a technical means for achieving the above object, the present invention is to connect a MOS transistor of the same type in series between one terminal of a power supply and an output terminal, and connect the same to an output terminal. The gate of one of the MOS transistors is connected to the other terminal of the power supply so that the MOS transistor is completely turned on. Also, the MO connected to the output terminal
The S transistor is preferably a depletion type MOS transistor. In other words, it is an inverter of the type in which the gate of one MOS transistor is completely turned on and the MOS transistor is driven by the source input of the other MOS transistor.

[0008]

In the semiconductor device according to the present invention, the gate of one of the MOS transistors connected to the output terminal is connected to the ground terminal or the power supply terminal to bring it into a completely ON state.
Since the gate acts as a shield electrode, the feedback capacitance can be reduced by the mirror effect between the input and output terminals,
As a result, the input capacitance is reduced and the switching speed can be improved and the frequency can be increased.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to the complementary inverter circuit shown in FIGS. 3 and 4 will be described with reference to FIGS.

The complementary inverter circuit of the present invention shown in FIG. 1 has two P-channel MOS transistors 11 and 12 of the same type between the [V _DD ] terminal 17 and the output terminal 16 of one of the power supplies. , And first and second MOS transistors] are connected in series, and similarly, two N-channel MOS transistors 13 of the same type are provided between the [GND] terminal 18 and the output terminal 16 on the other side of the power supply. , 1
4 [hereinafter, referred to as third and fourth MOS transistors]
Are connected in series.

Specifically, the gates of the first and fourth MOS transistors 11 and 14 are commonly connected to the input terminal 15,
The drains of the second and third MOS transistors 12 and 13 are commonly connected to the output terminal 16. On the other hand, the first MOS
The source of the transistor 11 is connected to the VDD terminal 17 and the fourth M
The source of the OS transistor 14 is connected to the GND terminal 18, respectively. In addition, the drain of the first MOS transistor 11 and the source of the second MOS transistor 12 are connected, and the drain of the third MOS transistor 13 and the source of the fourth MOS transistor 14 are connected.

The mask wiring pattern of the complementary inverter circuit of the present invention is formed on the surface of the substrate as follows, as shown in FIG. That is, the gates 11G and 14G of the first and fourth MOS transistors 11 and 14 are formed in a U shape and commonly connected to the input line 15L.
The second and third MOS transistors 12 are provided inside the 4G,
The drains 11D and 14D of the first and fourth MOS transistors 11 and 14 arranged via 13 are commonly connected to the output line 16L. Further, the source 11S disposed outside the gate 11G of the first MOS transistor 11
Connected to the V _DD line 17L and the source 14S disposed outside the gate 14G of the fourth MOS transistor 14
Is connected to the GND line 18L.

On the other hand, the gate 12G of the second MOS transistor 12 is arranged in parallel between the gate 11G of the first MOS transistor 11 and the drain 11D of the first MOS transistor 11 on the output line 16L to GND.
The gate 13G of the third MOS transistor 13 is connected to the line 18L, and the gate 14G of the fourth MOS transistor 14 and the fourth M on the output line 16L are connected.
It is arranged in parallel with the drain 14D of the OS transistor 14 and connected to the V _DD line 17L.

In the complementary inverter circuit of the present invention having the above-mentioned structure, the third MOS transistor close to the output line 16L is provided.
The gate 13G of the transistor 13 is connected to the _VDD line 17L, and similarly, the second MOS near the output line 16L is connected.
The gate 12G of the transistor 12 is connected to the GND line 18L
The gates 12G and 13G of the second and third MOS transistors 12 and 13 are completely turned on by being connected to
And the impedance is low in terms of AC. As a result, the gates 12G and 13G of the second and third MOS transistors 12 and 13 act as shield electrodes, and the first and fourth MO transistors connected to the input terminal 15 are connected.
Gates 11G and 14G of the S transistors 11 and 14,
The second and third MOS transistors 1 are connected to the output terminal 16.
The feedback capacitance due to the Miller effect between the drains 11D and 14D of the first and fourth MOS transistors 11 and 14 connected via 2 and 13 is
It is reduced by the presence of the gates 12G and 13G of the transistors 12 and 13. Due to this reduction of the feedback capacitance, the input capacitance is reduced and the switching speed is increased.

In the above embodiment, the case where the invention is applied to the complementary inverter circuit has been described, but the present invention is not limited to this, and can be applied to other logic circuits such as an AND circuit and an OR circuit. is there.

[0016]

According to the semiconductor device of the present invention, the gate of one of the MOS transistors connected to the output terminal is connected to the ground terminal or the power supply terminal to bring it into a completely ON state, so that the gate is shielded. As a result, the feedback capacitance due to the Miller effect between the input and output terminals can be reduced, and as a result, the input capacitance can be reduced, the switching speed can be improved and the frequency can be increased, and a semiconductor device of great practical value Can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a complementary inverter circuit for explaining an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a plan view showing a mask wiring pattern of the complementary inverter circuit of FIG.

FIG. 3 is for explaining a conventional example of a semiconductor device,
Circuit diagram showing complementary inverter circuit

FIG. 4 is a plan view showing a mask wiring pattern of the complementary inverter circuit of FIG.

[Explanation of symbols]

11-14 MOS transistor 11G-14G gate 11D-14D drain 11S-14S source 15 input terminal 16 output terminal 17 one [V _DD ] terminal of the power supply 18 the other [GND] terminal of the power supply

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/017 8321-5J

Claims (3)

[Claims] 1. A MOS transistor of the same type is connected in series between one terminal and an output terminal of a power supply, and the gate of one MOS transistor connected to the output terminal is connected to the other terminal of the power supply to complete ON. A semiconductor device characterized by being put into a state. 2. The semiconductor device according to claim 1, wherein a channel region near the drain connected to the output terminal is a depletion structure MOS transistor. 3. A P-channel MOS transistor and an N-channel MOS transistor whose drains are commonly connected to serve as an output terminal.
Comprising a complementary circuit in which the gates of the transistors are connected to the low potential side and the high potential side of the power supply terminal and the source electrode is an input, and a source-grounded complementary circuit that drives each of the source electrodes A semiconductor device characterized by a P-channel MOS transistor and an N-channel MOS transistor.