JPH0758600B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a nonvolatile semiconductor memory having a floating gate.

[Conventional technology]

A method of reading information of the nonvolatile semiconductor memory device having a conventional floating gate (hereinafter simply referred to as a memory device) in comparison with the pseudo memory device having the same structure and the same size, after writing of the memory device voltage (hereinafter V _{TM -W} ) is difficult to measure, so the value is slightly biased (V _TM-W +
It can be measured only as a rough guideline of α), and further, there is a problem that the α does not have a constant value, but its size varies depending on the value of V _{TM -W} . For this reason, the correct value of _VTM-W of the actual memory element cannot be measured, and it is difficult to investigate the write characteristics.

A semiconductor device having a read circuit which is generally used in the past will be described with reference to the drawings.

FIG. 2 shows an example of the configuration of a read circuit of a conventional semiconductor device.

Memory element M1, sense amplifier S1, insulated gate field effect transistor (hereinafter abbreviated as IGFET) MP1, M2, MPd
・ Current comparison circuit 2 composed of M3 (here, MP
1 and MPd are P-channel type IGFETs, M2 and M3 are N-channel type IGFETs), the pseudo memory element MD and the sense amplifier section SD constitute a read circuit. Here, the sense amplifier sections S1 and SD are configured by the same circuit so as to exhibit the same characteristics. IGFET M1 ・ M to be compared by the conductance resistance ratio (gm ratio) of IGFET M2 and M3
The current ratio of D is determined, but if the gm of IGFET M3 (transistor w / L) is tripled compared to IGFET M2, IGFETM
Read as "on" when more than 1/3 of the current flowing in D flows in IGFET M1.

This operation will be described with reference to FIG.

The horizontal axis of FIG. 3 represents the gate voltage of the memory element, and the vertical axis represents the current of the memory element. A curve A is a current curve flowing through the memory element before writing, a curve B is a current curve flowing through the memory element after writing (V _{TM -W} ), and a curve C is a current when the current flowing through the pseudo memory element is 1/3. A curve is shown.

If the current I of the memory element is larger than this curve C, "o
n "(Vout" H "), if smaller," off "(Vout" L "). After writing (V _TM-W )," off "is the expected value, which satisfies this the maximum value of the gate voltage V _G becomes _{(V TM-W + α)} . If this gate voltage V _G is less than, the expected values "off", and the gate voltage V _G from (V _TM-W + α) If it is larger, it becomes “on” and malfunctions, that is, “α” with respect to V _TM- α of the memory element after actual writing
It operates normally up to the added value. Thus, even if the threshold voltage of the memory element is V _TM-W , when V _CC is raised and monitored, only V _CC max = (V _TM-W ) + α can be measured, and the actual V _TM-W Is difficult to measure.

[Problems to be solved by the invention]

As described above, the read circuit of the conventional semiconductor device is
The drawback is that the actual threshold voltage of the memory device cannot be measured.

SUMMARY OF THE INVENTION Problems to be solved by the present invention, in other words, an object of the present invention is to provide means for changing the gate voltage of a pseudo memory element in order to eliminate the drawbacks of the read circuit of the conventional semiconductor device as described above. Accordingly, it is an object of the present invention to provide a semiconductor device capable of easily measuring the threshold voltage of a memory element.

[Means for solving problems]

A semiconductor device of the present invention includes a nonvolatile semiconductor memory element having a floating gate, and a pseudo-nonvolatile semiconductor memory element for comparison having the same structure and size as the nonvolatile semiconductor memory element for storing write or erase information. In a semiconductor device including a circuit for reading information of the nonvolatile semiconductor memory element on the same semiconductor substrate by comparing the currents of the nonvolatile semiconductor memory element and the pseudo-nonvolatile semiconductor memory element for comparison, A first insulated gate field effect transistor connected to one power supply and a second insulated gate field effect transistor having a drain connected to a second power supply, wherein the first and second insulated gate field effect transistors The source of the effect transistor is connected to the gate of the pseudo non-volatile semiconductor memory device.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In FIG. 1, a memory device M1 having a floating gate,
The pseudo-memory element M _D having the same structure and size as the memory element M1 for comparison and the memory element M1 storing the write or erase information are connected to the sense amplifier sections S1 and S _D and the IGFET MP1, MP2, and MPd.
・ A circuit for reading the information of the memory device M1 by comparing the current with M3 is provided on the same semiconductor substrate, and the pseudo memory device
Means for making the voltage V _G1 applied to the gate of M _D independent of the gate applied voltage (V _{CC in} this case) of the memory device M1. , Set IGEFETMR2 to “on”, set V _G1 ≈ V _PP, and set V
_{By making PP} variable, the voltage applied to the gate of the pseudo memory device M _D can be made variable). IGFET MR1 and MR2 are connected to the gate of the pseudo memory element M _D as follows. That is, N-channel depletion type IGFETM
R1 is a drain to V _CC, the gate ▲ ▼ to, a source connected to the gate of the pseudo memory device M _D, N-channel type IGFETMR2 is the gate to V _Re, the drain second power supply V
_{At PP} , the source is connected to the gate of the pseudo memory device M _D.

Next, the operation of the above circuit will be described with reference to FIG.

Control signal during normal read Setting MR1 to “on” and MR2 to “off” to set the gate voltage V _G1 of the pseudo memory device M _D to the first power supply V
Becomes _CC the same potential, the same operation as the conventional circuit is equal gate voltages of the memory device M1 and the pseudo memory device M _D. Next, during the test to read the threshold voltage of the memory device M1, the control signal And turn on both IGFETMR1 and IGFETMR2. Here, by setting the gm of IGFETMR2 sufficiently larger than the gm of IGFETMR1, V _G1 ≈V _PP . By setting this V _PP near the initial threshold voltage V _TMO of the memory device M1, the pseudo memory device M _D has the current characteristic shown by the curve D in FIG. As a result, the difference β between the threshold voltage V _TM-W of the memory element M1 after writing and the power supply voltage operation maximum value V _CC max is significantly reduced. So by measuring V _CC max
V _TM-W can be easily measured.

〔The invention's effect〕

As described above in detail, the present invention has an effect that the threshold voltage of the memory element can be easily measured by providing the means capable of varying the gate voltage of the pseudo memory element.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a conventional semiconductor device, and FIG. 3 is a current characteristic for explaining the operation of the example of FIG. FIG. 4 is a graph showing current for explaining the operation of the embodiment shown in FIG. S1, SD …… Sense amplifier section, M2, M3, MR2 …… n channel
IGFET, MR1 ... n-channel depletion type IGFET, M
P1, MPd ...... P-channel IGFET, M1 ...... memory element, M _D
...... Pseudo memory device.

Claims (1)

[Claims] 1. A non-volatile semiconductor memory device having a floating gate, and a pseudo-non-volatile semiconductor memory device for comparison having the same structure and size as the non-volatile semiconductor memory device for storing write or erase information. In a semiconductor device having a circuit for reading out information of the nonvolatile semiconductor memory element on the same semiconductor substrate by comparing the currents of the nonvolatile semiconductor memory element and the pseudo-nonvolatile semiconductor memory element for comparison, the first drain is provided. A first insulated gate field effect transistor having a power supply connected thereto and a second insulated gate field effect transistor having a drain connected to a second power supply, wherein the first and second insulated gate field effect transistors are provided. The semiconductor device is characterized in that the source is connected to the gate of the pseudo-nonvolatile semiconductor memory element.