JPH0758129A - Method of manufactur field effect transistor - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a field effect transistor which has a gate electrode, using two layers of resist without providing a separation between the resist layers. CONSTITUTION:A first resist layer is formed with resist covering a temporary gate 8 and it is turned insoluble in developing liquid by exposure. Then a second resist layer 13 is formed with resist, the region positioning on the temporary gate is masked, exposed and baked, and a reverse tapered groove 14 is formed by developing the second resist layer 13. After removing the temporary gate 8 in the groove 14 and depositing a metal film 15 for a gate electrode, a T-shaped gate 16 is formed removing the first and the first and the second layers 12 and 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor (hereinafter referred to as FET). More specifically, the present invention relates to a method for manufacturing an FET having a gate electrode having a T-shaped cross-section with a thin lower portion on the semiconductor substrate side and a thick upper portion, which is a gate electrode of an FET used at high frequencies. Here, the T-shape includes a mushroom shape.

[0002]

2. Description of the Related Art In recent years, satellite broadcasting has become widespread, but a converter for satellite broadcasting receivers requires a low noise and high gain amplifier in the microwave band. As a microwave band semiconductor device, a Schottky junction FET using a compound semiconductor such as GaAs, so-called MESFET, has been conventionally developed. This MESFET is suitable for miniaturization of the gate length because of its simple structure and manufacturing process, and is widely used for devices having excellent high frequency characteristics and integrated circuits requiring high-speed operation because of its high electron mobility. ing.

As is well known, it is necessary to shorten the gate length in order to realize higher frequency operation. However, if the gate electrode is simply miniaturized for the purpose of shortening the gate length, the electrical resistance of the gate electrode is increased, which deteriorates the noise characteristic. Therefore, a gate electrode having a small gate length and a low electric resistance is required. Therefore, a gate electrode having a T-shaped or mushroom-shaped cross section is used so that the lower portion in contact with the active layer of the semiconductor substrate is thin and the upper portion is thick.

An example of a conventional method of manufacturing a semiconductor device having a gate electrode having a T-shaped cross section is disclosed in, for example, Japanese Patent Laid-Open No. 2-2.
It is described in Japanese Patent Application No. 99245 (Japanese Patent Application No. 1-120989) and Japanese Patent Application Laid-Open No. 4-44238 (Japanese Patent Application No. 2-150393). The latter manufacturing method will be described with reference to FIGS.

First, as shown in FIG. 5A, a temporary gate 22 is formed on a semiconductor substrate 21. This temporary gate 22 is made of, for example, SiON on the entire surface of the semiconductor substrate 21 by plasma CV.
The temporary gate 22 is formed by patterning by the D method or the like, and patterning is performed to remove the portion other than the portion required as the temporary gate by etching.

Next, as shown in FIG. 5B, a photoresist is applied to the entire surface of the semiconductor substrate 21 so as to cover the temporary gate 22 over the entire surface of the semiconductor substrate 21,
The first resist layer 23 is formed.

Next, as shown in FIG. 5C, the first resist layer is formed so that the temporary gate 22 is exposed by a predetermined amount.
The upper part of 23 is removed by etching the entire surface. As an etching method, for example, reactive ion etching using O ₂ plasma (hereinafter referred to as RIE) can be used.

Next, as shown in FIG. 6D, a metal film 24 of Ni or the like is formed on the exposed surfaces of the temporary gate 22 and the first resist layer 23 by a vacuum deposition method or a sputtering method. .

Next, as shown in FIG. 6E, a second resist layer 25 is formed by applying a resist on the metal film 24, and the second resist layer 25 is formed on the temporary gate 22. An inversely tapered groove 26 is formed in a region located at the area where the width increases from the resist surface toward the metal film 24. This reverse test
The pa-shaped groove 26 can be formed by the following method using, for example, an image reversal positive photoresist.
That is, the image reversal positive photoresist is exposed to light.
When reversal-baked at about 110 to 120 ° C., the exposed portion exhibits a reversal action of making it insoluble in a developing solution. For example, a resist such as AZ5200E series of Hoechst in Germany can be used. Therefore, the temporary gate 23 of the second resist layer 25 applied over the entire surface
After exposing the mask with a mask on it, remove the mask and then 110
By reversal baking at ~ 120 ° C and exposing the entire surface again, only the portion of the second resist layer 25 that is not insoluble in the developing solution, that is, the portion that is initially masked on the temporary gate 22 is the second time. Exposure (post-exposure). After that, by developing with TMAH or the like, only the resist layer in the post-exposed portion is removed.
As shown in (e), the groove 26 is formed. As shown in FIG. 6E, the cross section of the groove 26 has a divergent shape, that is, a reverse taper cross section.

Next, as shown in FIG. 6 (f), the metal film 24 in the groove 26 is removed by etching with dilute hydrochloric acid, for example.

Next, as shown in FIG. 7 (g), the temporary gate 22 in the groove 26 is removed by etching, for example, with a buffered hydrofluoric acid solution.

Then, as shown in FIG. 7H, a metal film for gate is formed in the groove 26 by a thickness thinner than that of the second resist layer 25.
27 is formed on the entire surface by vapor deposition or the like. As a result, the portion where the groove 26 is formed in the second resist layer 25 is in the groove 26,
A second resist layer is formed on the portion where the groove 26 is not formed.
A metal film 27 for a gate electrode is deposited on 23.

Finally, as shown in FIG. 7 (i), the first resist layer 23 and the second resist layer 23 are made of, for example, acetone.
By removing 25, the gate electrode metal film 27 on the second resist layer 25 is also removed, and the gate electrode 28 has a thin lower portion, a thick upper portion, and a T-shaped cross section on the semiconductor substrate 21. It is formed.

In the manufacturing method disclosed in the above-mentioned Japanese Patent Laid-Open No. 2-299245, the resist layer is formed as a single layer, and an inversely tapered groove is formed so that only the temporary gate portion is exposed at the top of the temporary gate. After that, the temporary gate is removed by etching, a gate metal is provided as in the above example, and then the resist layer is removed.

[0015]

In the conventional method using a single-layer resist, it is necessary to control the thickness of the resist layer to be left when forming the reverse taper groove so that the top of the temporary gate is exposed. It is difficult, and especially when the thickness of the resist layer to be left is large, there is a problem in that a crack is formed between the upper part and the lower part of the T-shaped gate and the upper part is easily peeled off. Further, there is a problem that the resist is likely to float during etching of the temporary gate.

Further, according to the method using the two-layer resist using the above-mentioned interlayer metal film, the first resist layer and the second resist layer have a structure requiring a separation layer such as a metal film. Therefore, there is a problem that an extra metal film forming step is required.

Further, when wet etching is used to remove the metal film in the groove and the temporary gate, the metal film is also etched in the lateral direction, and there is a problem that the second resist in the upper layer is likely to float. Further, when dry etching is used, etching in the lateral method can be prevented, but there is a problem that the surface of the semiconductor substrate provided with the temporary gate is damaged when the temporary gate is removed.

Further, there is a problem that the etching process is required twice because the metal film needs to be etched more than the etching of only the temporary gate.

The present invention solves the above-mentioned problems by using a two-layer resist method which does not use a separation film such as a metal film.
It is an object of the present invention to provide a method of manufacturing a FET in which a leg gate of a T-shaped gate electrode can be formed with good controllability by a simple process.

[0020]

According to the method of manufacturing a field effect transistor of the present invention, (a) a temporary gate is formed in a region on a semiconductor substrate where a gate electrode is to be formed, and (b) a negative type covering the temporary gate. A resist material is applied to the surface of the semiconductor substrate, and then the entire surface is exposed to form a first resist layer covering the temporary gate, and (c) the upper portion of the first resist layer is removed, and the upper portion of the temporary gate is formed. And (d) baking is performed at a temperature such that the solvent in the resist can be removed after the step (b) or (c), and (e) the resist material is partially exposed to the first gate. To form a second resist layer by coating on the resist layer of (1), (f) mask and expose the region located above the temporary gate, and then develop the second resist layer, (g) Second resist after removing the temporary gate Provided a thin gate electrode metal film than the layer, then, it is characterized in that the allowed to form a gate electrode of the (h) cross-section by removing the first and second resist layer is T-shaped.

The first resist layer and / or the second resist layer is an image reversal positive type photoresist, and in the step (b), the resist material is applied, and after exposure, a reversal bake is performed. In step f), it is preferable that the resist material is exposed, then reversal baked, and then the entire surface is exposed.

Further, in the step of removing the upper portion of the first resist layer and exposing the upper portion of the temporary gate in the step (c) of the manufacturing method, it is preferable that the upper portion of the temporary gate is also removed by etching at the same time.

Further, in the method for manufacturing a field effect transistor according to claim 4, in the method for manufacturing a field effect transistor according to claim 1, at the time of exposure in the step (b), a mask is applied to a wiring region portion connected to the gate electrode. To prevent exposure to light, and then to develop to remove the first resist layer in the wiring region portion, and at the time of exposure in step (f), the wiring connected to the region above the temporary gate and the gate electrode. The second resist layer on the temporary gate and on the wiring region portion is removed by masking the region portion so as not to be exposed to light, and then developing, and the gate electrode wiring is simultaneously formed at the time of forming the gate electrode in step (h). It is characterized by forming.

[0024]

According to the present invention, the first resist layer is exposed to light,
Since it is further baked, when the region of the second resist layer located above the temporary gate is developed to form the reverse tapered groove, the underlying first resist layer is not affected at all. Therefore, it is not necessary to separate the first and second resist layers with a metal film or the like, and moreover, the thickness of the first resist layer can be accurately left, and a gate electrode having an accurate size can be formed by a simple process. can do.

According to the fourth aspect of the present invention, when the lower first resist layer and the upper second resist layer are exposed, the regions of the wiring portions connected to the gate electrodes are masked and developed. Since the resist layer can be removed by the method, not only the T-shaped gate electrode but also the wiring portion following the T-shaped gate electrode can be formed at the same time, and they can be formed continuously at one time.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing an FET having a gate electrode having a T-shaped cross section according to the present invention will be described below with reference to the drawings. 1 to 3 are cross-sectional explanatory views showing respective manufacturing steps of an embodiment of a method for manufacturing a high frequency FET of the present invention, and FIG. 4 is a plan view of an embodiment in which a wiring portion connected to a gate electrode is formed at the same time as a T-shaped gate electrode. FIG.

First, as shown in FIGS. 1A to 2F, an active region is formed on the surface of a semiconductor substrate, and a temporary gate is formed in a region where a gate electrode is to be formed. As the semiconductor substrate, a semi-insulating GaAs substrate, InP substrate, or the like is preferable as the high-frequency FET. When a semi-insulating GaAs substrate is used as the semiconductor substrate for the active region, for example, as shown in FIG.
An n-type impurity is ion-implanted into the surface of the substrate to form an operating layer, but when an epitaxial layer is used as the n-layer, the ion-implantation step for forming the n-layer is not necessary. Furthermore, FIG.
In the embodiment shown in (b), the mesa type is used to form the operating region, but the invention is not limited to the mesa type and may be a planar type or the like when the n layer is formed by ion implantation.

The material for the temporary gate may be any material that can be easily etched with the resist layer during subsequent etching and is easily etched. For example, SiON or S.
iN _x , SiO ₂ or the like can be used. Although the size of the temporary gate depends on the desired characteristics of the FET, it is usually formed to have a height of 0.4 to 0.6 μm and a width of 0.3 to 1.5 μm. Further, the temporary gate is formed by depositing a material for the temporary gate by a sputtering method, a CVD method, a plasma CVD method or the like as in the process of a normal semiconductor device, and by dry etching such as RIE using CHF ₃ + O ₂ plasma. It is formed.

Further, in order to activate the ion implantation layer,
As shown in FIG. 2 (f), S is formed on the entire surface by plasma CVD.
After forming an annealing protection film using an iON film, etc., 750
~ Heat treatment at 850 ℃. Then, the film is removed by etching.

Next, as shown in FIG. 2 (g), an image reversal positive type resist material covering the temporary gate is applied to the surface of the semiconductor substrate, and then the entire surface is exposed, and then a reversal bake is conducted at 110 ° C. to 120 ° C. To form a first resist layer covering the temporary gate. A negative resist material or the like may be used as the resist material, but in this case, the reversal bake is not necessary.

Next, as shown in FIG. 2H, the upper part of the first resist layer is removed to expose the upper part of the temporary gate. The removal of the upper portion of the first resist layer is performed, for example, with O
_{2 Use} of dry etching such as RIE using plasma is convenient for etching the first resist layer to a desired thickness because it is relatively easy to control the etching rate. CHF _{3 for} this etching
The thickness of the temporary gate is 0.1 to 0.2 μm using + O ₂ etc.
It is preferable that a part of the upper portion of the temporary gate is etched at the same time so that the temporary gate etching time after the formation of the second resist layer is shortened.

After forming the above-mentioned first resist layer,
Alternatively, after removing the upper portion of the first resist layer by etching, the first resist layer is baked at 130 to 170 ° C. in order to sufficiently remove the solvent.

Next, a second resist layer is formed by further applying a resist material on the first resist layer where a part of the temporary gate is exposed. As a resist material for the second resist layer, an image reversal positive type photoresist is used to form a reverse taper type groove described later.

Next, as shown in FIG. 3 (i), the region located above the temporary gate is masked, exposed, reversal baked, and then exposed on the entire surface, and then the second resist layer is developed. As a result, the reverse tapered groove 14 as shown in FIG. 3 (i) is formed. The reverse tapered groove 14 is formed by using an image reversal positive type photoresist as the second resist layer. That is, when using this resist, after applying it by spin coating or the like, the region located above the temporary gate is masked and exposed, reversal baked, and the entire surface is exposed and then developed. Only the unexposed portion is removed, but the amount of light transmitted into the resist layer becomes smaller as it becomes deeper. Therefore, in the deep portion of the resist layer, not only the lower side of the mask but also the periphery thereof is developed to form a reverse tapered groove. When a negative type resist is used as this resist material, reversal bake and overall exposure are not required. Since the first resist layer is entirely exposed to light and baked at a temperature of 130 ° C. or higher before the second resist layer is adhered, if an image reversal positive resist is used for the first resist layer. However, even when a negative resist is used, it is not affected at all by exposure and development of the second resist layer. Therefore, only the second resist layer is formed with the reverse taper-shaped groove 14 having a wider width toward the first resist layer.

Next, as shown in FIG. 3J, after removing the temporary gate, a metal film for a gate electrode, which is thinner than the second resist layer, is provided. First to remove this temporary gate
Alternatively, without etching the second resist layer, etching may be performed with an etching solution for etching only the temporary gate material, for example, buffer hydrofluoric acid when SiON is used as the temporary gate. The metal film for the gate electrode is
For example, a metal material such as a three-layer metal film in which Ti, Pt, and Au are laminated in this order or a two-layer metal film in which Ti and Au are laminated in this order is formed by a sputtering method, a vacuum evaporation method, or the like to form 0.4 to 0.7. It is provided with a thickness of about μm. As a result, the portion of the second resist layer 13 in which the groove 14 is formed is in the groove 14, and in the portion in which the groove is not formed, the gate electrode metal film 15 is formed on the second resist layer 13. Since the metal film 15 is stacked and stacked on the portion where the temporary gate is removed, the gate electrode 16 having a T-shaped cross section is formed.

Then, the first and second resist layers 12,
By removing 13, the gate electrode metal film 15 on the second resist layer 13 is lifted off, and only the gate electrode 16 is removed.
The FET is completed by forming the source electrode 17 and the drain electrode 18 which are formed on the active region and are thereafter made of an Au-Ge film or the like. First and second resist layer 1
Acetone can be used as an etching solution for removing the second and the third, for example.

Next, more detailed description will be given with reference to specific examples.

Example 1 After a SiN film was formed on the entire surface of a semiconductor substrate 1 in which an n layer 2 was epitaxially grown on a semi-insulating GaAs substrate, a predetermined amount was formed on the surface of the semiconductor substrate 1 to form source and drain regions. By forming a resist pattern 3 having a hole of a size of n and implanting Si ions deeper and higher in concentration than the n layer 2 into the n ⁺⁺ layer 4 on the semiconductor substrate 1.
Was formed (see FIG. 1A).

This n ⁺⁺ layer 4 becomes the source region and the drain region of the field effect transistor. Further, the resist pattern 3 was removed, and the SiN film was removed by etching with a hydrofluoric acid solution.

Next, a resist pattern 5 is formed on a part of the n ⁺⁺ layer 4 of the semiconductor substrate 1 and a part sandwiched therebetween, and mesa etching is performed to form a mesa n-type GaAs layer having a trapezoidal cross section. Formed as an operating area (Fig. 1 (b))
reference).

Next, a temporary gate material of SiON was deposited on the semiconductor substrate 1 by the plasma CVD method to form a temporary gate layer 6 having a film thickness of about 0.4 μm. Further, a resist is applied on the temporary gate layer 6, exposed through a photomask, and developed to form a temporary gate forming resist pattern 7 corresponding to the gate electrode on the temporary gate layer 6 (FIG. 1). (See (c)).

Then, the temporary gate layer 6 was subjected to RIE using O ₂ + CHF ₃ plasma through the temporary gate forming resist pattern 7 to form the temporary gate 8 (see FIG. 1D).

Next, a part of the n ⁺⁺ layer 4 is covered with a resist layer 9 leaving the upper bottom of the mesa type active layer having a trapezoidal cross section, and S
I was ion-implanted (arrow) to form an n ⁺ layer 10 (FIG. 2).
(See (e)). The n ⁺ layer 10 is a layer having a depth and concentration intermediate between those of the n layer 2 and the n ⁺⁺ layer 4 and serves as a source region and a drain region.

Next, after removing the resist layer 9 with acetone, a SiON film is formed as an annealing protection film 11 over the entire surface of the semiconductor substrate 1 by a plasma CVD method at 200 Å.
It was formed to a thickness of about. This is to prevent evaporation of As during annealing (see FIG. 2 (f)). Next, anneal at 750-850 ℃ for about 10-30 minutes,
The n ⁺ layer 10 and the n ⁺⁺ layer 4 were activated.

Next, the annealing protection film 11 is formed with CHF ₃ + O.
Removed by RIE with ₂ . As the first resist layer 12, an image reversal positive type photoresist was applied by spin coating to a thickness of about 1.2 μm, and the temperature was about 100 to 110 ° C.
After pre-exposure baking, expose the entire surface, then 110-1
Reversal baking was performed at 20 ° C. (see FIG. 2 (g)).

Next, part of the upper portion of the temporary gate 8 is exposed,
The first resist layer 12 was etched by RIE using O ₂ + CHF ₃ plasma so that the thickness of the temporary gate 8 was about 0.15 μm (see FIG. 2H). After that, about 150
Baking at ℃.

Next, an image reversal positive photoresist was applied as the second resist layer 13 by spin coating to the entire upper surface of the first resist layer 12 and the temporary gate 8 to a thickness of about 1.5 μm, and the temperature was about 110 ° C. Baking before exposure with the second
A resist layer 13 of was formed. Further, after masking the area located above the temporary gate 8 and performing initial exposure, reversal baking is performed at about 115 ° C.
The resist film on the temporary gate 8 was removed by performing a post-exposure, which is the first exposure, and performing a development process (FIG. 3 (i)).
reference). The opening formed in this way became an inversely tapered groove 14.

Next, the temporary gate 8 in the groove 14 is removed by etching with a buffered hydrofluoric acid solution, and Ti is deposited on the entire surface.
1000Å, Pt of about 1000Å, and Au of about 3000Å were sequentially deposited to form a gate electrode metal film 15 having a three-layer structure of Ti, Pt, and Au (see FIG. 3 (j)). The total film thickness of these three layers is about 0.5 μm. The gate electrode metal film 15 formed in the groove 14 becomes a T-shaped gate electrode 16 in cross section. The gate electrode 16 is formed of three layers of Ti, Pt, and Au. When the Au film is directly formed on the GaAs layer, it easily reacts with the GaAs layer, and the Ti film is suitable for obtaining a stable interface with the semiconductor layer. The Pt film is for preventing Au from diffusing into the GaAs layer through the Ti film.

Next, by removing the second resist layer 13 with acetone, the gate electrode metal film 15 on the second resist layer 13 is also removed at the same time, and the gate electrode 16 has a thin lower part and a thick upper part. A gate electrode 16 having a T-shaped cross section was formed on the semiconductor substrate 1. After that, the source electrode 17 and the drain electrode 18 were formed by using the Au-Ge film (see FIG. 3).
(See (k)).

Example 2 A temporary gate 8 is formed in the same manner as in Example 1, and a source region and a drain region of the n ⁺ layer 10 are formed, and then, FIG.
Then, apply a negative resist as a first resist layer to a thickness of about 1.2 μm, and perform pre-exposure baking at about 100 to 110 ° C.,
It was formed by exposing the entire surface. After that, as in Example 1, the upper portion of the first resist layer was etched to expose the upper portion of the temporary gate 8 and baked at about 150 ° C.

Next, a negative resist is applied as a second resist layer by spin coating on the entire surface of the first resist layer and the upper portion of the temporary gate 8 to a thickness of about 1.2 μm, and a thickness of about 110 μm is applied.
Pre-exposure baking was performed at a temperature of ℃ to form a second resist layer 13. After that, the region above the temporary gate 8 was masked and exposed, exposed at about 100 ° C., baked and then developed to remove the resist film above the temporary gate 8 (FIG. 3 (i)). reference). In this way, the reverse tapered groove 14 was formed in the same manner as in Example 1. Subsequent steps were performed in the same manner as in Example 1 to manufacture an FET having a gate electrode having a T-shaped cross section.

Example 3 A temporary gate 8 is formed in the same manner as in Example 1 and, after forming a source region and a drain region of the n ⁺ layer 10, FIG.
As shown in (1), an image reversal positive photoresist was applied by spin coating to a thickness of about 1.2 μm. After that, the entire surface was not exposed and exposure was performed by using a mask so that the wiring region portion connected to the gate electrode was not exposed.
After that, a reversal bake is carried out, the entire surface is exposed, and then development is carried out. As shown in FIG.
The wiring region portion 19 of the resist layer 12 was removed.

After that, as in the first embodiment, the upper part of the first resist layer 12 is etched to expose the upper part of the temporary gate 8, and then the second resist layer 13 is exposed in the step of FIG. Then, during development, not only the region on the temporary gate 8 but also the wiring region connected to the gate electrode is masked and exposed so that light is not irradiated. Further, the film is reversal baked, exposed on the entire surface, and then developed. As a result,
As shown in the plan view in (b), the second resist layer around the temporary gate and in the wiring region portion 19 was removed. After that, the gate electrode metal film 15 is provided and the first and second resist layers are removed in the same manner as in the embodiment to form a gate electrode having a T-shaped cross section and a wiring connected to the gate electrode. FET was manufactured.

[0054]

According to the present invention, although the two resist layers consisting of the first and second resist layers are used, the first and second resist layers are separated by a metal film or the like. Since it is not necessary to do so, the step of forming the metal film is unnecessary, the manufacturing process is simplified, and the etching removal of the metal film is not necessary. Therefore, the manufacturing process can be shortened and the productivity can be improved.

Further, according to the present invention, when the first and second resist layers are exposed, the regions of the wiring portions connected to the gate electrodes are also exposed so that only the T-shaped gate electrodes are formed in the subsequent process. Not only that, but also the subsequent wiring portion can be formed at the same time, the productivity can be further improved, and the displacement of the T-shaped gate electrode and the wiring layer portion connected thereto can be prevented,
In addition, when the wiring is formed after the gate is formed, there is no step formed by overlapping the two at the connection portion, and the reliability is greatly improved.

[Brief description of drawings]

FIG. 1 is a process cross-sectional explanatory view of an example of a method for manufacturing a field effect transistor of the present invention.

FIG. 2 is a process cross-sectional explanatory view of an example of a method for manufacturing a field effect transistor of the present invention.

FIG. 3 is a process cross-sectional explanatory view of an example of a method for manufacturing a field effect transistor of the present invention.

FIG. 4 is an explanatory plan view of another embodiment of the method for manufacturing the FET of the present invention.

FIG. 5 is a process cross-sectional view of a conventional method for manufacturing a field effect transistor.

FIG. 6 is a process cross-sectional view of a conventional field effect transistor manufacturing method.

FIG. 7 is a process cross-sectional view of a method for manufacturing a conventional field effect transistor.

[Explanation of symbols]

 1 Semiconductor Substrate 8 Temporary Gate 12 First Resist Layer 13 Second Resist Layer 14 Groove 15 Metal Film for Gate Electrode 16 Gate Electrode

Claims (4)

[Claims] 1. A method of: (a) forming a temporary gate on a region of a semiconductor substrate where a gate electrode is to be formed; and (b) applying a negative resist material covering the temporary gate to the surface of the semiconductor substrate, and then covering the entire surface. To form a first resist layer covering the temporary gate, (c) removing the upper part of the first resist layer to expose the upper part of the temporary gate, and (d) the above (b) or (c). After the step (b), baking is performed at a temperature that allows the solvent in the resist to be removed, and (e) a negative resist material is applied onto the first resist layer where a part of the temporary gate is exposed to form a second resist. (F) the second resist layer is developed, and then (g) the temporary gate is removed, and then the second resist layer is formed. A metal film for the gate electrode that is thinner than Then, (h) the first and second resist layers are removed and the cross section is T
A method of manufacturing a field effect transistor, characterized in that a gate electrode having a V-shape is formed. 2. The first resist layer and / or the second resist layer.
The resist layer is an image reversal type photoresist, the resist material is applied in the step (b), exposed and then reversal baked, and the resist material is exposed in the step (f) and then reversal baked. The method of manufacturing a field effect transistor according to claim 1, further comprising exposing the entire surface. 3. The step of removing the upper part of the first resist layer in the step (c) and exposing the upper part of the temporary gate, the upper part of the temporary gate is also etched away at the same time. Manufacturing method of field effect transistor. 4. The method of manufacturing a field effect transistor according to claim 1, wherein at the time of the exposure in the step (b), a wiring region portion connected to the gate electrode is masked so as not to be exposed, and then developed. The first resist layer in the wiring region portion is removed, and at the time of the exposure in the step (f), the region located above the temporary gate and the wiring region portion connected to the gate electrode are masked so as not to be exposed. A method of manufacturing a field effect transistor, characterized in that the second resist layer on the temporary gate and on the wiring region portion is removed by developing, and the gate electrode wiring is simultaneously formed at the time of forming the gate electrode in the step (h).