JPH0756755A - Method for controlling processor - Google Patents

Abstract

PURPOSE:To obtain effective prefetch technique for a processor adopting a continuous buffer or the like by means of a simple hardware constitution by previously prefetching an instruction string pointed out by an instruction painter stored in the continuous buffer to a high speed buffer memory. CONSTITUTION:A prefetching device 150 prereads continuation to be executed in the future from the continuous buffer 120 based upon continuation prereading information 123 and prefetches a necessary instruction or data by means of the continuation. An instruction pointer 227-1 out of the continuation preread based upon the information 123 is transferred to a high speed buffer memory monitoring part 211 in an instruction prefetching part 210. The monitoring part 211 inspects whether a buffer memory line including an instruction specified by the painter 227-1 is included in the high speed buffer memory or not based upon high speed buffer memory inspecting information 152. When the memory line is not included, a prefetch request issuing part 212 issues a prefetch request for the buffer memory line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor which is the core of a computer system, and more particularly to a high performance microprocessor capable of processing one program in parallel.

[0002]

2. Description of the Related Art In a processor, particularly a microprocessor, a high-speed buffer memory represented by a cache memory is utilized to store both instructions and data required for calculation in the high-speed buffer memory, and then to access this at high speed. It is common to perform the necessary processing.

If the desired instruction or data does not exist in the high-speed buffer memory (hereinafter, this case is referred to as a buffer memory miss), the desired instruction or data must be transferred from the main memory or the like. A long time is one of the factors that reduce the performance of the processor. The high speed buffer memory is composed of a plurality of buffer memory lines, and the above transfer due to a buffer memory miss is performed in units of the requested buffer memory line.

In order to solve the problem of performance deterioration due to the overhead of transfer processing in the case of a buffer memory miss, there is a conventional technique called prefetch. Here, the prefetch is to load necessary instructions or data into the high speed buffer memory in advance.

The following is a summary of the prior art relating to prefetching.

[1] It is a technique of preliminarily loading necessary data into a high-speed buffer memory in a software and explicit manner by a prefetch instruction.

The compiler uses this instruction to configure the program code so that necessary data is loaded into the high speed buffer memory in advance.

As an example of actually adopting such a technique, Digital Equipment Corp.
There is an alpha architecture announced by the corporation or the MC88110 architecture announced by Motorola.

[2] This is a technique for implementing prefetch by configuring a prefetch device with hardware.

Norman P. Juppi, "Im
proving Direct-Mapped Cac
he Performance by the Add
edition of a Small Fully-As
social Cache and Prefe
tch Buffers ”, The 17th Int
international Symposium on C
computer Architecture, IEEE
Computer Society Press, 1
990, pp. Some of 364-373 are called stream buffers.

This is a kind of prefetch buffer that has been known for a long time. When a certain instruction or data is accessed, subsequent instructions or data are serially accessed and stored in a stream buffer. That is. If the program behavior is serial, such a method can significantly improve the probability that a desired instruction or data exists in the high-speed buffer memory.

Similarly, there is a multi-thread type architecture as a conventional technique of the element processors constituting the parallel processing computer.

In the multithreaded architecture, a program is compiled into a plurality of threads that can be executed in parallel. Here, a thread is a sequence of instructions that are sequentially executed. These threads are distributed to the respective element processors that make up the parallel processing computer, and the respective processors execute arithmetic processing. At this time, the basic point of the multithreaded architecture is that multiple threads are assigned to one processor, and when waiting time such as inter-processor communication occurs, execution is switched to another thread and the waiting time is effectively used. Is an idea.

As a typical example of the multithreaded architecture, R. S. Nikhil, G .; M. Pap
adopoulos, Arvind, “* T: A Mu
lthreaded Massively Par
allell Architecture ", The19
th International Symposiu
m on Computer Architecture
e, IEEE Computer Society P
ress, 1992, pp. 156-167).

In a multithreaded architecture, the processor needs to be aware of which threads can execute. For this reason, it is common to have a buffer in the processor called the continuation buffer. Here, the continuation (or continuation) is a set of an instruction pointer indicating the head instruction address of the thread and a frame pointer designating the head address of a frame which is a data area used by the thread.

When the execution of the thread is started, the leading instruction of the thread is fetched according to the value of the instruction pointer. Subsequent instructions in the thread are fetched as specified by the program counter as usual. The data required to execute the instruction is fetched into the register from the frame designated by the frame pointer.

[0017]

The gist of the problem to be solved by the present invention in the above-mentioned conventional prefetch technique lies in the following two items.

[1] It is difficult to effectively insert a prefetch instruction into an instruction sequence during compilation, at least one cycle is consumed for issuing a prefetch instruction, and only data prefetch is performed. The problem is that it is effective for prefetching and cannot be used for prefetching instructions.

[2] Since it is assumed that the behavior of the program is serial, in many cases, there is a problem of prefetching useless instructions or data. This not only increases the miss rate of the high speed buffer memory, but also wastes the bandwidth between the main memory and the high speed buffer memory.

It is an object of the present invention to provide a processor having a continuation buffer, such as a multi-threaded architecture, which selects one of a plurality of executable continuations stored in the continuation buffer to execute arithmetic processing. On the other hand, another object of the present invention is to provide a control method of a processor that realizes a prefetch technique that takes advantage of the characteristics.

[0021]

The gist of means of the present invention for solving the above-mentioned problems lies in the following 6 items.

[1] Continuation buffer that stores an instruction pointer that specifies the address of the first instruction in an instruction string that is a series of executable instructions and a frame pointer that specifies a data storage area that stores data corresponding to the instruction string And a program counter for designating an address of an instruction currently being executed, and a high-speed buffer memory having a plurality of buffer memory lines for storing instructions and data, in the processor, the instruction stored in the continuation buffer. The pointer and the frame pointer corresponding to the instruction pointer are fetched, the instruction pointer is stored in the program counter, the instruction pointer stored in the program counter is fetched, and the instruction designated by the fetched instruction pointer Stores the first instruction in the row The instruction stored in the continuation buffer when the arithmetic operation in the instruction sequence starting from the first instruction is sequentially executed for the data storage area designated by the frame pointer. A method of controlling a processor, characterized in that the instruction sequence designated by a pointer is prefetched into the high-speed buffer memory in advance.

[2] The method of controlling a processor according to claim 1, wherein the length of the instruction string is limited to a length that can be stored in the buffer memory line that constitutes the high-speed buffer memory.

[3] Instruction sequence length information indicating the length of the instruction sequence is stored in the continuation buffer together with the instruction pointer, and corresponds to the instruction pointer and the instruction pointer stored in the continuation buffer. The processor control method according to claim 1, wherein all the buffer memory lines including the required instruction sequence are prefetched into the high-speed buffer memory in advance by using the instruction sequence length information.

[4] The processor according to claim 1, wherein the necessary data storage area is prefetched into the high-speed buffer memory in advance by using the frame pointer stored in the continuation buffer. Control method.

[5] A processor according to claim 4, wherein the size of the data area is limited so that the data area can be stored in the buffer memory line forming the high speed buffer memory. Control method.

[6] Frame size information indicating the size of the data area is stored in the continuation buffer together with the frame pointer, and the frame pointer stored in the continuation buffer and the frame pointer corresponding to the frame pointer are stored. The processor control method according to claim 1, wherein the required data area is prefetched into the high-speed buffer memory in advance using frame size information.

[0028]

1 is a block diagram showing an embodiment of a processor to which a control method according to the present invention is applied.

In FIG. 1, the processor 110 comprises a continuation buffer 120, a program counter 130, a high speed buffer memory 140, a prefetch device 150, an arithmetic execution device 160 and a register 170.

Hereinafter, referring to FIG. 1, the processor 1
An outline of the control method of 10 will be described. Continuation buffer 120
Stores a plurality of continuations each composed of a pair of an instruction pointer indicating the start instruction address of an executable thread and a frame pointer indicating a storage area of data corresponding to this instruction pointer. The continuation stored in the continuation buffer 120 is given from another processor using the continuation input information 111 or from the arithmetic execution unit 160 using the continuation storage information 161.

When the arithmetic execution unit 160 becomes able to execute a new thread, one is selected from the continuations stored in the continuation buffer 120, and the instruction pointer included in the selected continuation reads out the instruction pointer. It is read to the program counter 130 using the information 121. The instruction address notification information 131 specifies the address of the instruction to be executed in the high speed buffer memory 140 according to the value of the instruction pointer read, and the specified instruction is sent to the arithmetic execution unit 160 using the instruction transfer information 141. It is read and executed.

The frame pointer included in the continuation selected from the continuation buffer 120 is read to the arithmetic execution unit 160 using the frame pointer read information 122. If there is an instruction to access the memory in the thread starting from the instruction specified by the instruction pointer, the address of the data is calculated using the frame pointer,
The high speed buffer memory 140 is notified using the data address notification information 162. The data transfer information 142 is used to transfer the data between the register 170 and the high speed buffer memory 140.

When the required instruction or data does not exist in the high speed buffer memory 140, the instruction or data is transferred from the main memory 180 to the high speed buffer memory 140 using the data transfer information 181. The high speed buffer memory is composed of a plurality of buffer memory lines, and includes the main memory 180 and the high speed buffer memory 1 described above.
The transfer between 40 is performed in units of this buffer memory line. The prefetch device 150 reads the continuation stored in the continuation buffer using the continuation readahead information 123, uses the instruction pointer or frame pointer in the read continuation, respectively, and prefetches the instruction or data using the prefetch request information 151. Request to the main memory 180.

FIG. 2 is a detailed block diagram of the prefetch device 150 and the continuation buffer 120 for explaining the first embodiment of the control method for the embodiment of the processor 110 of FIG. In FIG. 2, the prefetch device 150 of the present invention comprises an instruction prefetch unit 210, a data prefetch unit 220 and an arbitrator 230.

The instruction prefetch unit 210 and the data prefetch unit 220 respectively include a high speed buffer memory monitor unit 211 and 221 and a prefetch request issuing unit 212, respectively.
It is composed of 222. Further, the continuation buffer 120 stores n from continuation (1) 226-1 to continuation (n) 226-n.
Store the number of continuations (n is a positive integer). Each continuation is indicated by an instruction pointer 227-1 and a frame pointer 227-1.
It consists of two.

As an example of the method of configuring the continuation buffer 120, there is a method of configuring it as a FIFO (first in first out) type queue. That is, the continuation input from the continuation input information 111 or the continuation storage information 161 is input to the tail of the queue and sequentially sent toward the head of the queue. When the continuation is taken out for the execution of the thread, it is read from continuation (1) 226-1 at the head of the queue by using the instruction pointer read information 121 and the instruction pointer read information 122.

A first embodiment of the processor control method according to the present invention will be described below with reference to FIG.

The prefetch device 150 uses the continuation prefetch information 123 to prefetch a continuation to be executed in the future from the continuation buffer 120, and uses this to prefetch necessary instructions or data.

As an example of a method of prefetching from the continuation buffer, a method of performing it when the continuation reaches the head of the queue, or the m-th from the head (m is a positive integer less than or equal to n)
There is a method such as prefetching for continuation until. The instruction pointer 227-1 of the continuation prefetched using the continuation prefetch information 123 is transferred to the high-speed buffer memory monitor unit 211 in the instruction prefetch unit 210.

The high speed buffer memory monitor unit 211 uses the high speed buffer memory inspection information 152 to inspect whether or not the buffer memory line including the instruction designated by the instruction pointer 227-1 is included in the high speed buffer memory. If not included, the prefetch request issuing unit 21
2 issues a prefetch request for that buffer memory line. The frame pointer 227-2 of the prefetched continuation is transferred to the high speed buffer memory monitor unit 221 in the data prefetch unit.

The high speed buffer memory monitor 221 uses the high speed buffer memory inspection information 152 to inspect whether or not the buffer memory line including the head address of the frame designated by the frame pointer 227-2 is included in the high speed buffer memory. . If it is not included, the prefetch request issuing unit 222 issues the prefetch request for the block. When prefetch requests from the instruction prefetch unit 210 and the data prefetch unit 220 occur at the same time, the arbitrator 230 arbitrates between them and uses the prefetch request information 151 to request prefetch from the main memory 180. As an example of the arbitration method, the instruction prefetch unit 21
There is a method in which the prefetch request from 0 is always prioritized.

In the first embodiment of the control method described above, the prefetched buffer memory line contains the instruction specified by the instruction pointer 227-1 or the data specified by the frame pointer 227-2. Is guaranteed, all threads starting from the instruction specified by the instruction pointer 227-1 or the frame pointer 22
It is not guaranteed to include all the frames specified in 7-2. Therefore, during execution of the thread, the necessary instruction or data may not exist in the high speed buffer memory 140.

A second method of controlling a processor according to the present invention
In order to improve such a point, in addition to the first embodiment of the control method of the processor, the embodiment of the above-mentioned method of the thread or the frame of the thread or frame is included in one buffer memory line. It limits the size. Thus, by prefetching the buffer memory line according to the designation of the instruction pointer 227-1 or the frame pointer 227-2, all the instructions and data of the thread are prefetched to the high speed buffer memory 140 before the execution of the thread. Will be possible.

FIG. 3 is a detailed block diagram of the continuation buffer 120 for explaining the third embodiment of the control method for the embodiment of the processor 110 of FIG. In FIG. 3, the continuation buffer 120 stores n (n is a positive integer) continuations from continuation (1) 326-1 to continuation (n) 326-n. Each continuation is an instruction pointer 327
-1, frame pointer 327-2, thread length information 3
27-3 and frame size information 327-4.

The third embodiment is characterized in that the continuation includes thread length information 327-3 indicating the thread length and frame size information 327-4 indicating the frame size. The prefetch device 150 uses these pieces of information to perform the following prefetch operation. First, when prefetching an instruction, all buffer memory lines including the thread are calculated using the instruction pointer 327-1 and the thread length information 327-3. Whether or not the buffer memory line found as a result of the calculation is stored in the high speed buffer memory 140 is sequentially inspected using the high speed buffer memory inspection information 152, and if not included, the prefetch requests are sequentially issued.

When prefetching data, all the buffer memory lines including the frame are calculated using the frame pointer 327-2 and the frame size information 327-4. Whether or not the buffer memory line found as a result of the calculation is stored in the high speed buffer memory 140 is sequentially inspected using the high speed buffer memory inspection information 152, and if not included, the prefetch requests are sequentially issued. This allows all instructions and data of a thread to be prefetched into the high speed buffer memory 140 before execution of the thread.

[0047]

According to the processor control method of the present invention, an effective prefetch technique can be applied to a processor adopting a continuation buffer such as a multithreaded architecture or a mechanism similar to it by a simple hardware configuration. Can be provided.

In particular, when the thread to be executed next is uniquely determined in advance, such as when the continuation buffer is configured as a FIFO queue, the prefetch technique provided by the processor control method according to the present invention is It is possible to surely prefetch not only the data necessary for the execution of the next thread but also the instruction without prefetching useless instructions or data.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a processor for illustrating a method of controlling a processor according to the present invention.

FIG. 2 is a block diagram showing a configuration of a continuation buffer and a prefetch device in FIG.

3 is a block diagram showing a configuration of a continuation buffer in FIG. 1. FIG.

[Explanation of symbols]

110 Processor 111 Continuation Input Information 120 Continuation Buffer 121 Instruction Pointer Readout Information 122 Frame Pointer Readout Information 123 Continuation Lookahead Information 130 Program Counter 131 Instruction Address Notification Information 140 High Speed Buffer Memory 142 Data Transfer Information 150 Prefetch Device 151 Prefetch Request Information 152 High Speed Buffer memory check information 160 Operation execution device 161 Continuous storage information 162 Data address notification information 170 Register 180 Main memory 181 Data transfer information 210 Instruction prefetch unit 220 Data prefetch unit 226-1, ..., 226-n Continuation (1), ..., Continuation (n) 227-1 Instruction pointer 227-2 Frame pointer 230 Arbitrator 211,221 High speed buffer memory monitor Part 212,222 Prefetch request issuing part 226 Continuation 326 Continuation 326-1, ..., 326-n Continuation (1), ..., Continuation (n) 327-1 Instruction pointer 327-2 Frame pointer 327-3 Thread length information 327- 4 Frame size information

Claims (6)

[Claims] 1. A continuation buffer for storing an instruction pointer for designating an address of a first instruction in an instruction sequence which is a series of executable instructions and a frame pointer for designating a data storage area for storing data corresponding to the instruction sequence. A processor having a program counter for designating an address of an instruction currently being executed and a high speed buffer memory having a plurality of buffer memory lines for storing instructions and data, wherein the instruction pointer stored in the continuation buffer And fetching the frame pointer corresponding to the instruction pointer, storing the instruction pointer in the program counter, fetching the instruction pointer stored in the program counter, and based on the instruction of the fetched instruction pointer, The first instruction of the instruction sequence is stored The instruction stored in the continuation buffer when sequentially executing the arithmetic processing in the instruction sequence starting from the first instruction to the data storage area specified by the frame pointer A method of controlling a processor, characterized in that the instruction sequence designated by a pointer is prefetched into the high-speed buffer memory in advance. 2. The method of controlling a processor according to claim 1, wherein the length of the instruction sequence is limited to a length that can be stored in the buffer memory line that constitutes the high speed buffer memory. 3. The instruction string length information indicating the length of the instruction string is stored in the continuation buffer together with the instruction pointer, and the instruction pointer stored in the continuation buffer and the instruction pointer corresponding to the instruction pointer. 2. The processor control method according to claim 1, wherein all the buffer memory lines including the required instruction sequence are prefetched into the high-speed buffer memory in advance using the instruction sequence length information. 4. The control of the processor according to claim 1, wherein the necessary data storage area is prefetched into the high-speed buffer memory in advance by using the frame pointer stored in the continuation buffer. Method. 5. The control of the processor according to claim 4, wherein the size of the data area is limited so that the data area can be stored in the buffer memory line forming the high speed buffer memory. Method. 6. Frame size information indicating a size of the data area is stored in the continuation buffer together with the frame pointer, and the frame pointer stored in the continuation buffer and the frame corresponding to the frame pointer. 2. The size information is used to prefetch the required data area into the high-speed buffer memory in advance.
The method of controlling the processor according to.