JPH0756481Y2 - Bias network - Google Patents

Bias network

Info

Publication number
JPH0756481Y2
JPH0756481Y2 JP1987185103U JP18510387U JPH0756481Y2 JP H0756481 Y2 JPH0756481 Y2 JP H0756481Y2 JP 1987185103 U JP1987185103 U JP 1987185103U JP 18510387 U JP18510387 U JP 18510387U JP H0756481 Y2 JPH0756481 Y2 JP H0756481Y2
Authority
JP
Japan
Prior art keywords
frequency signal
bias network
high frequency
signal
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987185103U
Other languages
Japanese (ja)
Other versions
JPH0188503U (en
Inventor
準一 下田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1987185103U priority Critical patent/JPH0756481Y2/en
Publication of JPH0188503U publication Critical patent/JPH0188503U/ja
Application granted granted Critical
Publication of JPH0756481Y2 publication Critical patent/JPH0756481Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Waveguides (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は高周波信号線に直流大電流を印加できるバイア
スネットワークに関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a bias network capable of applying a large DC current to a high-frequency signal line.

〔従来の技術〕[Conventional technology]

従来の高周波信号に直流信号を重畳するバイアスネット
ワークは、第3図の部分断面による正面図に示される。
端子31,32の間の高周波信号の伝送に、中心導体1を含
む同軸線路が用いられ、端子4から供給される直流信号
が一方の端子31にのみ出力されるように、中心導体1の
端子32側の規定の位置に絶縁体2が挟まれている。直流
信号は、直流入力端子4から導体5を介して中心導体1
へ印加される。
A conventional bias network for superimposing a direct current signal on a high frequency signal is shown in a front view in partial section in FIG.
A coaxial line including the center conductor 1 is used to transmit a high-frequency signal between the terminals 31 and 32, and the DC signal supplied from the terminal 4 is output only to one of the terminals 31 so that the terminals of the center conductor 1 can be output. The insulator 2 is sandwiched at a specified position on the 32 side. The DC signal is transmitted from the DC input terminal 4 through the conductor 5 to the center conductor 1
Is applied to.

〔考案が解決しようとする問題点〕[Problems to be solved by the invention]

このような従来のバイアスネットワークは、高周波伝送
線路のインピーダンスに比べて直流線路のインピーダン
スを高くするため、極力細い導線を直流入力線5に用い
ている。例えば、高周波半導体素子の高周波特性を測定
する時に、5A前後の直流電流を必要とする場合、直流入
力端子4から印加できる電流容量が小さいため、この入
力端子(4)を複数個備えたバイアスネットワークがあ
る。しかし、外形寸法の制限や直流入力点の増加によ
り、高周波信号へ及ぼす悪影響が増加する欠点がある。
In such a conventional bias network, in order to make the impedance of the DC line higher than the impedance of the high frequency transmission line, a conductor as thin as possible is used for the DC input line 5. For example, when a DC current of about 5 A is required when measuring the high frequency characteristics of a high frequency semiconductor device, the current capacity that can be applied from the DC input terminal 4 is small, so a bias network having a plurality of this input terminal (4) is provided. There is. However, there is a drawback that the adverse effect on the high frequency signal increases due to the limitation of the external dimensions and the increase of the DC input points.

本考案の目的は、このような欠点を除き、直流入力線に
直流大電流を印加できるようにしたバイアスネットワー
クを提供することにある。
An object of the present invention is to eliminate the above drawbacks and to provide a bias network capable of applying a large DC current to a DC input line.

〔問題点を解決するための手段〕[Means for solving problems]

本考案の構成は、高周波信号を伝送する中心導体に高周
波信号の入出力端子を接続し、前記中心導体に直流信号
を印加する直流入力線を接続したバイアスネットワーク
において、前記直流入力線に挿入され円筒形の絶縁体か
らなる整合回路を設け、この整合回路と前記中心導体と
の距離を可変してインピーダンス整合できるようにした
ことを特徴とする。
The structure of the present invention is inserted into the DC input line in a bias network in which a high frequency signal input / output terminal is connected to a center conductor that transmits a high frequency signal and a DC input line that applies a DC signal is connected to the center conductor. A matching circuit made of a cylindrical insulator is provided, and the distance between the matching circuit and the central conductor can be varied to perform impedance matching.

〔実施例〕〔Example〕

次に、本考案を図面により詳細に説明する。 Next, the present invention will be described in detail with reference to the drawings.

第1図は本考案の一実施例を示す断面図である。端子3
1,32の間の高周波伝送路に中心導体1の途中に絶縁体2
を挟んだ同軸線路を用いており、高周波信号は端子32か
ら入力され、中心導体1を通り端子32へ出力される。一
方、直流信号は直流入力端子4から導線5を介して中心
導体1へ印加されるが、直流信号を端子32のみに出力す
るため中心導体1に絶縁体2を設けている。この場合、
直流入力線5に高周波特性のすぐれた円筒状の絶縁体6
を挿入して、中心導体1と絶縁体6との間の距離Lを調
整することにより、中心導体1と直流入力線5とのイン
ピーダンスの整合がとられるようになっている。すなわ
ち、従来の直流用導線5に比べて太い径の導線を用いる
ので絶縁体6を設けて高周波回路の整合がとれるように
して高周波信号への悪影響を除いている。
FIG. 1 is a sectional view showing an embodiment of the present invention. Terminal 3
Insulator 2 in the middle of the central conductor 1 in the high frequency transmission line between 1,32.
A high-frequency signal is input from the terminal 32, passes through the central conductor 1, and is output to the terminal 32. On the other hand, a DC signal is applied to the central conductor 1 from the DC input terminal 4 through the conductor 5, but an insulator 2 is provided on the central conductor 1 to output the DC signal only to the terminal 32. in this case,
Cylindrical insulator 6 with excellent high frequency characteristics for DC input line 5
By adjusting the distance L between the central conductor 1 and the insulator 6 by inserting, the impedance of the central conductor 1 and the DC input line 5 can be matched. That is, since a conductor wire having a diameter larger than that of the conventional direct-current conductor wire 5 is used, the insulator 6 is provided so that the high-frequency circuit can be matched and the adverse effect on the high-frequency signal is eliminated.

第2図は本考案に関連する高周波信号分離回路の一例部
分断面正面図である。本回路例は同軸線路の高周波信号
の分離において、高周波信号を端子31から印加し端子3
2,33へ出力する場合であるが、信号分離点ではインピー
ダンスが変化する。このインピーダンスの変化点におい
て高周波信号の反射や損失を生じる。
FIG. 2 is a partial sectional front view of an example of a high frequency signal separation circuit related to the present invention. This circuit example applies a high-frequency signal from the terminal 31 to separate the high-frequency signal on the coaxial line from the terminal 3
In the case of outputting to 2,33, the impedance changes at the signal separation point. The high frequency signal is reflected or lost at this impedance change point.

本回路例では信号分離点と端子32,33との間に、インピ
ーダンスの整合を行う絶縁体7を中心導体1に設けてお
り、絶縁体7と信号分離点の距離L1,L2を調整すること
によりインピーダンスの整合を計っている。
In this circuit example, the insulator 7 for impedance matching is provided in the center conductor 1 between the signal separation point and the terminals 32 and 33, and the distances L 1 and L 2 between the insulator 7 and the signal separation point are adjusted. By doing so, impedance matching is measured.

この回路例では任意の高周波信号に対してインピーダン
スの調整が可能であるため、広い周波数範囲で高周波信
号の分離ができる利点がある。
In this circuit example, the impedance can be adjusted with respect to an arbitrary high frequency signal, so that there is an advantage that the high frequency signal can be separated in a wide frequency range.

〔考案の効果〕[Effect of device]

以上説明したように本考案によれば、高周波信号への悪
影響を除くように、直流入力線路に整合回路を付加して
インピーダンスの整合を行っているので、直流大電流を
必要とする高周波部分に対して、規定の高周波及び直流
信号を印加することができる。
As described above, according to the present invention, a matching circuit is added to the DC input line to perform impedance matching so as to eliminate adverse effects on high-frequency signals. On the other hand, prescribed high frequency and DC signals can be applied.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の一実施例を部分断面で示した正面図、
第2図は本考案に関連する高周波信号分離回路の一例を
部分断面で示した正面図、第3図は従来のバイアスネッ
トワークの一例を示す部分断面の正面図である。 1…同軸線路中心導体、2,6,7…絶縁体、31,32,33…高
周波信号入出力端子、4…直流入力端子、5…直流入力
線、L…絶縁体6と中心導体1の距離、L1,L2…信号分
離点と絶縁体7の距離。
FIG. 1 is a front view showing an embodiment of the present invention in a partial cross section,
FIG. 2 is a front view showing an example of a high frequency signal separation circuit related to the present invention in a partial cross section, and FIG. 3 is a front view of a partial cross section showing an example of a conventional bias network. 1 ... Coaxial line center conductor, 2, 6, 7 ... Insulator, 31, 32, 33 ... High frequency signal input / output terminal, 4 ... DC input terminal, 5 ... DC input line, L ... Insulator 6 and center conductor 1 Distance, L 1 , L 2 ... Distance between signal separation point and insulator 7.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】高周波信号を伝送する中心導体に高周波信
号の入出力端子を接続し、前記中心導体に直流信号を印
加する直流入力線を接続したバイアスネットワークにお
いて、前記直流入力線に挿入され円筒形の絶縁体からな
る整合回路を設け、この整合回路と前記中心導体との距
離を可変してインピーダンス整合できるようにしたこと
を特徴とするバイアスネットワーク。
1. A cylinder inserted into the DC input line in a bias network in which a high-frequency signal input / output terminal is connected to a center conductor for transmitting a high-frequency signal, and a DC input line for applying a DC signal is connected to the center conductor. A bias network, wherein a matching circuit made of an insulating material is provided, and a distance between the matching circuit and the central conductor is varied so that impedance matching can be performed.
JP1987185103U 1987-12-03 1987-12-03 Bias network Expired - Lifetime JPH0756481Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987185103U JPH0756481Y2 (en) 1987-12-03 1987-12-03 Bias network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987185103U JPH0756481Y2 (en) 1987-12-03 1987-12-03 Bias network

Publications (2)

Publication Number Publication Date
JPH0188503U JPH0188503U (en) 1989-06-12
JPH0756481Y2 true JPH0756481Y2 (en) 1995-12-25

Family

ID=31476431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987185103U Expired - Lifetime JPH0756481Y2 (en) 1987-12-03 1987-12-03 Bias network

Country Status (1)

Country Link
JP (1) JPH0756481Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62196901A (en) * 1986-02-25 1987-08-31 Sumitomo Electric Ind Ltd Bias superposing device for microstrip line

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62196901A (en) * 1986-02-25 1987-08-31 Sumitomo Electric Ind Ltd Bias superposing device for microstrip line

Also Published As

Publication number Publication date
JPH0188503U (en) 1989-06-12

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