JPH0755856A - Cycle measuring apparatus - Google Patents

Abstract

PURPOSE:To measure the cycle of a horizontal synchronizing signal at a small error and with good accuracy even when it is long by a method wherein the number of times in which a third signal has been activated is measured during a prescribed measuring period prescribed by a first signal. CONSTITUTION:The number of internal pulses IP during a prescribed measuring period tM prescribed by a horizontal synchronizing signal HS is measured. Cycles of the signal HS and the pulses IP are designated respectively as TH and TS, and the period tM is set as one cycle of a frequency-dividing signal NS obtained by frequency-dividing the signal HS into N. When the pulses IP are activated K times within the period tM, the cycle TH of the signal HS is found. In this case, a certain error epsilon is caused. After the start of the period tM and during the Kth activation and the (K+1)th activation of the pulses IP, the signal NS is transferred, and the period tM is finishes. Thereby, TS.K<tM<TS.(K+1) is established. However, since tM=TH.N, the error epsilon does not depend on the number of times K in which the pulses IP are activated during the period tM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for measuring the cycle of a signal which is periodically activated, and more particularly to an apparatus for measuring the cycle of a horizontal synchronizing signal in a video signal and an image signal.

[0002]

2. Description of the Related Art Conventionally, as a display monitor of a computer, there has been a multi-scan type monitor which performs display based on video signals from a plurality of computers. Here, the periods of the horizontal synchronizing signal and the vertical synchronizing signal in the video signal are not always the same among a plurality of computers. Therefore, it is necessary to change the setting inside the display monitor in accordance with the video signal of each computer. Specifically, it was necessary to measure the cycle of the horizontal synchronizing signal and make settings corresponding to this cycle.

This horizontal sync signal may be configured to be lost during the vertical blanking time, especially during the vertical sync period. Even in such a case, the period of the horizontal synchronizing signal needs to be measured.

FIG. 22 is a block diagram showing the structure of a conventional period measuring apparatus 200, and FIG. 23 is a timing chart showing its operation. The cycle measuring device 200 can measure the cycle of the horizontal sync signal that is configured to be missing during the vertical sync period.

A horizontal synchronizing signal HS and a vertical synchronizing signal VS are given to the microcomputer 1. The microcomputer 1 includes an internal pulse oscillator 2 that generates an internal pulse IP and an internal counter 3. The internal pulse IP depends on the system clock that serves as a reference for the operation of the microcomputer 1.

The horizontal synchronizing signal HS is activated several times between adjacent activated vertical synchronizing signals VS. The cycle measuring device 200 measures how many times the horizontal synchronizing signal HS is activated in a constant measurement period t _m .

Specifically, the measurement period t _m starts after a certain waiting time t _w has elapsed after the vertical synchronizing signal VS was activated. The measurement period t _m and the waiting time t _w are both set based on the internal pulse IP, and are set to, for example, 1
It is set to ms and 5 ms. Then, the internal counter 3 measures the number of pulses of the horizontal synchronizing signal HS activated within the measurement period t _m .

When the count value of the number of pulses of the horizontal synchronizing signal HS measured within the measuring period t _m is C, the period of the actual horizontal synchronizing signal HS is set to T _H and the equation (1) is used. Is established.

T _m / (C + 1) < _TH <t _m / C (1) Therefore, the error in the period measurement of the horizontal synchronizing signal HS of the period measuring device 200 is ε = t _m / C-t _m / (C + 1) ... (2).

[0010]

BRIEF Problem to be Solved] Thus, in the conventional art, the count value C greater the period T _H of the horizontal synchronizing signal HS becomes longer decreases, there is a problem that error ε is increases It was Especially, when the measurement period t _m becomes short, this occurs remarkably.

[0011] For example, when the measurement period t _m is 5 ms, the period T _H of the horizontal synchronizing signal HS was 1 / (60 kHz), the error ε is 55 ns. However, if the period T _H of the horizontal synchronizing signal HS is 1 / (30 kHz), the error ε will be four times 220 ns.

Moreover, assuming that the measurement period t _m is 1 ms,
Even if the period T _H of the horizontal synchronizing signal HS was 1 / (60kHz), the error ε is 4.9 times the 270Ns.

The present invention has been made to solve the above problems, and an object thereof is to obtain a cycle measuring apparatus capable of accurately measuring the error even if the cycle T _H of the horizontal synchronizing signal HS is long. And

[0014]

A cycle measuring apparatus according to the present invention is a cycle measuring apparatus for measuring a cycle of a first signal which is periodically activated, and has a period larger than that of the first signal. An input terminal for inputting a second signal having a predetermined relationship with the first signal, (b) an oscillator for generating a third signal having a shorter period than the first signal, and (c) the second
A first counter for measuring the number of times the third signal is activated in a measurement period determined by the signal; and (d) the first counter.
Arithmetic means for obtaining the cycle of the first signal from the output of the counter, the cycle of the third signal, and the predetermined relationship.

Here, the predetermined relationship means that the period of the second signal is an integer N times the period of the first signal, for example.

Preferably, (e) a frequency divider is further provided, which divides the first signal by N to generate the second signal and supplies the second signal to the input terminal.

For example, the first signal is active at least when the periodically activating fourth signal is inactive, and the frequency divider is given a second value whose initial value is given by the activated fourth signal. It has a counter. And the second
The signal is obtained as the output of the second counter.

The measurement period is preferably an integral multiple of half of one cycle of the second signal, and preferably corresponds to one cycle or half cycle of the second signal, for example.

Further, (f) latch means for holding the output of the first counter, and (g) reading means for inputting the output of the latch means are further provided, and the fourth signal is activated from inactive state. The first transition to is a trigger for resetting the first counter and holding the latching means,
The first counters can also perform the measurement only between transitions of the second signals that are adjacent to each other and have different directions.

Preferably, during the period in which the fourth signal is continuously inactive, the second signal makes only two transitions in different directions.

[0021]

The first counter of the present invention measures the number of times the third signal is activated in the measurement period determined by the second signal. The second signal has a predetermined relationship with the first signal. For example, the cycle is an integer N times the cycle of the first signal.

The measurement period is equal to one cycle of the second signal,
If the period of the third signal is T _S and the third signal is activated K times during the measurement period, the period of the second signal is measured as T _S · K / N.

[0023]

【Example】

A. Basic concept: Before entering a detailed description of the present invention, the basic concept of the present invention will be described.

In the conventional technique, the number of pulses of the horizontal synchronizing signal HS in the fixed measurement period t _m defined by the internal pulse IP is measured, whereas in the present invention, the predetermined measurement defined by the horizontal synchronizing signal HS is measured. The number of internal pulses IP in the period t _M is measured. Here, the measurement period t _M can be set by dividing the horizontal synchronization signal HS by N.

FIG. 1 is a conceptual diagram showing the basic idea of the present invention. Further, FIG. 2 is a conceptual diagram in which a part Z of FIG. 1 is enlarged. It is assumed that the periods of the horizontal synchronizing signal HS and the internal pulse IP are T _H and T _S , respectively, and the measurement period t _M is set to one period of the divided signal NS obtained by dividing the horizontal synchronizing signal HS by N. . As shown in FIG. 1, when the period T _H of the horizontal synchronizing signal HS is obtained from the case where the internal pulse IP is activated K times within this measurement period t _M ,
An error ε occurs.

As shown in FIG. 2, after the start of the measurement period t _M , the Kth activation of the internal pulse IP and (K + 1)
During the activation of the second time, the divided signal NS makes a transition and the measurement period t _M ends. Therefore, the equation (3) is established.

T _S · K <t _M <T _S · (K + 1) (3) However, since t _M = T _H · N, the error ε is ε = T _S · (K + 1) / N−T _S · K / N = T _S / N (4) Here, the error ε does not depend on the number of activations K of the internal pulse IP in the measurement period t _M.

Therefore, unlike the error ε in the conventional technique expressed by the equation (2), the period T _{H of the} horizontal synchronizing signal HS is
The error .epsilon. Does not increase even if .alpha. Becomes long and the value of K becomes small. For example, when the frequency division value is set to N = 256 and the cycle of the internal pulse IP is set to T _S = 1 μs,
The error ε is 3.9 ns, and the horizontal synchronization signal H is highly accurate.
It can be seen that the period T _H of S can be measured.

Specific configurations of the embodiments based on the above basic concept will be individually described in detail below.

B. Specific Structure of Embodiment: (B-1) First Embodiment: FIG. 3 is a block diagram showing the structure of a cycle measuring apparatus 101 according to the first embodiment of the present invention. The cycle measuring device 101 includes a frequency divider 4. The horizontal synchronizing signal HS and the vertical synchronizing signal VS are input to the frequency divider 4, and the horizontal synchronizing signal HS is divided by N to output a divided signal NS. The frequency divider 4 is reset by the vertical synchronization signal VS.

The cycle measuring device 101 also includes a microcomputer 1. The microcomputer 1 has an internal pulse oscillator 2 that generates an internal pulse IP, and an internal counter 3. The internal counter 3 measures the number K of times the internal pulse IP is activated in the measurement period t _M corresponding to one cycle of the divided signal NS.

FIG. 4 is a timing chart for explaining the operation of the cycle measuring apparatus 101. The frequency divider 4 reset by the "H" level of the vertical synchronizing signal VS divides the horizontal synchronizing signal HS by N to generate a divided signal NS. FIG. 5 is a circuit diagram showing a configuration example of the frequency dividing circuit 4a that can be used for the frequency divider 4. T flip-flop 4 ₁ ,
4 _2, 4 _3, ..., 4 _n are a connected in series, T flip-flop 4 _2, 4 _3, ..., 4 to the _n clock input terminal T, Q ¯ of each preceding stage Output is given. The horizontal synchronizing signal HS is applied to the clock input terminal T of the T flip-flop 4 ₁ . The vertical synchronizing signal VS is applied to the reset terminals R of all the T flip-flops 4 ₂ , 4 ₃ , ..., 4 _n .

By using the frequency ^dividing circuit 4a thus constructed in the frequency divider 4, it is reset by the "H" level of the vertical synchronizing signal VS, and the horizontal synchronizing signal HS is divided by 2 ⁿ to obtain a divided signal NS. Can be obtained from the Q output of the T flip-flop 4 _n . Since the inverted Q output is given to the clock input terminal T of the next stage, the rising edge of the horizontal synchronizing signal HS should be counted 2 ^(n-1) times and the divided signal NS should rise and fall by 2 ^n. become.

Returning to FIGS. 3 and 4, the counter 3 sets the measurement period t _M from the first rising of the divided signal NS after the vertical synchronizing signal VS is inactivated to the next rising,
The number of activations of the internal pulse IP during this period is measured. Divided signal NS is, when the horizontal synchronizing signal HS of the period T _H divided by N, the measurement period t _M is equal to N · T _H. Further, since the frequency-divided signal rises after counting the rising of the horizontal synchronizing signal HS 2 ^(n-1) times, the time from the deactivation of the vertical synchronizing signal VS to the first rising of the horizontal synchronizing signal HS is w. Then, the measurement period t _M is
Wait time F = (t after the vertical synchronization signal VS is deactivated
It will start after _M / 2- _TH + w).

FIG. 6 is a flowchart showing the operation of the cycle measuring apparatus 101. The procedure shown in this flowchart is controlled by the microcomputer 1.

First, in step S1, it is determined whether or not the vertical synchronizing signal VS is input to the microcomputer 1. If it has not been input, the determination in step S1 is repeated. And the vertical sync signal V
When it is determined that S is input, the internal counter 3 is reset in step S2.

Then, in step S3, the divided signal NS
It is determined whether or not the rising edge of is detected. If it has not been detected yet, the determination in step S3 is repeated. When it is determined that the rising edge of the divided signal NS is detected, the internal counter 3 starts counting the internal pulse IP by step S4.

After that, it is judged again in step S5 whether or not the rising edge of the divided signal NS is detected. If it has not been detected yet, the determination in step S5 is repeated. During this period, the internal counter 3 continues to count the internal pulse IP.

If it is determined in step S5 that the rising edge of the divided signal NS is detected, step S5
6, the counting of the internal pulse IP by the internal counter 3 is completed. The period from the determination of “YES” in step S3 to the determination of “YES” in step S6 corresponds to the measurement period t _M. The number of times K of activating the internal pulse is obtained by the counting by the internal counter 3 up to this point.

Then, in step S7, the period of the horizontal synchronizing signal HS is obtained. Specifically, T = T _S · K / N
Is required as. As shown in equation (4), the error ε between the period T _H of the true horizontal sync signal HS is suppressed to less than T _S / N.

Since the cycle measuring apparatus 101 is constructed and operates as described above, even if the cycle of the horizontal synchronizing signal HS is long, as described in "A. Basic concept",
This can be measured accurately.

In the first embodiment, the vertical synchronizing signal VS has a positive polarity (active and inactive correspond to "H" and "L", respectively), and the frequency divider 4 is reset vertically. The case where the synchronization signal VS is at "H" level is shown. However, when the vertical synchronizing signal VS has a negative polarity (active and inactive correspond to “L” and “H”, respectively), the frequency divider 4 can be reset at the “L” level. .

In this case, as shown in FIG. 7, the T flip-flop 4 is reset by the signal of "L" level.
_{1 ', 4 2', 4} 3 ', ..., 4 n' can be used constituted divider 4b in series connection. FIG. 8 is a timing chart showing the operation of the cycle measuring apparatus 101 in such a case.

Since the measurement period t _M is determined in the same manner as the operation shown in FIG. 4, even if the period of the horizontal synchronizing signal HS is long, it can be accurately measured.

(B-2) Second Embodiment: In the first embodiment,
In steps S3 and S5 shown in FIG. 6, it is judged whether or not the rising edge of the divided signal NS is detected, but whether or not the falling edge of the divided signal NS is detected in steps S3 and S5. May be judged. This is because the lengths of the measurement periods t _M are equal in this case as well.

When the measurement period t _M is determined by the fall of the divided signal NS, the divided signal is divided so that the value of the divided signal NS becomes “H” level immediately after the vertical synchronizing signal VS is deactivated. It is desirable to configure the container 4. If frequency dividers 4a and 4b are used for frequency divider 4, vertical synchronizing signal VS
Immediately after the deactivation, the value of the divided signal NS is "L".
If it becomes the level, the waiting time F until the divided signal NS first falls after the vertical synchronizing signal VS is deactivated must be one cycle or more of the divided signal NS. That is, in order to secure the measurement period t _M , the period of the vertical synchronizing signal VS needs to be at least twice the period of the divided signal NS.

Therefore, in the video signal generated by the computer connected to the monitor, the vertical synchronizing signal VS
If the period of is short, the value of the frequency division value N must be reduced. On the other hand, as shown in the equation (4), the measurement error ε is inversely proportional to N. Therefore, when the frequency division value N is decreased, the measurement error ε increases.

FIG. 9 is a circuit diagram showing the configuration of the frequency dividing circuit 4c which is preferably used when the measurement period t _M is determined by the fall of the frequency divided signal NS. Here, similar to FIG. 5, the configuration in the case where the vertical synchronizing signal VS is reset by being at the “H” level is shown, but FIG.
Similarly, the T flip-flops 4 ₁ ′, 4 ₂ ′, 4 ₃ ′, ..., 4 _n ′ having a reset terminal which is reset when the signal becomes “L” level as shown in FIG. can do.

The frequency dividing circuit 4c is the same as the frequency dividing circuit 4a except for one point. The only difference is that the divided signal NS is obtained from the inverted Q output of the T flip-flop 4 _n .

FIG. 10 is a timing chart showing how the period of the horizontal synchronizing signal HS is measured in the second embodiment. As in the case of the first embodiment shown in FIG. 4, the waiting time F is (t _M / 2-T _H + w). Therefore, even when the measurement period t _M is determined by the fall of the divided signal NS, and even when the period of the vertical synchronizing signal VS is short, the horizontal synchronizing signal can be accurately measured without decreasing the divided value N. The period of HS can be measured.

(B-3) Third Embodiment: As described in the second embodiment, when the period of the vertical synchronizing signal VS is short, the frequency division value N must be reduced.
This is because the horizontal sync signal HS may be missing near the time when the vertical sync signal VS is activated. In the third embodiment, by advancing the start time of the measurement period t _M , even if the cycle of the vertical synchronizing signal VS is short, the horizontal synchronizing signal HS can be accurately measured without decreasing the frequency division value N.
To measure the period.

The structure of the cycle measuring apparatus according to the third embodiment is shown in FIG. 3 as in the first and second embodiments. However, in the third embodiment, the configuration of the frequency divider 4 is different from these.

FIG. 11 is a circuit diagram showing a configuration of a frequency dividing circuit 4d which is preferably used for the frequency divider 4 in the third embodiment. The frequency dividing circuit 4d is the same as the frequency dividing circuit 4a except for one point. The difference is that the T flip-flop 4 in the kth stage
_With respect to _k , the vertical synchronizing signal VS is not input to the reset terminal but is input to the set terminal S.

All the T flip-flops 4 ₂ , 4 ₃ , ..., 4 _n except the T flip-flop 4 _k are reset by the "H" level of the vertical synchronizing signal VS. Then, only the T flip-flop 4 _k is set (preset). Therefore, the preset value of the frequency dividing circuit 4d is 2
^(k-1) , and the rising edge of the horizontal sync signal HS becomes 2
^{The divided} signal NS rises only by counting 2 ^(nk) times earlier than counting ^(n-1) times.

Therefore, the waiting time F from the deactivation of the vertical synchronization signal VS to the start of the measurement period t _M is set to the first and second waiting times.
It can be shortened from (t _M / 2-T _H + w) required in the example.

The number of flip-flops to which the vertical synchronizing signal VS is applied to the set terminal S for presetting need not be limited to one. T flip-flops 4 ₂ , 4 ₃ ,
, 4 _n may be provided with a set terminal S to which the vertical synchronizing signal VS is applied. In this case, assuming that the preset value is P, the divided signal NS rises by counting (2 ^(n-1) −P) times.

FIG. 12 is a timing chart showing the operation of the third embodiment. Since the preset is applied according to the "H" level of the vertical synchronizing signal VS, the divided signal NS can rise early.

Since the third embodiment is constructed and operates as described above, even if the period of the vertical synchronizing signal VS is short, the horizontal synchronizing signal HS can be accurately measured without reducing the frequency dividing value N.
The period of can be measured.

(B-4) Fourth Embodiment: In the first to third embodiments, the measurement period t _M is set as one cycle of the divided signal NS. In other words, the measurement period t _M is the horizontal synchronization signal H.
Period T _H of S, has been described a case equal to the value N times the division. However, the measurement period t _M can be set equal to an integral multiple of half the period T _H. This is the divided signal N
It suffices to select any two transitions of S and set the interval between them as the measurement period t _M.

In the fourth embodiment, the measurement period t _M is thus set.
13 is a block diagram showing the configuration of the cycle measuring apparatus 102 according to the fourth embodiment. Figure 3
The cycle measuring apparatus 101 according to the first embodiment shown in FIG. 2 has a configuration in which a counter 32 is newly provided. 14
3 is a timing chart showing the operation of the cycle measuring apparatus 102, and the measurement period t _M is set to N · T _H / 2.

The setting of the measurement period t _M as described above is, specifically, the transition of the second frequency-divided signal NS starting from the transition of the first frequency-divided signal NS after the vertical synchronizing signal VS is deactivated. It will be set as the end point.

FIG. 15 is a flowchart showing a part of the operation of the cycle measuring device 102. The steps S3, S4 and S5 shown in FIG. 6 are replaced with the steps S31, S4 shown here.
By replacing with S41, S42, S51, S52, S53, the entire operation of the cycle measuring device 102 is given.

After the internal counter 3 is reset in step S2 shown in FIG. 6, step S32 shown in FIG. 15 is executed. In step S32, it is determined whether or not the transition, which is the rising or falling of the divided signal NS, is detected. If not detected, step S32 is repeatedly executed.

When it is determined in step 32 that the rising or falling of the divided signal NS is detected, the value 1 is given to the variable J in step S41. Then, the same processing as step S4 in the first embodiment is executed in step S42. Thereafter, each time the transition of the divided signal NS is detected in step S51, the value of the variable J is incremented by 1 in step S52. The value of such a variable J is updated by the counter 32 shown in FIG.

Then, in step S53, it is determined whether or not the value of the variable J has reached a predetermined value JJ. If the value of the variable J has not yet reached the predetermined value JJ, the process returns to step 51, and the processes of steps 51 to 53 are repeatedly executed.

In the timing chart shown in FIG. 14, the value of the measurement period t _M is equal to N · T _H / 2. The predetermined value JJ in such a case is selected as 2. of course,
The value of JJ can be set to other values such as 3, 4, ....

The transition of the frequency division signal NS which sets the starting point of the measurement period t _M does not have to occur first after the inactivation of the vertical synchronization signal VS, and is secondly divided.
It is also possible to set the time point at which the transition occurs to the starting point of the measurement period t _M. However, as described in the second and third embodiments, it is desirable that the waiting time F is short. Therefore, as in the fourth embodiment, the transition which occurs first after the inactivation of the vertical synchronizing signal VS is used as a starting point. It is desirable to set the measurement period t _M.

(B-5) Fifth Embodiment: FIG. 16 is a block diagram showing the structure of a cycle measuring apparatus 103 according to the fifth embodiment of the present invention. The cycle measuring device 103 is the microcomputer 1 of the cycle measuring device 101 according to the first embodiment.
Is replaced with the measuring means 12.

The measuring means 12 comprises an internal pulse oscillator 2 for generating an internal pulse IP, a counter 31, a latch 6, and a microprocessor (MPU) 7. The measuring means 12 does not necessarily have to be a microcomputer, but may be a microcomputer. In addition, the internal pulse oscillator 2, the counter 31, the frequency divider 4, the latch 6
Can be formed on the same semiconductor chip.

FIG. 17 is a timing chart showing the operation of the cycle measuring device 103. However, the interval of the internal pulse IP is drawn wide for ease of explanation. The counter 31 is reset by the rising edge of the vertical synchronizing signal VS. Alternatively, it may be configured to reset at the fall. Also, by applying the third embodiment,
The waiting time F from the vertical synchronizing signal VS to the rising of the divided signal NS can be appropriately shortened.

The divided signal NS obtained by dividing the horizontal synchronizing signal HS by N is input to the enable terminal ENB of the counter 31, and when the value becomes "H", the counter 31 measures. It becomes possible (count enable). Count enabled counter 31
Is an internal pulse I input to its clock terminal CLK.
P is counted as 0, 1, 2, .... Then, when the value of the divided signal NS becomes "L", the counter 31 becomes unmeasurable (count disabled), and the counter 31 stops counting the internal pulse IP at the number K.

Therefore, the measurement period t _M includes the first to third measurement periods.
Half of the measurement period t _M in the embodiment, that is, N · T _H / 2
Therefore, even if the period of the vertical synchronizing signal VS does not correspond to one period of the frequency-divided signal NS, half of the period is sufficient.

The output of the counter 31 which takes the value K is given to the latch 6. The vertical synchronizing signal VS is given to the latch 6 as a latch signal, and the value of the latch 6 is held by the rising of the vertical synchronizing signal VS. That is, the vertical synchronizing signal VS serves to reset the counter 31 and hold the value of the latch 6.

If the period of the vertical synchronizing signal VS is equal to the half period of the frequency dividing signal NS, the counter 31 is count disabled at least immediately before the vertical synchronizing signal VS rises, and its output L is the vertical synchronizing signal. It does not depend on the VS cycle. The output A of the latch 6 at a certain time is the vertical synchronization signal VS that rises before that time and the vertical synchronization signal V that rises before that time.
Between S and S, the value measured by the counter 31 is held. Depending on which one of the rising edges of the vertical synchronizing signal VS shown in FIG.
The counter 31 is reset, and the output A of the latch 6 is the value L ₀ of the output L of the counter 31 determined up to immediately before that.
Hold. The counter 31 is reset by the one located on the right side, and the output A of the latch 6 holds the value K of the output L of the counter 31 determined up to immediately before that.

The MPU 7 gives the read signal RD to the latch 6 and inputs the output A to obtain the value K. Using the value K obtained in this way, the period of the horizontal synchronizing signal HS is T = 2.
Calculated as T _S · K / N. This processing is MPU7
Done in. In the fifth embodiment, the measurement period t _M
Becomes half, the error ε is twice that of the first embodiment,
It becomes 2T _S / N. However, as in the first embodiment, the accuracy of the horizontal synchronizing signal HS does not deteriorate due to the longer period.

Moreover, in the fifth embodiment, the output A can be obtained at any time except when writing to the latch 6. Therefore, for example, by reading this in synchronization with the fall of the vertical synchronizing signal VS, the MPU 7 can stably obtain the output L of the counter 31.

FIG. 18 shows the configuration of the buffer 9 suitable for use when the output A of the latch 6 is given to the MPU 7 in synchronization with the fall of the vertical synchronizing signal VS, and the latches 6 and MP.
It is a block diagram which shows the connection relation with U7.

Here, the mode of the output L of the counter 31 is parallel, and correspondingly, the latch 6 is provided with a plurality of D flip-flops 6a in parallel. Buffer 9 is
A plurality of tri-state buffers 9a arranged in parallel
And an MPU data bus 9b.

Clock terminal C of D flip-flop 6a
The vertical synchronizing signal VS is given to LK, and the value of the D input is latched to the Q output by the rise thereof.

The read signal RD is applied to the tri-state buffer 9a, and when it is activated, the value applied to the input end of the tri-state buffer 9a is applied to its output end. When it is deactivated, the output terminal of the tri-state buffer 9a is in the high impedance state.

The MPU 7 is provided with an interrupt terminal INT for accepting interrupt processing, and the vertical sync signal V
S inputs. When the vertical synchronizing signal VS falls, the read signal RD is activated for a certain period, and the output A of the latch 6 is given to the MPU 7 via the MPU data bus 9b.

(B-6) Sixth Embodiment: In the fifth embodiment, it was shown that the effect can be obtained if the period of the vertical synchronizing signal VS is half the period of the divided signal NS. A problem occurs when the period of the signal VS is equal to or longer than one period of the divided signal NS.

FIG. 19 is a timing chart for explaining the problems of the fifth embodiment. As shown in FIG. 19, when the level of the divided signal NS becomes “H” a plurality of times during the period when the vertical synchronization signal VS is continuously inactive, the counter 31 further increases the value of its output L. go. Therefore, even if the obtained value is multiplied by 2T _S / N, the period of the horizontal synchronizing signal HS is not obtained, and the effect of the fifth embodiment cannot be expected.

In the sixth embodiment, in order to prevent such a problem, the level of the divided signal NS does not become "H" a plurality of times during the period in which the vertical synchronizing signal VS is continuously inactive. The divided signal NS is generated.

FIG. 20 is a circuit diagram showing the structure of the frequency dividing circuit 4e suitable for use in the sixth embodiment. Frequency divider 4e
Is applied to the frequency divider 4 included in the period measuring device 103 shown in FIG. 16 to realize the sixth embodiment. Dividing circuit 4e is replaced with the divider circuit 4a of the T flip-flop 4 ₁ toggle disable terminal TE (negative logic) with a T flip-flop 4 ₁ "shown in FIG. 5, the final divider 4a It has a configuration in which the T flip-flop 4 _S is added after the T flip-flop 4 _{n in} stages.

Specifically, the horizontal synchronizing signal HS is applied to the clock input terminal T of the T flip-flop 4 ₁ ″, and its inverted Q output is applied to the clock input terminal T of the T flip-flop 4 _{2 ″.} The inverted Q output is given to the clock input terminal T of the T flip-flop 4 _{3. In} this way, the T flip-flop 4 ₁ ″,
4 _2, ..., 4 _n, 4 _s are connected, Q output of the T flip-flop 4 _s is T flip-flop 4 ₁ "is given to the toggle disable terminal TE of. Also all the T flip-flop 4 _1", 4 _The vertical synchronizing signal VS is applied to the reset terminals R of ₂ , ..., 4 _n , 4 _s .

Here, _if the Q output of the T flip-flop 4 _n is adopted as the frequency-divided signal NS, the T-flip-flop 4 _N will fall when the frequency-divided signal NS falls, that is, at the time when the frequency-divided signal NS transits to the “L” level. Q output of 4 _n rises. Therefore, the Q output of the T flip-flop 4 _s , which was previously reset by the vertical synchronizing signal VS and was at the “L” level, transits to the “H” level and the T flip-flop 4 ₁ which is the first stage of the frequency dividing circuit 4 e. Therefore, after the frequency-divided signal NS once becomes “L”, the vertical synchronizing signal VS is activated and all the T flip-flops 4 ₁ ″, 4 ₂ , ..., 4 _n , The frequency-divided signal NS does not take the "H" level again unless 4 _s is reset.

Since the sixth embodiment is constructed and operates as described above, there will be no improper counting which may occur in the fifth embodiment, and the same effect as that of the fifth embodiment can be obtained. be able to.

C. Other Modifications: In each of the above embodiments, the vertical synchronizing signal VS is used as it is as a reset signal of the frequency divider 4 or as a preset trigger. However, as can be seen from the description of the operation of each embodiment, it is not necessary to define the period during which the vertical synchronizing signal VS is active to a specific length in the present invention.

Further, in each of the above-described embodiments, the divided signal NS is generated immediately from the horizontal synchronizing signal HS. However, when the divided signal NS is generated, transitions such as rising of the horizontal synchronizing signal HS are counted. So the length of its activation period is not important.

On the other hand, in the monitor, the horizontal synchronizing signal H
A new signal is separately generated by controlling the pulse widths of S and the vertical synchronization signal VS. FIG. 21 is a conceptual diagram exemplifying a case where the present invention is applied using signals generated by controlling the pulse widths of the horizontal synchronizing signal HS and the vertical synchronizing signal VS in the monitor. For example, the blanking pulse generator 1001 generates a blanking pulse BP1 from the vertical synchronization signal VS, and the pulse generator 1002 generates a blanking pulse BP2 from the horizontal synchronization signal HS.
The clamp pulse CP and the drive pulse DV are generated.

Therefore, as shown in FIG. 21, the frequency divider 4 is reset using the blanking pulse BP1 instead of the vertical synchronizing signal VS, and the clamp pulse CP is divided instead of the horizontal synchronizing signal HS. As a result, the frequency-divided signal NS is generated to obtain the same effect as that of the first embodiment. Also in each of the other embodiments, the respective effects can be obtained by performing such substitution.

[0093]

As described above, according to the cycle measuring apparatus of the present invention, the number of times the third signal is activated in the predetermined measurement period defined by the first signal is measured. It is possible to avoid an increase in measurement error even if the period of is increased.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing the basic idea of the present invention.

FIG. 2 is a conceptual diagram in which a part Z of FIG. 1 is enlarged.

FIG. 3 is a block diagram showing a first embodiment of the present invention.

FIG. 4 is a timing chart explaining the operation of the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a first embodiment of the present invention.

FIG. 6 is a flowchart showing the operation of the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration example of a first embodiment of the present invention.

FIG. 8 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration example of a second embodiment of the present invention.

FIG. 10 is a timing chart showing the operation of the second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration example of a third embodiment of the present invention.

FIG. 12 is a timing chart showing the operation of the third embodiment of the present invention.

FIG. 13 is a block diagram showing a fourth embodiment of the present invention.

FIG. 14 is a timing chart showing the operation of the fourth embodiment of the present invention.

FIG. 15 is a flowchart showing a part of the operation of the fourth embodiment of the present invention.

FIG. 16 is a block diagram showing the configuration of a fifth embodiment of the present invention.

FIG. 17 is a timing chart showing the operation of the fifth embodiment of the present invention.

FIG. 18 is a configuration diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 19 is a timing chart explaining a problem of the fifth embodiment of the present invention.

FIG. 20 is a circuit diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 21 is a conceptual diagram showing a modified example of the present invention.

FIG. 22 is a block diagram showing a conventional technique.

FIG. 23 is a timing chart showing a conventional technique.

[Explanation of symbols]

 1 Microcomputer 2 Oscillator 3 Internal counter 4 Frequency divider 4a-4e Frequency divider circuit 6 Latch 7 Microprocessor (MPU) 101-103 Period measuring device HS horizontal synchronizing signal VS vertical synchronizing signal NS frequency dividing signal IP internal pulse

[Procedure amendment]

[Submission date] December 15, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0080

[Correction method] Change

[Correction content]

The read signal RD is applied to the tri-state buffer 9a, and when it is activated, the value applied to the input end of the tri-state buffer 9a is applied to its output end. When it is deactivated, the output terminal of the tri-state buffer 9a is in a high impedance state.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 21

[Correction method] Change

[Correction content]

FIG. 21 ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 26, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

The measurement period is equal to one cycle of the second signal,
When the period of the third signal is T _S and the third signal is activated K times during the measurement period, the period of the first signal is measured as T _S · K / N.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

FIG. 4 is a timing chart for explaining the operation of the cycle measuring apparatus 101. The frequency divider 4 reset by the "H" level of the vertical synchronizing signal VS divides the horizontal synchronizing signal HS by N to generate a divided signal NS. FIG. 5 is a circuit diagram showing a configuration example of the frequency dividing circuit 4a that can be used for the frequency divider 4. T flip-flop 4 ₁ ,
4 _2, 4 _3, ..., 4 _n are a connected in series, T flip-flop 4 _2, 4 _3, ..., 4 to the _n clock input terminal T, Q ¯ of each preceding stage Output is given. The horizontal synchronizing signal HS is applied to the clock input terminal T of the T flip-flop 4 ₁ . And all the T flip-flop 4 _1, 4 _2, ..., a reset terminal R of 4 _n given vertical synchronizing signal VS.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction content]

By the "H" level of the vertical synchronizing signal VS, all the T flip-flops 4 ₁ , 4 ₂ , ..., 4 _n except the T flip-flop 4 _k are reset. Then, only the T flip-flop 4 _k is set (preset). Therefore, the preset value of the frequency dividing circuit 4d is 2
^(k-1) , and the rising edge of the horizontal sync signal HS becomes 2
^{The divided} signal NS rises only by counting 2 ^(nk) times earlier than counting ^(n-1) times.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0062

[Correction method] Change

[Correction content]

FIG. 15 is a flowchart showing a part of the operation of the cycle measuring device 102. Step S 32 to Step S3, S4, S5 shown in FIG. 6, shown here,
By replacing with S41, S42, S51, S52, S53, the entire operation of the cycle measuring device 102 is given.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0093

[Correction method] Change

[Correction content]

[0093]

As described above, according to the period measuring apparatus of the present invention, the number of times the third signal is activated in the predetermined measurement period defined by the second signal is measured. It is possible to avoid an increase in measurement error even if the period of is increased.

Claims (9)

[Claims] 1. A cycle measuring device for measuring the cycle of a first signal which is cyclically activated, comprising: (a) a cycle having a cycle larger than that of the first signal and having a predetermined relationship with the first signal. An input terminal for inputting two signals; (b) an oscillator for generating a third signal having a shorter cycle than the first signal; and (c) activation of the third signal in a measurement period determined by the second signal. A first counter for measuring the number of times, (d) the output of the first counter, the cycle of the third signal,
And a calculation unit that calculates the cycle of the first signal from the predetermined relationship. 2. The cycle measuring device according to claim 1, wherein the predetermined relationship is that the cycle of the second signal is an integer N times the cycle of the first signal. 3. The period measuring device according to claim 2, further comprising: (e) a frequency divider that divides the first signal by N to generate the second signal and supplies the second signal to the input terminal. 4. The first signal is activated at least when a periodically activating fourth signal is inactive, and the frequency divider is given an initial value by the activated fourth signal. 2 counters, the second signal is the second
The period measuring device according to claim 2, which is obtained as an output of a counter. 5. The period measuring device according to claim 4, wherein the measurement period is an integral multiple of one half of one period of the second signal. 6. The cycle measuring device according to claim 5, wherein the measurement period corresponds to one cycle of the second signal. 7. The cycle measuring device according to claim 5, wherein the measurement period corresponds to a half cycle of the second signal. 8. (f) Latch means for holding the output of the first counter, (g) Read means for inputting the output of the latch means, and further comprising: To the resetting of the first counter and the holding of the latch means, and the first counters are adjacent to each other, and the measurement is performed only during the transition of the second signals in different directions. The cycle measuring device according to claim 7, which performs 9. The period measuring apparatus according to claim 8, wherein the second signal makes only two transitions in mutually different directions during a period in which the fourth signal is continuously inactive.