JPH0752594B2 - Address control circuit for semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address control circuit for a semiconductor memory, and more particularly to a ROM address control circuit incorporated in a microcomputer, a master slice type semiconductor device, or the like.

[Conventional technology]

In a semiconductor device, a built-in ROM (Read Only Memory) has an address control circuit that decodes an address signal and selects a memory cell. In this built-in ROM, the same data may exist over different addresses. For this type of ROM, a method of compressing the addresses by an address control circuit to apparently reduce the memory capacity is used.

Conventionally, an address control circuit having a predecode circuit is used as a means for realizing this method, as shown in FIG. In this way, the same ROM for multiple addresses
There is a microprogram ROM as a typical example of those having output data, and hereinafter, an address control circuit of the microprogram ROM will be described as an example. As an example, a microprogram having cell selection control signals and output values corresponding to address inputs as shown in Table 1 can be considered.

In FIG. 3, 1 is a microprogram ROM, 2
Is a column selection circuit of the microprogram ROM 1, 3 is a column selection decoding circuit (hereinafter referred to as Y-decoder), 4 is a row selection decoding circuit (hereinafter referred to as X-decoder), 5 is an address register, and 6 is It is a pre-decoding circuit. A0 ~
A4 is an address signal, Y0 to Y2 are Y decoder output signals, and X0 to
X7 is an X decoder output.

The address signals A0 to A4 cause the address control circuit having the predecode circuit 6, the address register 5, the X-decoder 4, and the Y-decoder 3 to operate, and the X-decoder for selecting a memory cell outputs the output Xn (n = 0-7), Y-decoder output
The ROM output is obtained by Ym (m = 0,1,2). The circuit diagram of the X-decoder in this case is shown in FIG. 4 (a), the circuit diagram of the Y-decoder in FIG. 4 (b), and the predecoding circuit is shown in FIG. 4 (c). The X-decoder of FIG. 4 (a) decodes the output of the lower 3 bits (A0, A1, A2) of the address register 5 to generate eight decoded outputs of X0 to X7, and the row of the microprogram ROM1. Select. Further, the Y-decoder of FIG.
The output of bits (A3, A4) is decoded to generate three kinds of decoded outputs Y0 to Y2, and the column of the microprogram ROM1 is selected. The predecoding circuit of FIG. 4 (c) receives the address signals A0 to A3 as input and outputs the predecoding signal.
Table 2 shows a truth table of the outputs of the predecode signals PD0 to PD3 corresponding to the address signals A0 to A3, which outputs PD0 to PD3.

Predecode signals PD0 to PD3 are given by the following logical expressions.

PD3 = 0 PD2 = A3 PD1 = ▲ ▼ ・ A2 ＋ A2 ・ A1 PD0 ＝ ▲ ▼ ・ A1 + A3 ・ A2 ・ ▲ ▼ In Table 1, all output values of microprogram ROM1 are different, so full decoding is done. It is necessary, but addresses 16 to 31 can be compressed because the microprogram ROM1 has the same output. Third
In the figure, from address 16 onward, the address signal A4 becomes a logical value "1", and instead of the address signals A0 to A3, the predecode signals PD0 to PD3 are input to the address register 5 via the predecode circuit 6, The cell selection control signal shown in Table 1 is output to obtain the desired microprogram ROM output. In this case, apparently, the capacity of the microprogram ROM at address 32 is compressed to 23.

[Problems to be solved by the invention]

In the address control circuit of the semiconductor memory such as the conventional microprogram ROM described above, when a plurality of addresses have the same content data, the predecode circuit is used as a means for compressing the addresses. Since the delay time of the predecoding circuit is added in the time, there is a drawback that it becomes an obstacle to high-speed access.

An object of the present invention is to provide an address control circuit for a semiconductor memory that can be accessed at high speed.

[Means for solving problems]

An address control circuit of a semiconductor memory according to the present invention selectively generates a row selection signal of a memory cell array for an i-bit single address signal of 1 ≦ i <n among n-bit address signals. Different from the i-bit address signal among the n-bit address signal, the first row selection decoding circuit selectively stores the memory cells in response to a plurality of j-bit address signals satisfying 1 ≦ j <n. A second row selection decoding circuit for generating an array row selection signal;
A column selection decoding circuit for selectively generating a column selection signal of the memory cell array in response to an address signal of an upper bit of the bit address signal excluding the i bit, and the first and second row selection signals. Of the n-bit address signal and selectively driven by at least a part of the upper-bit address signal to supply the output to the memory cell array.
And a second buffer circuit, which enables address control of the memory cell array having a smaller number of addresses than can be specified by the n-bit address signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, a memory cell array (microprogram ROM 1) is selectively used for a single address signal of 3 bits (A0 to A2) among the address signals of 5 bits (A0 to A4).
Of the first row selection decoding circuit (first X-decoder 7) for generating the row selection signal and the above-mentioned 3-bit (A0 to A2) address signal of the 5-bit address signal, A second row selection decoding circuit (second X-decoder 9) for selectively generating a row selection signal of the microprogram ROM 1 for a plurality of 3-bit (A1 to A3) address signals; Among the bit address signals, the above 3
A column selection decoding circuit (Y-decoder 3) for selectively generating column selection signals Y0 to Y1 of the microprogram ROM1 in response to the address signals of the upper bits (A3 to A4) excluding the bits (A0 to A2), The outputs of the above-mentioned first and second row selection signals are received and selectively driven by a part A4 of the upper-order bit (A3-A4) address signal of the 5-bit (A0-A4) address signal, respectively. Micro program RO
A first and a second buffer circuit (8,10) for supplying outputs (X0-X7, X0'-X7 ') to M1 and thereby 5
Number of addresses that can be specified by address signals of bits (A0 to A4) 32
It is possible to control the address of the microprogram ROM 1 with a smaller address number of 24.

The address register 5 stores address signals A0 to A4 to the microprogram ROM 1, and the address signals are input to the first X-decoder 7, Y-decoder 3 and second X-decoder 9. . The output of the first X-decoder 7 passes through the first buffer 8 and the microprogram RO.
It becomes the row selection signals X0 to X7 of M1. The first buffer 8 is supplied with a reverse phase signal ▲ ▼ of the address signal A4 as a control signal, and this control signal controls whether to output the row selection signals X0 to X7. The output of the second X-decoder 9 is given as row selection signals X0 'to X7' via the second buffer 10, but the same row as X0 and X0 ', ..., X7 and X7' described above. The second buffer 10 is added to the selection signal line.
Since the control signal of is the address signal A4, it is not applied at the same time. The Y-decoder 3 receives the address signals A3 and A4.
It receives as an input and outputs the column selection signals Y0, Y1, Y2.

The circuit of the first X-decoder 7 is the same as that shown in FIG. 4 (a), and the circuit of the Y-decoder 3 is shown in FIG. 4 (b).
Is the same as that shown in.

FIG. 2 is a circuit diagram of one column of the second X-decoder 9.
The correspondence relationship between the address signal of the second X-decoder and the row selection signal is as shown in Table 3 below. (Address signals A0 and ▲ ▼ in Table 3 are not shown in FIG. 2 because they are not used substantially.) Next, the operation from address 0 to address 31 will be described. First, in addresses 0 to 15, the highest address signal A4 is logical "0", the second buffer 10 is not driven, and the first buffer 7 controlled by the reverse phase signal ▲ ▼ of the address signal A4 is When driven, the first X-decoder 7 becomes valid. Therefore, the row selection signals X0 to X7 are as shown at addresses 0 to 15 in Table 1. As for the output of the Y-decoder 3, the column selection signal Y0 is selected from addresses 0 to 7 and Y1 is selected from addresses 8 to 15, and the micro program ROM output at a predetermined address is made by these row selection signal and column selection signal. To get

After the 16th address, the address signals A4 and ▲ ▼ are opposite to those described above, the second buffer 10 operates, and the second X-decoder 9 becomes valid. The second X-decoder 9 shown in FIG. 2 outputs row selection signals X0 'to X7' as shown in Table 3. In the Y-decoder 3, the address signal A4 is logical "1".
Therefore, the column selection signal Y2 is selected. In this way 16
The operations up to address 31 are the same as those shown in Table 1.

Although the micro program ROM has been described above, it goes without saying that the present invention can be applied regardless of the type of memory.

〔The invention's effect〕

As described above, according to the present invention, since the predecode circuit included in the conventional address control circuit is not required, the delay time due to the predecode circuit can be reduced and the semiconductor memory can be accessed at high speed. effective. Further, since the second X-decoder is used instead of the pre-decoding circuit, a mask can be designed according to the pitch of the memory cell array, resulting in a geometrically regular layout, improving characteristics and reducing the occupied area. There is also the effect of being obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a second X-decoder, FIG. 3 is a block diagram showing an example of the prior art, FIG. 4 (a), (B) and (c)
3 are circuit diagrams of an X-decoder, a Y-decoder and a pre-decoding circuit in FIG. 3, respectively. 1 ... Micro program ROM, 2 ... Column selection circuit, 3
...... Y-decoder, 4 ... X-decoder, 5 ... address register, 6 ... predecode circuit, 7 ... first X
-Decoder, 8 ... first buffer, 9 ... second X-
Decoder, 10 ... Second buffer, A0-A4 ... Address signal, O1-O8 ... Output terminal, PD0-PD3 ... Predecode circuit output signal, X0-X7 ... Row selection signal, Y0-Y2 …… Column selection signal.

Claims (1)

[Claims] 1. 1 ≦ i <of n-bit address signals
a first row selection decoding circuit for selectively generating a row selection signal of the memory cell array for a single i-bit address signal of n;
A second row selection decoding circuit for selectively generating a row selection signal of the memory cell array for a plurality of j-bit address signals satisfying 1 ≦ j <n, unlike the i-bit address signal; A column selection decoding circuit for selectively generating a column selection signal of the memory cell array for an address signal of an upper bit of the n-bit address signal excluding the i-bit, and the first and second row selection circuits. First and second buffer circuits that receive a signal output and are selectively driven by at least a part of the upper-bit address signal of the n-bit address signal to supply an output to the memory cell array, respectively. , Which enables address control of the memory cell array having a smaller number of addresses than can be specified by the n-bit address signal. And then the semiconductor memory of the address control circuit, characterized in that the.