JPH0752540B2 - Digital phase controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase control device for phase-locking the phases of two systems of motors, for example, synchronization of continuous recording operation of a magnetic recording / reproducing apparatus (VTR). It is used for a phase servo system in a mode (standby mode).

2. Description of the Related Art FIG. 5 shows the operation timing of a continuous recording mode having X value shift correction by a conventional apparatus, and FIG. 6 is a functional block diagram thereof. The continuous recording mode is, for example, National Technical Port Volume 28, No.3.P561 to P57.
As detailed in 6,1982, standby mode (also called short play) that synchronizes the video signal on the already recorded magnetic tape with the video signal to be newly recorded, and after phase synchronization The above-described series of operations removes the noise of the reproduced image due to the disturbance of synchronization at the time of the connection in the reproduction operation mode of the video signal recorded by the connection. In addition, in order to improve the controllability of the tape running servo (capstan servo system) at constant speed during a series of operations of acceleration, constant speed, deceleration, and stop of the frame feed fine throw method, a special playback head is used. There is a case where a correction is added without adding the phase of the control signal (CTL) on the tape to the same phase as the external vertical synchronizing signal (VSY ₁ ). This is called X value shift correction, and the head switching signal (HSW). The time from to the control signal (CTL) is called an X value shift. Here, a conventional example will be described below in a continuous recording mode having X value shift correction.

In the standby mode, the external vertical sync signal (VSY ₁ ) obtained by sync separation from the video signal and the head switching signal (HSW), which is this position signal, are phase-locked to synchronize the head position on the rotary head. A cylinder servo system for controlling the head position and a control signal (CTL) in a phase relationship determined by the X value shift time T _XS , and a capstan servo system that controls the phase of the magnetic tape running in synchronization with each other. There is a need.

In the cylinder servo system, the external vertical synchronization signal (VSY ₁ ) with a cycle of 1 / f _{V (SYNC)} is input to the preset generation circuit 7 of the phase discriminator 1 for cylinder phase comparison, and the cylinder phase comparison signal of the same phase discriminator 1 is input. At the output 26, the cylinder phase comparison signal (CYL P / C) shown in FIG. 5 (B) is external vertical synchronization signal (VSY ₁ ).
It is output in synchronization with the falling edge timing of (However, the cylinder / capstan phase comparison signal is shown by DA conversion of the digital phase count value). On the other hand, the position signal (HSW) of the rotary head is input to the latch generation circuit 6 of the phase discriminator 1, and at the falling timing of the head switching signal (HSW), the cylinder phase comparison signal (CYL P /
Latch the deviation value from the reference phase by the trapezoidal wave of C),
For example, when the external vertical synchronizing signal (VSY ₁ ) and the head switching signal (HSW) are phase locked, the phase lock output N _CY (deviation value zero output) is output from the cylinder phase comparison signal output 26 and the head switching signal is output. The phase between the rising edge of (HSW) and the falling edge of the external vertical sync signal (VSY ₁ ) is τ _(REC) ≈ 6H (where H is 1 horizontal scanning period = 63.5μs) according to the VTR specifications. Locked. (However, the duty of the head switching signal is 50%.) In the capstan servo system, the count value NH _Y gate output 22 of the cylinder phase comparison counter 3 is supplied to the preset generation circuit 12 of the capstan phase comparison phase discriminator 2. By the input, the capstan phase comparison counter 8 is synchronously operated with the cylinder phase comparison counter 3 at the cycle 1 / f _{V (SYNC)} . Moreover, the preset value NP _A capstan phase comparator counter 8 which phase lock count NC _A capstan phase comparator counter 8 with the falling edge timing of the X value shift (trapezoidal wave NL _A -NH _A central value) is synchronized select. On the other hand, the control signal recorded on the control track of the magnetic tape is amplified and input to the CTL processing circuit 17 as a reproduction control pulse signal (PB CTL), and its rising edge output 37 is input to the latch generation circuit 11. , Capstan phase comparison signal (CAP P /
The trapezoidal wave in C) latches the deviation from the reference phase. As a result, the external vertical sync signal (VSY ₁ ), head switching signal (HSW) and playback control pulse signal (P
BCTL) are phase locked to each other. Furthermore, the control signal (CTL) is input to divide the frequency of the capstan frequency generator (FG) signal (CAP FG), and the phase generator (PG) signal (PG) which is the compared signal of the capstan phase system during recording ( The PG processing circuit 18 for generating PG) is reset to set the count to zero, and the timing when the count value is 1 is configured to be output as a frequency division output (PG).
If f _PG is set to a PG frequency division ratio that establishes a relationship of 1 / f _PG 1 / f _{V (SYNC)} with frame sync vertical sync signal period 1 / f _{V (SYNC)} , playback in standby mode The phase difference between the control signal (PB CTL) and PG signal can be locked with an error of 0 to 1 / f _{CAP FG} .

In the recording mode, the cylinder servo system operates the same as in the standby mode, while in the capstan servo system, the capstan phase comparison counter 8 has the same cycle 1 / f _{V (REC)} as 1 / f _PG.
The internal reference oscillation is generated at, the PG signal that is the compared signal is input to the latch generation circuit 11, and the capstan phase comparison signal (CAP
Latch the deviation value from the reference phase from the trapezoidal wave of (P / C). As a result, the joint error of the joint recording is 1 / max.
f _{CAP FG} can be suppressed and the image noise at the joint can be removed.

Then a timing chart of standby mode in Figure 7, detailing the relationship between the preset value NP _A X value shift time T _XS capstan phase comparator counter 8.
This timing chart is an enlarged view of the standby mode in FIG. Where NP _Y : Cylinder phase comparison counter preset value.

NC _Y : Trapezoidal wave center count value of the cylinder phase comparison counter.

n: Number of bits of cylinder phase comparison gate & latch circuit.
(Number of bits of trapezoidal wave) f _{V (SYNC)} : Frame sync vertical sync frequency.

NP _A : Preset value of the capstan phase comparison counter.

NC _A : The trapezoidal wave center count value of the capstan phase comparison counter.

T _XS : X value shift time.

It is defined as here It can be calculated preset count NP _A as described above.

In the invention is to solve the conventional device problems described above which may have the following: restrictions in the preset value NP _A capstan phase comparator counter. However, the trapezoid position is fixed regardless of the X value shift amount.

NL _A NP _A NH _A This is the preset value of the capstan phase comparison counter.
A case where NP _A is included in the trapezoidal wave period of the capstan phase comparison signal (CAP P / C), in this case, it is discontinuous portions trapezoidal section, or not to apply phase lock, significantly interfere It cannot be used.

0NP If _A NL when _A is and NP _A is close to NL _A This is the balance of the H period of the comparison signal (or NH _A) and L period (NL _A hereinafter) deteriorates, adversely affect the pull-in time.

Therefore, the preset value NP _A must design a count value that is not contained within the restriction period, further, in relation to the X value shift time, if falls within the period, a problem that the system can not be used There is a point.

The present invention solves such a problem, and suppresses the increase in hardware, and provides a continuous recording mode having X value shift correction without the above-mentioned restrictions.
An object is to provide a realizable digital phase control device.

Means for Solving the Problems In order to solve the above-mentioned problems, the digital phase control apparatus of the present invention is a pair that obtains, as a binary output, the deviation of the periods of two kinds of mutually synchronized input signals from the reference period. Of digital phase discriminator, that is, a phase discriminator for cylinder phase comparison and a phase discriminator for capstan phase comparison,
In the joint recording mode with X-value shift correction of the magnetic recording / reproducing apparatus, the capstan phase comparison phase discriminator is preset to the initial count value NP _A at the preset timing of the initial count value NP _Y of the cylinder phase comparison phase discriminator. To do.

Working With this configuration, the position of the trapezoidal wave for capstan phase comparison can be designed to any phase set by X value shift,
It realizes the deletion of design restrictions.

Embodiment FIG. 1 is an operation timing chart in a continuous recording mode having X value shift correction according to an embodiment of the present invention.
FIG. 2 shows a functional block diagram for realizing this, and FIG. 3 shows a digital phase comparison circuit for explaining the operation of the cylinder phase comparison signal (CYL P / C) and the capstan phase comparison signal (CYL P / C). It is a basic principle explanatory drawing.

The cylinder phase comparison phase discriminator 1 counts and compares phase differences to generate a reference cycle, and a cylinder phase comparison counter 3,
A preset data generation circuit 4 for generating a preset count value, a gate & latch circuit 5 for forming a trapezoidal wave from the output 25 of the cylinder phase comparison counter 3, and a preset generation circuit for presetting a preset value NP _Y to the counter 3. 7. Latch generation circuit 6 for latching the counter output 25 according to the compared signal, NL _Y gate, NH _Y gate,
Formed by NF _Y gate and VSY ₂ generation circuit.

The phase comparison counter 3 is an m-bit binary counter shown by the characteristic a in FIG. 3, and the lower n-bit output 25 is input to the gate & latch circuit 5. The external vertical sync signal (VSY ₁ ) is input to the preset generation circuit 7 as a reference signal input,
At the falling edge timing of the external vertical synchronizing signal (VSY ₁ ), the preset control output 20 presets the data NP _Y from the preset data generation circuit 4 to the cylinder phase comparison counter 3. Frequency output from the reference signal generation circuit 15 based on the reference signal input (RCK) The reference value of the reference clock pulse causes the cylinder phase comparison counter 3 to count up, and a preset value which becomes the external vertical synchronization signal (VSY ₁ ) of cycle 1 / f _{V (SYNC)} in frame synchronization at the timing of NF ′ _Y. If you select NP _Y ,
The cylinder phase comparison counter 3 It operates repeatedly with the reference synchronization of. Characteristic b indicates the lower n bits of the cylinder phase comparison counter 3. Repeated operation from count value 0 to count value (2 ⁿ -1). Counting zero, the center value ^{{2 (n-1)}} , the maximum value respectively NL _Y comparison counter value corresponding to the _{^{(2 n -1), NC Y}} , and NH _Y, NL _Y for this counting detector
By providing a gate and an NH _Y gate and inputting this output to the gate & latch circuit 5, the comparison counter 3 outputs the output value NP.
_The operation to reach _Y- NF ' _Y is configured to be output from 26 as a trapezoidal wave shown in the characteristic c of FIG. However, the respective characteristics a to c in FIG. 3 are represented in an analog manner by DA conversion of the digital count value. The head switching signal (HSW), which is the compared signal, is input to the latch generation circuit 6, and the output count value characteristic of the gate & latch circuit 5 corresponding to the count value characteristic a of the comparison counter 3 at the timing output 27 of its falling edge. c is output from the terminal 26 as a cylinder phase comparison signal. As shown in FIG. 3, the lead phase from the count value NP _{Y to} NL _Y is L output, the lag phase from NH _{Y to} NF ′ _Y is H output, and the trapezoidal wave from NL _{Y to} NH _Y. During the period, a count value corresponding to the latched counter value is output. The above is the operation of the cylinder servo system.

Next, the capstan servo system will be described. The operation of the phase discriminator 2 for capstan phase comparison in the standby mode is basically the same as the operation of the phase discriminator 1 for cylinder phase comparison described above, but a signal input to the preset generation circuit 12 as a reference signal. Is the output 20 of the preset generation circuit 7 of the cylinder phase comparison discriminator 1, which is the feature of the present invention. According to this configuration, the capstan phase comparing preset value NP _A
Does not limit the X value shift time even if the trapezoidal wave position is fixed. This will be described in detail below.

FIG. 4 shows a timing chart in the standby mode of the present invention. The following equation holds from the figure.

However, τ _(REL) : Phase difference between head switching signal (HSW) and external vertical sync signal (VSY ₁ ) in recording mode In this device, since the preset timing of the capstan phase comparison counter 8 can be set independently of the trapezoidal wave position of the cylinder phase comparison counter 3, the preset value NP _A of the cylinder phase comparison counter 3 limits T _XS . It will have no end.

The relationship between the control signal (CTL) and the flikesin generator signal (PG) in standby mode can be set in the same way as in the conventional example, so both The phase is locked by the phase difference of, and the phase difference between the joints is also maximum. Can be suppressed.

As described above, according to the present invention, in the continuous recording mode with X-value shift correction, the X-value shift value can be arbitrarily set without any limitation, and the additional design can be minimized. Since it is held down, there is almost no cost increase due to functional improvement.

[Brief description of drawings]

FIG. 1 is an operation timing chart of the joint recording mode in the apparatus of the present invention, FIG. 2 is a functional block of the apparatus of the present invention, FIG. 3 is an explanatory view of the basic principle of the digital phase comparison circuit, and FIG. FIG. 5 is a timing chart in the standby mode by the apparatus of the present invention, FIG. 5 is an operation timing chart of the continuous recording mode in the conventional apparatus, FIG. 6 is a functional block diagram of the conventional apparatus, and FIG. 7 is a conventional example. 6 is a timing chart in the standby mode by the device. 1 ... Cylinder phase comparison phase discriminator, 2 ... Capstan phase comparison phase discriminator, 3 ... Cylinder phase comparison counter, 4 ... Preset data generation circuit, 5 ... Gate & latch circuit, 6 ... Latch generation circuit, 7 ... Preset generation circuit, 8 ... Capstan phase comparison counter,
9 …… Preset data generation circuit, 10 …… Gate and latch circuit, 11 …… Latch generation circuit, 12 …… Preset generation circuit, 13 …… X value correction mono-multi.

Claims (1)

[Claims] 1. A digital phase control device used in a magnetic recording / reproducing device, comprising a pair of digital phase discriminators for obtaining deviations of two types of periods of mutually synchronized input signals from a reference period as binary outputs. The pair of digital phase discriminators are a cylinder phase comparison phase discriminator and a capstan phase comparison phase discriminator, and the cylinder phase comparison is performed in the joint recording mode having the X value shift correction of the magnetic recording / reproducing apparatus. Digital phase controller, wherein the capstan phase comparison phase discriminator is preset to an initial count value at a preset timing of the initial count value of the phase discriminator.