JPH0750578A - Pll circuit - Google Patents

Abstract

PURPOSE:To improve the converging speed in a transient response state without deteriorating the steady characteristic. CONSTITUTION:The output of a voltage control type variable oscillator VCO 1 is supplied to a divider 2, and the division signal (comparison pulse) is supplied to a phase detector 3. At the same time, a prescribed reference pulse is supplied to the detector 3. The detection output of the detector 3 is supplied to the VCO 1 via a filter 4, and a phase locked oscillation signal is taken out of the reference pulse. The oscillation signal is supplied to a counter 5 from the VCO 1, and the count value of the counter 5 is supplied to a decoder 6 for production of a horizontal deflection signal. Furthermore the oscillation signal is supplied to a counter 7 from the VCO 1, and the count value of the counter 7 is supplied to a decoder 8 for production of a prescribed stepped signal. Then the stepped signal is taken out with timing of the reference pulse. A drive current source 9 of the detector 3 is controlled in response to the level of the stepped signal. Then the detection gain of the detector 3 is controlled under the control of the current source 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit used in a horizontal synchronizing system of a television receiver, for example.

[0002]

2. Description of the Related Art As a PLL circuit, a circuit generally shown in FIG. 10 has been conventionally used. That is, in FIG. 10, a voltage controlled variable oscillator (VCO) 101
Is supplied to the frequency divider 102, and this frequency-divided signal (comparison pulse) is supplied to the phase detector 103. Further, a predetermined reference pulse is supplied to the phase detector 103. Therefore, the phase detector 103 detects the phase difference between the frequency-divided signal and the reference pulse. Then, the detected output is supplied to the VCO 101 via the filter 104, and the oscillation signal phase-locked with the reference pulse is taken out.

In such a PLL circuit, the transfer function H _(S) of one round is

[Equation 1] However, K _VCO is represented by the gain of the _VCO 101, K _PD is represented by the gain of the phase detector 103, and 1 / N is represented by the division ratio of the frequency divider 102.

On the other hand, the filter 104 is usually shown in FIG.
The lag lead filter as shown in is used, and its transfer function F _(S) is

[Equation 2] It is represented by.

The natural frequency ω _n and the damping factor ξ at this time are respectively described as follows.

[Equation 3]

[0006]

[Equation 4] Here, the convergence during transient response becomes faster as the value of ω _n increases.

On the other hand, the noise band B _L, which is one of the parameters showing the stationary characteristic, is expressed by the following equation.

[Equation 5]

Therefore, in the above-mentioned PLL circuit, _if the value of ω _n is increased in order to improve the convergence speed at the time of transient response, B _L becomes large and the steady-state characteristic deteriorates. Therefore, in the conventional PLL circuit, ω _n
There was a limit to increasing the value of.

By the way, such a PLL circuit is used, for example,
Considered to be used in the horizontal synchronization system of a television receiver
Has been. In that case, for example, the video signal from the VTR
The position of the horizontal sync signal is changed when the head is switched during image reception.
Considering the time when the transient response is changed,
It is necessary to improve the convergence speed. But above
As described above, in order to improve the convergence speed during transient response,_n
When the value of is increased, B _LBecomes larger and the steady-state characteristics deteriorate.
It was something I would do.

On the other hand, for example, as shown in FIG. 12, the constants of the filter 104 can be switched, and the constants in the transient response and the constants in the steady state can be selected to improve the characteristics of both. Conceivable. However, in such a method, the number of externally attached parts is increased, and the rapid frequency change at the time of switching is not preferable for the horizontal deflection system, and there is a possibility that the constituent elements may be destroyed depending on the conditions. This application is made in view of such a point.

[0011]

The problem to be solved is that ω _n in order to improve the convergence speed during transient response.
If the value of is increased, B _L is increased and the steady-state characteristics are deteriorated. Therefore, in the conventional PLL circuit, there is a limit in increasing the value of ω _n , considering the steady-state characteristics.

[0012]

According to a first means of the present invention, the output of a voltage controlled variable oscillator (VCO) 1 is supplied to a phase detector 3 through a frequency divider 2 and the divided signal is supplied to the phase detector 3. In a PLL circuit configured to supply a signal based on the phase difference between the divided signal and the reference pulse to the voltage controlled variable oscillator 1 to obtain a phase locked oscillation signal, the gain of the phase detector 3 is changed. (Variable current source 9), the phase difference between the divided signal and the reference pulse (counter 7, decoder 8)
It is a PLL circuit that controls this gain in accordance with.

According to a second aspect of the present invention, in the PLL circuit according to the first aspect, the phase detector is composed of a multiplier, and the gain is variable by controlling the drive current of the multiplier. A PLL circuit that counts the output signals of the voltage controlled variable oscillator, decodes the count value at the timing of the reference pulse, and controls the drive current according to the decoded value.

According to a third means of the present invention, in the PLL circuit according to the first means, the phase detector switches the current source circuit according to the phase difference, integrates the switched current, and outputs the output. It is a PLL circuit configured to obtain the variable gain by controlling the current value of the current source circuit.

A fourth means according to the present invention is the PLL circuit according to the first means, in which the gain is controlled by weighting the control amount for the phase difference.

[0016]

According to this, the gain of the phase detector is made variable,
By controlling this gain according to the phase difference between the frequency-divided signal and the reference pulse, it is possible to improve the convergence speed during the transient response without impairing the steady characteristics.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a voltage controlled variable oscillator (VC
The output of O) 1 is supplied to the frequency divider 2, and this frequency-divided signal (comparison pulse) is supplied to the phase detector 3. Further, a predetermined reference pulse is supplied to the phase detector 3. Therefore, the phase detector 3 detects the phase difference between the divided signal and the reference pulse. Then, the detected output is supplied to the VCO 1 through the filter 4, and the oscillation signal phase-locked with the reference pulse is taken out.

The PLL circuit is constructed as described above. Therefore, when such a PLL circuit is used in a horizontal synchronizing system of a television receiver, for example, an oscillation signal from the VCO 1 is supplied to the counter 5. Then, this count value is supplied to, for example, the decoder 6 to form a horizontal deflection signal.

In the PLL circuit described above, V
The oscillation signal from CO1 is supplied to the counter 7. This count value is supplied to the decoder 8 to form, for example, a stepwise signal as shown in FIG. This signal is extracted, for example, at the timing of the reference pulse, and the drive current source 9 of the phase detector 3 is controlled according to the level of this signal.

That is, the phase detector 3 is constructed, for example, as shown in FIG. In FIG. 3, the voltage source V1 is a reference voltage, and the voltage source V2 is different from the voltage source V1 in FIG.
Generates a voltage as shown in. The voltage of the voltage source V2 is converted into a current by the transistors Q7 and Q10 and the resistors R6 and R8, and the ratio of the currents flowing through the transistors Q7 and Q10 becomes equal to the ratio of the currents flowing through the transistors Q6 and Q4.

The emitters of the transistors Q4 and Q6 are connected to the base and collector of the transistor Q5. The current flowing through the transistor Q5 is the resistor R2,
It is determined by the resistance ratio of R4 and the current flowing through the transistor Q3. Here, the current flowing through the transistor Q3 is I
Then, the current flowing through the transistor Q5 becomes I * R2
/ (R2 + R4).

If the current ratio of the transistors Q7 and Q10 is k: 1-k (0 <k <1), the transistor Q4
The current I _Q4 flowing in

## _EQU6 ## I _Q4 = I _Q5 * (1-k) = I * R2 / (R2 + R4) * (1-k).

Therefore, the current I _P1 flowing through the transistor _P1
Is

[Expression 7] I _P1 = I _Q2 + I _Q4 = I / (R2 + R4) * (R4 + (1-k) * R2) ..., and the transistors P1 and P2 and the transistor Q are expressed.
It becomes a driving current for a multiplier to be described later through a current mirror circuit composed of 12 and Q15. Although the current is amplified by the transistor Q15 in the figure, this is not always necessary.

Then, the phase detection is performed by the multiplier composed of the transistors Q13 to Q17, the transistors P3 to P6 and the resistors R11 to R13. That is, the voltage source V
3, V5 and V7 are DC voltage sources that provide appropriate bias voltages in the operation of the circuit. Further, the voltage source V6 is supplied with a horizontal synchronizing signal (positive polarity) as a reference pulse, and the transistor Q14 is turned on only in the horizontal synchronizing section. Further, the voltage source V4 is supplied with a pulse obtained by dividing the output of VCO1 as a comparison pulse.

Therefore, first, consider a case where the current supplied from the transistor Q15 to the multiplier is constant regardless of the phases of the reference pulse and the comparison pulse, that is, the voltage source V2 is a constant voltage. When synchronized here, the phases of the reference pulse and the comparison pulse become 90 degrees as shown in FIG. 5, and the output voltage of the filter 4 applied to the VCO 1 does not change. On the other hand, when the synchronization is lost, the output voltage of the filter 4 changes and the reference pulse and the comparison pulse are finally synchronized. This is the operation of a general PLL circuit.

In such a PLL circuit, further, according to the present invention, the voltage source V2 is not a constant voltage but has a staircase waveform synchronized with the comparison pulse. That is, the waveform as shown in FIG. 4 described above is created by decoding the output of the VCO 1, and the decoded value is given to the voltage source V2.

Here, when the reference pulse and the comparison pulse are synchronized, the phase relationship between the voltage of the voltage source V2 and the reference pulse is as shown in FIG. That is, in the steady state, the reference pulse exists in the section E in FIG. Therefore, in the section E, if the above-mentioned transistor Q10 is cut off, since k = 1 in the equation, the current flowing through the transistor P1 becomes the minimum value,

## _EQU8 ## I _P1MIN = I / (R2 + R4) * R4 ...

Therefore, the current for driving the phase detector 3 is also minimum in the section E, and as a result, the detection gain K _PD is also minimum. That is, when compared with the case where the voltage of the voltage source V2 is a constant voltage, if the current value expressed by the equation and the current value when the voltage of the voltage source V2 is a constant voltage are equal, the steady-state characteristics are equal. it is obvious.

On the other hand, considering a phase step input as an example of the case where synchronization is lost, when the voltage of the voltage source V2 is a constant voltage, the value of the formula is obtained regardless of the phase difference between both pulses. If the above-mentioned transistor Q7 is cut off in the section A, the current flowing through the transistor P1 has the maximum value.

(9) Since I _P1MAX = I _··· increases, I _P1MAX / I as shown in FIG.
_{When P1MIN} = G, the detection gain K _PD of the phase detector 3 can be increased up to G times.

Thus, according to the above-mentioned device, the gain of the phase detector is made variable, and the gain is controlled according to the phase difference between the divided signal and the reference pulse, so that the transient response is not impaired. The convergence speed can be improved.

That is, in the above-described PLL circuit, the phase detector 3 is a system in which the value of the current source to be driven is changed by the phase difference between both pulses, and the phase detection gain K _PD is increased by the phase difference between both pulses. . So there is no need to switch filters in this system,
Therefore, the number of external parts does not increase. Also,
The output of the phase detector 3 passes through the lag lead filter 4 and becomes V
Since it is given to CO1, there is no sudden change in the oscillation frequency that occurs when the filter is switched.

Further, in the above-mentioned embodiment, the example of the phase detector using the multiplier by the analog circuit is shown. However, when it is performed by the digital circuit, for example, the circuit as shown in FIG. 7 can be used. That is, in FIG. 7, the phase detector 21 in which the reference pulse and the comparison pulse are composed of MOSIC
And the MOS switches 22 and 23 are turned on / off by the output of the phase detector 21. This MOS switch 2
Reference numerals 2 and 23 are connected to current sources 24 and 25, respectively, and a connection midpoint of the MOS switches 22 and 23 is connected to a VCO (not shown) through a filter 26.

In this circuit, the phase detector 21 and the MOS switches 22 and 23 have a digital configuration, and the current source 2
4, and 25, and a MOS circuit. Therefore, in this circuit, the phase detection output can be obtained by controlling or turning on / off the output current. Then, the invention of the present application can be realized by controlling the current values of the current sources 24 and 25 with this circuit as described above.

The voltage V2 can be generated by a circuit as shown in FIG. 8, for example. That is, in FIG. 8, the outputs of the decoders are added via the resistors each having the resistance value R. Thus, for example, when the outputs shown in A to D of FIG. 9 are taken out from the decoder, the V2 output shown in E of the same figure can be obtained.

Further, not limited to such a digital system, if it is synchronized with the comparison pulse, the analog V
2 may be obtained. Even in the above example, it is clear that if the step value of the staircase waveform is set to infinity, it becomes an analog waveform.

Further, in the above example, the stepwise waveform of V2 is shown at equal intervals on both the time axis and the voltage axis for convenience, but it is also possible to weight it. In fact, if the output voltage V2 is weighted and the current for driving the phase detector exponentially increases as the phase difference between the reference pulse and the comparison pulse increases, it is expected that the transient response of the system will be further improved. To be done. Such weighting can be realized by changing the resistance value of the resistor connected to the output of the decoder in the circuit of FIG.

[0037]

According to the present invention, the gain of the phase detector is made variable, and the gain is controlled according to the phase difference between the frequency-divided signal and the reference pulse, so that the transient response is not impaired. It has become possible to improve the speed of convergence.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a PLL circuit according to the present invention.

FIG. 2 is a diagram for explaining the explanation.

FIG. 3 is a configuration diagram of an example of a phase detector used in the present invention.

FIG. 4 is a diagram for explaining the explanation.

FIG. 5 is a diagram for explaining the explanation.

FIG. 6 is a diagram for explaining the explanation.

FIG. 7 is a configuration diagram of another example of the phase detector.

FIG. 8 is a configuration diagram of an example of a generating circuit for the power V2.

FIG. 9 is a diagram for explaining the explanation.

FIG. 10 is a configuration diagram of a conventional PLL circuit.

FIG. 11 is a configuration diagram of a filter.

FIG. 12 is a configuration diagram of a filter.

[Explanation of symbols]

 1 voltage control type variable oscillator (VCO) 2 frequency divider 3 phase detector 4 filter 5 counter 6 decoder 7 counter 8 decoder 9 drive current source

Claims (4)

[Claims] 1. An output of a voltage-controlled variable oscillator is supplied to a phase detector via a frequency divider, and the frequency-divided signal is supplied to a phase detector so that a signal based on a phase difference between the frequency-divided signal and a reference pulse is subjected to the voltage control. In a PLL circuit for supplying a phase-locked oscillator to obtain a phase-locked oscillation signal, the gain of the phase detector is made variable, and the gain is controlled according to the phase difference between the divided signal and the reference pulse. PLL circuit. 2. The PLL circuit according to claim 1, wherein the phase detector is composed of a multiplier, the drive current of the multiplier is controlled to make the gain variable, and the voltage-controlled variable oscillator A PLL circuit that counts output signals, decodes the count value at the timing of the reference pulse, and controls the drive current according to the decode value. 3. The PLL circuit according to claim 1, wherein the phase detector is configured to switch a current source circuit according to a phase difference and integrate the switched current to obtain an output. A PLL circuit in which the current value of the circuit is controlled to make the gain variable. 4. The PLL circuit according to claim 1, wherein the gain is controlled by weighting a control amount for the phase difference.