JPH0749809A - Cache memory controller - Google Patents

Abstract

PURPOSE:To prevent the performance of a large-scale multiprocessor system from decreasing and guarantee no contradiction by dividing an operation group of processor elements and putting them in synchronous units which exclusively use a network only at the time of signal transmission. CONSTITUTION:The processor elements 10-1 to 10-n are connected to a common bus 30. The synchronous unit control parts 13-1 to 13-n in the respective processor elements 10-1 to 10-n perform control so that the common bus is exclusively used only at the time of signal transmission. Monitor parts 14-1 to 14-n after exclusively using the common bus 30 by the synchronous unit control parts 13-1 to 13-n monitor the common bus 30 only for a maximum time required to receive a response to a request. State management parts 15-1 to 15-n determine the states of data of cache memories 12-1 to 12-n according to the contents of a signal which is inputted within the monitor time. Consequently, the utilization efficiency of the common bus 30 is improved to prevent the speed of the large-scale common bus from decreasing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control device in a multiprocessor system, and more particularly to a method for making data in the cache memory consistent.

[0002]

2. Description of the Related Art In a multiprocessor system in which a plurality of processors and a main memory (main memory device) shared by the processors are connected via a shared bus, it is possible to avoid all accesses of the processors from being concentrated on the shared bus. Therefore, each processor is generally equipped with a cache memory. On the other hand, in such a multiprocessor system, since each processor has its own cache memory, copies of the same data exist in a plurality of cache memories, thus maintaining the consistency of these data. There is a need.

Therefore, in a multiprocessor system,
When there is a change in the data in the cache memory of each processor, not only the main memory but also other cache memories are notified of the data change, and the consistency of the data in the system is maintained. Is called a cache memory consistency (coherency) protocol, and various protocols have been proposed.
Then, these protocols have the following configurations in order to make them consistent.

That is, when each processor performs an operation, it occupies the shared bus until the operation is completed, and
The signal corresponding to the operation is broadcast on the shared bus. On the other hand, other processors monitor the shared bus,
When the corresponding block is held in the cache memory, the consistency is guaranteed by the process of changing the state of the block according to the signal.

For example, a case of processor read miss in the Illinois protocol will be described below as such a consistent protocol. (A) When the processor performs a read operation and causes a cache miss, the processor makes the read miss signal significant,
Request data from the shared bus. (B1) When data is sent from another cache memory, the data is registered in the "Shared Clean" state (usually, data from another cache memory is faster and has higher priority than data in the main memory). To reach). (B2) If there is no data in the other cache memory, the data is sent from the main memory, and in this case, the data is registered in the "Private Clean" state.

As described above, in the conventional consistent protocol, the two operations (a) and (b1) or (b2) are combined into one indivisible operation, that is, after the operation of (a) is started. Until the operation of (b1) or (b2) is completed, it is regarded as one synchronization unit, and during this period, the bus exclusive state is not released.

[0007]

However, the limitation of "treating some operation groups as indivisible operations on the bus" in the above-mentioned conventional consistent method is not so problematic in a small multiprocessor. Although it does not occur, it becomes a big problem when a large-scale system or bus is replaced with a general-purpose network connection network. For example,
Considering a large-scale multiprocessor system, the propagation delay of signals flowing through the bus cannot be ignored. The same applies when a general network connection network is considered.

That is, when setting the same synchronization unit as in the conventional system in such a large-scale system, in order to guarantee the consistency of the cache memory, the propagation delay time is taken into consideration, and The maximum delay time shall be the synchronization unit. As a result, the larger the system size, the longer the network occupancy time due to the operation of one processor and the lower the system performance. Therefore, such a configuration cannot be adopted at all.

On the other hand, in order to deal with such a problem, it is conceivable that each processor sets its own synchronization unit without considering the delay of the signal from the bus. That is, this is a method in which the bus is exclusively used as an operation unit of each processor. However, when using such a method,
The conventional cache memory consistency method has the following problems. That is, in the cache memory consistent method so far, the state transition event of each cache memory is broadcast at the same time as the event occurrence by the global clock as the system. However, when the above-mentioned synchronization unit is set, the broadcast of such an event occurrence is delayed, and due to the distance from the source,
Occasionally, there is a case where the notification is reversed. Therefore, such a reversal of the notification causes a problem that the consistency of the cache memory cannot be guaranteed.

Such a problem will be described by taking a processor read miss by the above-mentioned Illinois protocol as an example. First, as described above, conventionally, the operation (a) and the operation (b1) or (b2) are performed by one indivisible operation. On the other hand, the operations (a), (b1),
Consider dividing into (b2) and performing each operation independently.

FIG. 2 shows a main part of a multiprocessor system for explaining this. Note that, in FIG. 2, a processor and the like are omitted in order to avoid complication. In the figure, reference numerals 1 and 2 denote cache memories, and it is assumed that the cache memories 1 and 2 and the main memory 3 are connected via a bus 4. Further, there is a relation of n> m, where n is a time during which the operation is transmitted between the cache memory 1 and the main memory 3, and m is a time during which the operation is transmitted between the cache memory 2 and the main memory 3.

Consider the case where a block of the cache memory 1 is read when a processor read miss occurs in the cache memory 2 when the cache memory 1 is dirty in such a configuration. Then, at this time, it is assumed that the cache memory 1 has correct data and the main memory 3 has old incorrect data (the write hit is repeated in the cache memory 1 and the data is updated).

The flow of events is shown below. In the cache memory 2, a processor read miss occurs for the block X. Block X in cache memory 1 at the same time as above
On the other hand, swap-out (write-back of data to the main memory 3) occurs. After m hours, the cache memory 2 receives the data (old / incorrect) from the main memory 3. That is, n> m
Due to the above relationship, the data from the cache memory 1 has not reached the main memory 3 at this point. After n hours, the main memory 3 receives the data (correct) from the cache memory 1. After n + m time, the cache memory 1 receives the data request from the cache memory 2, but the block X is not present because it is swapped out. In this case, the cache memory 1 normally processes the data request of the cache memory 2 in this case. Therefore, the cache memory 2 cannot receive correct data.

In the above-mentioned operation, in the conventional method, when either one of the processor read miss and the swap out takes the bus right, and the processor read miss takes the bus right, the swap out occurs. Is waited, and the correct data from the cache memory 1 is transferred to the cache memory 2. When the swap-out takes the bus right, the processor read miss is waited, the swap-out is performed to the main memory 3, and then the correct data is transferred from the main memory 3 to the cache memory 2. . On the other hand, when the operation group is divided as described above, data from another cache memory does not always arrive early and preferentially, old data is received and the consistency of the cache memory is guaranteed. It had a problem that it could not be done.

The present invention has been made in order to solve the above-mentioned conventional problems. Even in a large-scale multiprocessor system, the performance is not deteriorated, and it is possible to guarantee the consistency of the cache memory. An object is to provide a cache memory control device.

[0016]

The cache memory control device of the present invention is a cache memory control device of a multiprocessor system in which processor elements each including a processor and a cache memory are connected to a network having a broadcasting function. , Each of the processor elements releases a right of monopolizing the network by the synchronization unit controller that exclusively occupies the network only when a signal is sent from each processor element, and then a response to a request from the processor element is released. A monitoring unit that monitors an input signal from the network for the maximum time required to be received, and a self-cache memory that generated the request according to the content of the input signal during the monitoring time by the monitoring unit. Data in It is characterized in that a status management unit that determines a state.

[0017]

In the cache memory control device of the present invention, for example, when a read miss occurs in the processor element and a data request for this read miss occurs, the synchronization unit control unit occupies the shared bus or network only at the time of the data request. Claim the right to do. After the processor element releases the exclusive right, the monitoring unit monitors a signal input from the shared bus or the network for a predetermined maximum time required for receiving a response to the request.

The state management unit determines the state of the data in the cache memory based on the signal input at the time monitored by the monitoring unit. For example, during the monitoring time, when the data for the read miss is input and the write hit signal is input from another processor element, the input data and the data hit by the other processor element do not match, The entered data is invalid and the cache memory status is "Invalid".
Becomes In addition, in other cases, the state management unit determines the state of the cache memory after the monitoring time according to a predetermined rule. Therefore, even when the processor element has given up the right to exclusively use the shared bus and the network, it is possible to guarantee the consistency of the data in the cache memory.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a cache memory control device of the present invention. The illustrated apparatus includes a plurality of processor elements 10 (10-1 to 10-n), a main memory 20, and a shared bus (network) 30. The processor elements 10 are the processors 1 respectively.
1 (11-1 to 11-n) and the cache memory 12
(12-1 to 12-n). Since the processor elements 10-2 to 10-n have the same configuration as the processor element 10-1, the internal configuration is omitted from the drawing, and the configuration common to each processor element 10 is the processor 11 and the cache memory 12. As described below.

The processor 11 is a control unit that controls various controls, and particularly in a shared memory multiprocessor system, the cache memory 12 and the main memory 20.
The data write / read control between the cache memories 12 and the data transfer between the cache memories 12 are controlled. The processor 11 has a synchronization unit control unit 13, a monitoring unit 14, and a state management unit 15 as a control device of the cache memory 12. The synchronization unit controller 13 has a function of dividing an operation into synchronization units. Incidentally, this division will be described later.

The monitoring unit 14 also includes a buffer memory 14
a for monitoring data buffered at a predetermined monitoring time. The predetermined monitoring time here means the processor element 10
When a request is issued from the system, it refers to the maximum system delay time required from the start of the request until the response is received. Further, the state management unit 15 has a predetermined rule, and during the monitoring time by the monitoring unit 14,
When any response signal is input, the state of the cache memory 12 is determined according to this rule.

The cache memory 12 has a known function as a cache memory and also has a state management unit 15
The state of the data block stored by is determined. The main memory 20 is a memory shared by the processor elements 10, and the shared bus 3
Reference numeral 0 is a bus connecting the processor element 10 and the main memory 20. In this embodiment, a network connecting the plurality of processor elements 10 and the main memory 20 which is a shared memory of these processor elements 10 will be described as a shared bus 30, but
The shared bus 30 includes a plurality of processor elements 10.
The same applies to a general-purpose network having a broadcasting function between them.

Next, an example of division of the operation by the synchronization unit controller 13 will be described by taking the case of the Illinois protocol as an example. FIG. 3 shows the state transition of the Illinois protocol.
The numbers in parentheses in FIG. 3 correspond to the following numbers.

(1) Processor read miss (a) When the processor 11 performs a read operation and causes a cache miss, the read miss signal is made significant and data is requested to the shared bus 30. (B1) Cache memory 12 or main memory 20
Waits for the data sent from, and when the data is sent from another cache memory 12, the data is
Register in the state of "ed Clean". (B2) When data is sent from the main memory 20 (when there is no data in the other cache memory 12)
Registers data in the state of "Private Clean".

(2) Bus read miss This is a request from the processor 11 that is a slave of the shared bus 30 (the processor that receives this request while another processor 11 is issuing the request). You have a copy of your data and you receive a "bus read miss".

The state is "Private Clean"
Or in the case of "Shared Clean" (a) Cache memory 12 on the master side (cache memory of the processor element that issued the request)
Block-transfers the data requested to the cache memory 12 and sets the state of the cache memory 12 to "Shared Clean". When the status is "Dirty" (a) The requested data is block transferred to the cache memory 12 and the main memory 20 on the master side, and the status of the cache memory 12 is changed to "Shared C".
to "lean".

(3) Processor write hit state is "Dirty" or "Private Cl"
In case of “ean” (a) The data is immediately written in the cache memory 12,
Set the state to "Dirty". When the state is "Shared Clean" (a) The processor 11 sends an invalidation signal to the shared bus 30. Also, write the data in the cache memory 12,
Set the state to "Dirty".

(4) Processor write miss (a) When a cache miss occurs, the write miss signal is made significant and the shared bus 30 is requested for data. (B) Wait for the data sent from the cache memory 12 or the main memory 20, and set the data to “Dirty”
In this state, it is registered in the cache memory 12. At this time, the data from the cache memory 12 is prioritized and registered. Then, the processor 11 writes to the cache memory 12.

(5) Bus write hit state is "Shared Clean" (a) The processor 11 invalidates the state of the corresponding data.

(6) Bus Write Miss When the processor 11 that is a slave of the shared bus 30 has a copy of the requested data and receives a "bus write miss", the status is "Private Clean". Or "Sh
in the case of "ared Clean" (a) Block transfer of the requested data to the cache memory 12 on the master side, and the cache memory 12
Disable the state of. When the status is “Dirty” (a) The requested data is block transferred to the cache memory 12 and the main memory 20 on the master side, and the status of the cache memory 12 is invalidated.

Above, (a), (b), (b1), (b
Operations such as 2) are individually performed in one synchronization unit,
That is, it is performed as a unit for requesting the bus right.

Then, the above (1) processor read
In the case of the miss and (4) processor write miss, it is necessary to wait for the data sent from the other cache memory 12 or the main memory 20, and the order from these is not guaranteed. Therefore, the monitoring unit 14 buffers the signal from the shared bus 30 in the buffer memory 14a during the maximum delay time of the system.

Further, the state management unit 15 determines the state of the cache memory 12 based on the signal sent by the monitoring unit 14 within the monitoring time. In addition, the rules for the decision are as follows in order of priority. (1) Swap out from other cache memory 12 (2) Data block transfer from other cache memory 12 (3) Data block transfer from main memory 20 The state management unit 15 monitors in accordance with such priority order. The state of the cache memory 12 is written after a lapse of time. Incidentally, the division of the operation of the processor element 10 is the division of the operation on the shared bus 30, and it is not necessary to divide the operation regarding the state transition of the cache memory 12 as described above.

Further, considering the signal delay time, there exists a state in which an event occurs at the same block as if the events occurred at the same time. Various state transitions in such a case will be described below by taking two processor elements as an example.

4 to 10 are views showing the state. In these drawings, Pi and Pj are processor elements, and each processor element P
The length indicated by the thick line on the time axis of i, Pj is the shared bus 30.
The time when the monitoring unit 14 monitors the signal flowing (broadcast) is shown.

[1] When a plurality of read misses to the same block occur at the same time (FIG. 4) Also, in FIG. 4, “read miss” means that the processor has made a read miss, and is “RM”. Is a read miss signal, “SH” is a shared response, and “shared”
Indicates that the cache memory status is Shared Clean
It has become. In the case of (a), before the read miss signal from the processor element Pi reaches the processor element Pj, the processor element P
This is the case where a read miss signal is output from the j side to the same block. In the case of (b), the read miss signal is output from the processor element Pi to the processor element Pj.
This is the case where the read miss signal is output from the processor element Pj side after the arrival at the. In the case of such two patterns, the processor P that has received the read miss signal
i returns a response SH to be shared and displays its own status as “Sha
"Red Clean".

That is, these processor elements Pi,
After sending the read miss signal, Pj receives the corresponding block of data from the cache memory 12 or the main memory 20 of another processor element. In either case, this block is shared and the main memory 20
Since it also matches the block of “SharedCl
ean ”.

[2] When a read miss and a write hit for the same block occur at the same time (FIG. 5) Also, in FIG. 5, “write hit” means that the processor has caused a write hit, and is “WH”. Indicates a write hit signal, and “IV” indicates an invalidation response. Then, "shared" indicates that the state of the cache memory is SharedClean, and further,
“Dirty” indicates that the state of the cache memory is Dirty
And “invalid” indicates that the cache memory state has become invalid.

Here, in (a), the write hit signal from the processor element Pi is the processor element Pj.
In the case of (b), the read hit signal is output to the same block before the processor element Pj reaches the processor element Pj. This is the case where the read miss signal is output from the element Pj side.

In the case of such two patterns, the processor Pi which has received the read-miss signal both returns the response IV for invalidation, and sets its own state to "Dirty". Further, when the processor element Pj receives the invalidation response, it sets its own state to “Invalid”. That is, in the cache memory 12 of the processor element Pi,
Since new data has been written, that block does not match the block in the main memory 20, and if another cache memory 12 has the same block, that data becomes invalid.

It should be noted that the processor element Pj changes the state of the cache memory 12 to "Invalid" after the monitoring time.
Since it becomes "id", the read miss signal is transmitted again thereafter.

[3] When a read miss and a write miss for the same block occur at the same time (FIG. 6) Also, in FIG. 6, “write miss” indicates that the processor has caused a write miss, and “WM” indicates a write miss. Represents a signal. Here, in (a) and (b), as in the case of the above [2], a read miss is made to the same block from the processor element Pj side before the write miss signal from the processor element Pi reaches the processor element Pj. When the signal is output and after the write miss signal reaches the processor element Pj from the processor element Pi, the processor element P
This is the case where the read miss signal is output from the j side. Further, (c) is a case where the read miss signal from the processor element Pj first reaches the processor element Pi.

In such a case, as in the case of [2], the processor element Pi is the processor P in all cases.
A response that invalidates j is returned, and the processor element Pj
After receiving the invalidation response, the
d ". In this case, the processor element Pj
May receive data for a read miss from a processor element other than the processor element Pi or the main memory 20 during the monitoring time, but since data other than the processor element Pi is incorrect data, it is set to "Invalid". It is a thing.

Further, if the processor element Pi is not notified of the occurrence of an event such as a write hit or a write miss from a processor element with a high priority as described later within the monitoring time, the processor element Pi changes its state to "Dirty". ".

[4] When a plurality of write hits or write misses for the same block occur simultaneously (FIGS. 7 to 9) As shown in the figure, there are eight patterns (a) to (h). ) And other than that. That is, the pattern (a) is for the processor Pi that is undergoing a write hit transition.
Receives a write hit signal from the processor element Pj which is another processor element, in which case the priority of the processor is followed. For example, when the received signal has a higher priority than the own processor element, its own state is set to "Invalid", and when the received signal has a lower priority than the own processor element, the received signal is ignored.

In the example shown in FIGS. 7A to 7H, the priority of the processor element is Pi> Pj. Therefore, in FIG. 7A, the processor element Pi sets its own state to “Dirty”. Then, the processor element Pj sets its state to “Invalid”.

In the pattern (b), the processor element Pi makes a write hit in the state of "Shared Clean", the processor element Pj receives the write hit signal, and then the processor element Pj.
This is the case where j sends a write miss signal. in this case,
Unless the processor element Pi receives a notification of occurrence of an event such as a write hit or a write miss from another processor element having a higher priority than itself within the monitoring time,
The own state is set to “Dirty”, and the processor element Pj sets the own state to “Invali” after the monitoring time.
d ".

Next, in the pattern (c), the processor element Pi has a write miss and the processor element Pj
Is a light hit. In this case, since the processor element Pi has a higher priority, the invalidation signal is sent to the processor element Pj, and its own state is set to “Dirty”.

In the pattern (d), the processor element Pi has a write hit and the processor element P has a write hit.
In this example, j is a write miss. Also in this case, the processor element Pi having a high priority returns an invalidation response to the processor element Pj, and sets its own state to "D".
irty ”.

The pattern of (e) is the same as that of (d) above.
Contrary to the above case, the processor element Pi is a write miss and the processor element Pj is a write hit. However, also in this case, since the state transition is performed according to the priority, the processor element Pi having a high priority returns an invalidation response to the processor element Pj, and sets its own state to “Dirty”.

Further, the patterns (f), (g), and (h) are the cases where the processor elements Pi and Pj are both write misses, and when (f) occurs at almost the same time,
(G) is the case where the processor element Pi is generated earlier and the write miss signal arrives earlier than the write miss occurrence of the processor element Pj, and (h) is the case opposite to (g). Also in these examples, the processor element Pi having a high priority is the processor element Pj of the partner.
Returns a response that invalidates the status and sets your status to "Dirty"
And

[5] When a read miss or write miss for the same block and a swap-out occur at the same time (FIG. 10) (a) and (b), a read miss or a write miss occurs in the processor element Pi, and the processors are at about the same time. This is an example of swap-out occurring in the element Pj. In such a case, since the swap-out event is given priority regardless of the priority of the processor element, the data block transferred from the main memory 20 for the read miss or the write miss of the processor element Pi becomes invalid and the monitoring time After that, the processor element Pi sends the read miss signal or the write miss signal again. The swapped out processor element Pj is in a state in which no data block exists in the cache memory 12.

As described above, in the above-described embodiment, the maximum delay time of the system is monitored by the signal from the shared bus 30, and the cache memory 12 according to a predetermined rule.
Since the state transition is determined, the cache memory 2 can receive correct data even in the conventional example shown in FIG. That is, in the example of FIG. 2, the cache memory 2 receives data from the main memory 3 after m hours, but this data is invalidated by the swap-out signal from the cache memory 1 input within the monitoring time. Then, the cache memory 2 again sends the read miss signal, and the correct data is sent from the main memory 3 by the read miss signal.

In the above embodiment, the Illinois protocol was described as an example of the cache memory consistent protocol in the multiprocessor system, but the present invention is not limited to this, and various protocols such as the Berkeley protocol can also be applied. is there.

[0055]

As described above, according to the cache memory control device of the present invention, the operation group of the processor elements is divided into a synchronization unit having a network exclusively at the time of signal transmission, and the request is generated from the request. The maximum time required for the response to is received is to monitor the input signal from the network and determine the data state of the cache memory according to the signal input within this monitored time. Therefore, it becomes possible to replace it with a large-scale bus for a large-scale system or a general-purpose network connection network, and it can be expected to improve the performance of the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram of a cache memory control device of the present invention.

FIG. 2 is a main part configuration diagram of a multiprocessor system for explaining a conventional problem.

FIG. 3 is an explanatory diagram of state transition of the Illinois protocol related to the cache memory control device of the present invention.

FIG. 4 is an explanatory diagram in the case where a plurality of read misses to the same block occur at the same time in the cache memory control device of the present invention.

FIG. 5 is an explanatory diagram when a read miss and a write hit for the same block occur simultaneously in the cache memory control device of the present invention.

FIG. 6 is an explanatory diagram when a read miss and a write miss for the same block occur simultaneously in the cache memory control device of the present invention.

FIG. 7 is an explanatory diagram of a case (1) in which a plurality of write hits or write misses for the same block occur simultaneously in the cache memory control device of the present invention.

FIG. 8 is an explanatory diagram of the case where a plurality of write hits or write misses for the same block occur simultaneously in the cache memory control device of the present invention (part 2).

FIG. 9 is an explanatory diagram of a case (third) in which a plurality of write hits or write misses for the same block occur simultaneously in the cache memory control device of the present invention.

FIG. 10 is an explanatory diagram of a case where a read miss or a write miss and a swap-out for the same block occur simultaneously in the cache memory control device of the present invention.

[Explanation of symbols]

 10-1 to 10-n processor element 11-1 to 11-n processor 12-1 to 12-n cache memory 13-1 to 13-n synchronization unit control unit 14-1 to 14-n monitoring unit 15-1 15-n status management unit

Claims (1)

[Claims] 1. A cache memory control device of a multiprocessor system in which processor elements each including a processor and a cache memory are connected to a network having a broadcasting function, wherein each processor element is a signal of each processor element. A synchronization unit control unit that occupies the network only at the time of transmission, and, after releasing the right of the processor element to occupy the network, the maximum time required for receiving a response to a request from the processor element from the network. And a state management unit that determines the state of the data in the own cache memory that generated the request according to the content of the input signal during the monitoring time by the monitoring unit. Cashe Li controller.