JPH0962578A - Information processor and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the degradation of the use efficiency by avoiding concentration of traffic, which is caused by maintaining the cache consistency in a form adapted to a generous memory consistency model, on a bus at a synchronizing point in the parallel computer system. SOLUTION: A cache 11 requests a common bus 15 to a bus arbiter 16 and acquires the permission of the use; and when the cache 11 terminates the use, the bus arbiter 16 checks the use condition of the bus, and the bus arbiter 16 continuously gives the permission or the use to the cache no without the use request if there are no users. When this permission of the use is given to the cache 11, the cache 11 checks whether there is data updated after read from a memory 12 or not; and there is such data, this data is written back to the memory 12. A cache 12 monitors written-back data and finds written-back data to check whether the cache itself already holds this data in the address or not. If it already holds this data, it invalidates this data. Thus, data is written back to maintain the consistency in the bus idle time to prevent concentration of write-back at a prescribed synchronizing point.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which a plurality of processors connected via a cache by an interconnection network operate in parallel and a control method therefor.

[0002]

2. Description of the Related Art In a parallel computer system, a cache memory is often attached to each processor in order to respond to an access request to a main memory issued from the processor at high speed and to reduce traffic of an interconnection network. The memory access issued from each processor is performed via the cache memory, and a copy of the data block to be the memory access target is placed in the cache memory. In a parallel computer system, a situation may occur in which multiple copies of the same data block exist in multiple cache memories, but in order to guarantee consistency among these copies,
Conventionally, various methods have been devised / implemented.

The snoop method is generally used in a parallel computer system that uses a bus such as a bus capable of monitoring all transactions in a connection network that interconnects processors and processors and main memory. In the snoop method, the cache memory monitors all transactions issued on the connection network, and if a copy of the data block to be transacted exists in its own cache memory, the necessary coherency maintenance operation is performed. It is something to give.

Further, a directory system is used in a parallel computer system using a coupled network that interconnects processors and a processor / main memory with each other, in which it is difficult to monitor all transactions. The directory method stores and manages, in a storage device called a directory, caching information indicating in which cache memory the copy exists in each data block unit or similar unit, and the cache information from the processor is stored. When a transaction is issued, the occurrence of a transaction is notified to the cache memory having a copy of the transaction target data block based on the caching information obtained from the directory, and the consistency is maintained between the copies.

On the other hand, in order to suppress the access latency to the memory, various loose memory consistency
A model is invented / realized.

Generally, in the loose memory consistency model, a synchronization point is set in the course of processing, and when the processing reaches the synchronization point, the memory
It requires the transaction to be reflected in the system. This means that it is not necessary to reflect the outcome of each memory transaction prior to the sync point.

When the conventional cache coherency maintaining method is used in the parallel computer system which adopts the loose memory consistency model, an unnecessary coherency maintaining operation is carried out for each transaction at that time, and its overhead is Contrary to the purpose of the loose memory consistency model, it can be said that the memory access latency is carelessly increased.

To solve this problem, the overhead of the cache coherency behavior is delayed by delaying it to the point of a synchronization point at which the memory transactions need to be reflected in a loose memory consistency model. The applicant of the present application has already made a proposal to reduce the above-mentioned problem and improve the performance of the system.

[0009]

[Problems to be Solved by the Invention] However, in this way,
Reduces the overhead of unnecessary cache coherency operations by delaying the implementation of cache coherency operations to the point of a synchronization point where memory transactions need to be reflected in a loose memory consistency model. In such a system, since the cache coherency operation is centrally performed at the time of the synchronization point, the traffic is intensively generated on the interconnection network at the time of the synchronization point. There is a possibility that the utilization efficiency of the connection network may drop significantly at the time of the synchronization point.

The present invention has been made in view of the above-mentioned conventional example, and reduces the overhead caused by performing an unnecessary consistency maintaining operation, and at the same time, a mutual connection network is formed by concentrating traffic on the mutual connection network at a synchronization point. An object of the present invention is to provide an information processing device that can avoid a decrease in utilization efficiency and reduce processing overhead associated with a synchronous operation.

[0011]

In order to solve the above problems, the information processing apparatus of the present invention has the following configuration. That is, it is an information processing system including a plurality of processors, a plurality of connection network users including a cache memory and a main memory attached to each of the processors, and a connection network connecting the connection network users to each other. Then, when the processing of each processor reaches a predetermined stage, the coherency holding processing for holding the coherency of the content of the data block existing in the cache memory associated with the processor is executed.

More preferably, if the state of the connection network satisfies a predetermined condition before the processing by the processor reaches the predetermined stage, the data block existing in the cache memory is Performs a consistency process that maintains the consistency of contents.

More preferably, the condition satisfied by the connection network is that the connection network user does not use the connection network.

Further preferably, an arbitration unit is further connected to the connection network for arbitrating the use of the connection network by the connection network user, and the arbitration unit detects that the connection network is not used. Based on the result, the condition is judged, and according to the result, the permission to use the connection network is given to one of the connection network use subjects.

More preferably, the consistency maintaining process is
The updated data block existing in the cache memory is written back to the main memory.

More preferably, the information processing system is a loose memory consistency model.

Alternatively, the bus means, the memory means connected to the bus means, a plurality of bus master means for holding the data read from the memory means by using the bus means and updating the data, and the bus Bus management means for issuing permission to use the bus means to any of the plurality of bus master means when the means is not used by any of the bus master means, the bus master means having reached a predetermined time point. In the case, and when the use permission is issued, the updated data held by the bus means is written back to the memory means.

More preferably, the bus management means does not use any of the bus means after the use of the bus means in accordance with the permission of the bus master means to use the bus means. In this case, use permission of the bus means is issued to the bus master means that used the bus means immediately before.

More preferably, the bus master means that has not obtained permission to use the bus means uses the bus means when the bus master means that has obtained permission to use the bus means does not use the bus means for a predetermined time or longer. Then, the stored updated data is written back to the memory means.

More preferably, the bus master means further comprises processor means connected to the bus master means, and the bus master means stores in the memory means data updated and read from the memory means in accordance with a predetermined instruction issued from the processor means. Write back.

More preferably, 1 of the bus master means
When another bus master unit writes data back to the memory unit, it checks whether the data is duplicated and read from the memory unit to the bus master unit. , The data is invalidated.

Alternatively, in an information processing apparatus that holds the data stored in the memory means in duplicate by the cache means connected to each of the plurality of processors, the data stored in the cache means is the memory means. Determining means for determining whether or not the data stored in the memory is read and updated data, and the cache means if none of the cache means accesses the memory means according to the determination result by the determining means. First write-back means for writing back the data read and updated by any of the means to the memory means, and data read and updated by the cache means when a predetermined time is reached Writing back to the memory means
And write-back means of. .

Further, the control method of the information processing apparatus of the present invention has the following configuration. That is, it is a control method of an information processing apparatus, wherein data stored in a memory means is redundantly held by a cache means connected to each of a plurality of processors, wherein the data stored in the cache means is the memory means. The determination step of determining whether the data stored in the memory is read and updated, and the cache means when the memory means is not accessed from any of the cache means according to the determination result of the determination step. A first write-back step of writing back to the memory means the data read and updated by any one of the means, and the data read and updated by the cache means when a predetermined time is reached And a second write back step of writing back to the memory means.

With the above configuration, since the contents of the cache are written back to the memory when the bus means is free, an operation for maintaining the data consistency between the memory and the cache is performed at any time, and the operation causes congestion of the system. There is nothing to do.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. <Configuration of Multiprocessor System> FIG. 1 is a configuration diagram of a first multiprocessor system of a system for realizing the present invention.

Reference numerals 10 and 20 denote processors, and each processor has a cache 1 via processor buses 14 and 24.
1, 21 are connected. Further, the caches 11 and 21 are connected between the main memory 12 and the caches via the shared bus 15, and based on the request of the processor,
The data inside the caches 11 and 21 is updated and reflected in the main memory 12, and
Cache maintenance is performed by snooping the address information flowing on the bus. The bus arbiter 16 is for arbitrating the right to use the shared bus 15. The shared bus 15 includes an address bus 151, a data bus 152, and a control bus 153, and includes the processor bus 14
Includes an address bus 141, a data bus 142, and a control bus 143. The same applies to the processor bus 24.

FIG. 2 shows the caches 11 and 1 in FIG.
FIG.

The main body of the cache is a cache control sequencer 111 that controls the entire cache, an address tag 112, a status flag 113, an SRAM 114, and a comparator 1.
15, the selector 116 and interfaces 144 to 146 with the processor bus, and interfaces 154 to 156 with the shared bus. The address tag 112, the status flag 113, and the SRAM 114 correspond to a set of data as a set.

Here, the SRAM 114 constitutes a data block for holding data. Address tag 1
12 holds the address of the data block stored in the SRAM 114, and the status flag 113 holds the SRAM 114.
It plays a role in maintaining the state of the above data. This state will be described later. The comparator 115 has an address tag 1
12 and the processor bus 14 or shared bus 1
Compare with the address that comes from 5. Selector 11
6 selects the data in the SRAM 114 from the comparison result of the comparator 115. It is possible to determine whether there is any request target data in the cache by comparing / selecting the addresses by these, and if there is, it is possible to select it. The cache control sequencer 111 controls each module in these caches.

Although the two-way set associative structure is adopted here, these structures are not limited by the present invention. These caches are the processor, the processor bus address interface 1
44, a processor bus data interface 145, and a processor bus control interface 146, and supplies data and the like according to a request from the processor. In addition, these are shared bus 15 with shared bus address interface 154,
It is connected by the shared bus data interface 155 and the shared bus control interface 156, and when a cache miss occurs, data is loaded from the main memory 12 into the cache or the cache information is written back to the main memory according to a request from the processor. Alternatively, the state flag 113 inside the cache is changed based on the control information provided from another cache.

In this embodiment, in the system having the configuration shown in FIGS. 1 and 2, the write-back type cache
It is assumed that a memory invalidation protocol is used.
The invalidation protocol is to read a data block in a cache and invalidate the data block when the data block is written back to the main memory from another cache. An example is shown under which the cache memory coherency is guaranteed based on the control method of the cache memory that conforms to the loose memory consistency model.

Specifically, in a system using a protocol that guarantees the coherency of the cache memory at the time when an instruction for synchronization (hereinafter referred to as a SYNC instruction) is issued from the processor, In order to improve the performance, a data block that will be written back from the cache memory to the main memory at the time when a SYNC instruction is issued in the future, that is, the data block that is rewritten with the latest value inside the cache memory The present invention is applied to allow a data block whose value is not reflected in the memory (hereinafter referred to as “DIRTY” block) to be written back while the shared bus is not used by another bus master. The details of the operation procedure and system configuration of the multiprocessor system will be described below. A block in which the value of the cache block that has been read from the main memory or written back to the main memory and the value of the corresponding data block of the main memory match is called a "CLEAN" block. <Basic Operation of Cache System> First, the basic operation of the cache system itself will be described with reference to the flow charts of FIGS. 1, 2 and 3 to 5. [LOAD instruction] FIG. 3 shows a control procedure by the cache 11 when executing a LOAD instruction for reading a data block from the main memory 12 into the processor 10 (hereinafter, assuming that the LOAD instruction is issued from the processor 10). explain).

In FIG. 3, in response to the LOAD instruction issued from the processor 10, the address output to the address bus 141 and the address stored in the address tag 112 are compared by the comparator 115 (step S3).
01), if there is a cache read hit, the cache 11 supplies data to the processor 10 from the SRAM 114 (step S303).

On the other hand, the LO issued from the processor 10
When a cache read miss occurs with respect to the AD instruction, the cache 11 performs cache miss processing and reads data from the main memory 12 (step S302).
Data is supplied from the SRAM 114 to the processor 10 (step S303). In this case, the cache
The cache 11 does not supply the data to the processor 10 until the read-missed data is supplied to the cache 11.

The read cache miss process is performed in the procedure as shown in FIG.

First, it is determined whether cache replacement is necessary (step S501). That is, SRAM1
When all 14 are used and there is no free capacity, the block used is replaced. In the case of replacement, a block to be replaced is determined by a predetermined method, such as a block used in the farthest past or a block determined by a priority given in advance (step S502). Next, the block to be replaced is written back to the main memory 12 (step S50).
3). As a result of the write-back, it is guaranteed that the block to be replaced in the cache 11 and the corresponding data block in the main memory match, and the block can be deleted from the cache.

In this state, a request to use the shared bus 15 is issued to the bus arbiter 16 (step S50).
4).

After obtaining the use permission of the shared bus 15, the cache 11 transfers the address of the read access to the shared address bus 151, issues a read request to the shared control bus 153, and outputs the shared data bus. 1
Wait until data is supplied to 52 (step S50
6).

The main memory 12 requests read,
Also, the address of the read access is accepted, and data is supplied to the shared data bus 152 (step S
507).

The cache 11 has a shared data bus 152.
The data supplied to the SRAM 11 in the cache 11
It is registered in the entry of the data block of No. 4 (step S508).

After that, the state flag 113 is set to a predetermined value (step S509). Although the value of the status flag 113 will be described later, it is set to "CLEAN" in the case of a read miss and set to "DIRTY" in the case of a write miss.

In this way, if there is a cache miss, the required data block can be read from the main memory 12 and the LOAD instruction can be executed. [STORE instruction] FIG. 4 shows a control procedure by the cache 11 when executing the STORE instruction for writing data from the processor 10 to the cache 11 (hereinafter, it is assumed that the STORE instruction is issued from the processor 10). ).

In FIG. 4, in response to a STORE instruction issued from the processor 10, the address output to the address bus 141 and the address stored in the address tag 112 are compared by the comparator 115, and the matching address is found. If there is a cache hit (step S401), and if a cache write hit occurs, the processor 10 supplies data to the cache 11 (step S403).

STORE issued from the processor 10
If a cache write miss occurs for the instruction, the cache miss process of FIG. 5 is performed (step S40).
2) The cache write hit process is performed after the corresponding entry is obtained in the cache.

As described above, LOAD / STORE
The instruction is being processed in the cache. [SYNC instruction] The processing for the SYNC instruction will be described with reference to FIG. The SYNC instruction requests that the processor reflect the memory transaction issued so far in the system. In the present embodiment, the DIRTY block is forced to maintain the consistency of the data block of the cache. It is an instruction to write back. SY for decoding control signals
When the NC instruction is detected, the cache control sequencer 11
In FIG. 1, the write-back is performed by the write-back processing described later and shown in FIG. [Write-back Control (Explanation by Flowchart)] Next, a control procedure for executing write-back from the cache to the memory, which is a feature of the present system, will be described with reference to the flowchart of FIG. This procedure is shown in FIGS.
The "write-back process" step is executed.

The feature of this system is that the cache write-back is performed in accordance with the loose consistency model. Conventionally, when a data block (“DIRTY” block) that does not reflect the value is read from the main memory after being rewritten by another processor or the like with the latest value, the write-back is executed. However, this system does not do this. The write-back is performed as follows: 1: When a SYNC instruction is issued from the processor; in this case, all "DIRTY" blocks in the cache are written back to the main memory.

2: When a cache miss occurs and the "DIRTY" block is selected as a replacement target; in this case, only the replacement target block in the cache is written back to the main memory.

These cases 1 and 2 will be referred to as high-priority write-back in the sense that a shared-bus use request (shared bus request) is made and the bus use right is acquired to execute write-back. To do. Further, 3: When the "DIRTY" block exists in the cache and the shared bus is free; in this case, when the shared bus is free, the "DIRTY" block is sequentially written back to the memory. In this method, the case where the shared bus is vacant is determined based on the implicit shared bus use permission signal given from the shared bus arbiter. No shared bus request is issued to perform this write back. The implicit shared bus use permission signal will be described later in detail.

The write back in the case of this 3 will be called a low priority write back.

As described above, the write back is performed in the three cases, and the control in each case is realized by the procedure of FIG.

When the write-back process is started, it is judged whether or not there is a "DIRTY" block in the cache (step S801), and if there is, that is, in the case 1 (FIG. 1).
If it is called from 1), S from the processor
Until the cache control sequencer 111 issues a request for the shared bus (step S803) after detecting the write back due to the issuance of the YNC instruction (step S803), there is no "DIRTY" block inside the cache. The write back is repeatedly performed (steps S804 to S805).

In case 2 (when called from FIG. 5), that is, when a cache miss occurs, "DIRT
If the Y "cache block is replaced (step S806-Yes), a shared bus request is issued to obtain permission to use the common bus 15 (step S807).
Replace the cache block to be replaced with the main memory 12
Write back to (step S808).

In case 3, the implicit permission to use the shared bus is given (step S809-Ye).
s), write back of the "DIRTY" block is performed (step S810).

FIG. 6 shows "DIRTY" in main memory.
9 shows a control procedure for executing write-back processing of a data block, which is a write-back execution procedure of high priority (steps S804 and S808) and low priority (step S810) of the write-back procedure in FIG. Hereinafter, the write-back processing to the main memory 12 is the cache 1
It will be described as being issued from 1.

FIG. 6 starts immediately after the cache 11 requests the right to use the shared bus 15. In the high-priority write-back execution procedure of FIG. 6, the cache 11
After acquiring the right to use the shared bus 15 (step S60)
1), the write-back request source information to the shared control bus 153 and the address of the write-back access to the shared address bus 151 are transferred, and the write-back request is issued to the shared control bus 153 (step S602). ), And supplies the data to be written back to the shared data bus 152 and writes the data in the main memory 12 (step S603). Then, the state flag of the write-back cache block is set to "CLEAN" (step S604).

In the low-priority write-back execution procedure, the shared bus request is not issued, so that the procedure starts from step S602.

On the other hand, when a write back request is issued from the cache 11, the caches other than the cache 11, for example, the cache 21, snoops the address transferred to the shared bus 15 (step S611) and sets the address tag in the cache 12 to the address tag. Search (step S61)
2). As a result of the search, the copy of the data of the snooped address is valid in the address tag, that is, "DIR".
If it is held in TY "or" CLEAN "(step S613), the status flag corresponding to the data block held in the valid status is invalidated (" INVA ").
LID "). This invalidation is the consistency maintaining operation in this example.

When the write-back process is performed in this way, the data held in the cache that was written back becomes valid as the data that matches the main memory, and the write-back held in the other caches is performed. The invalidated data is invalidated and the data is kept consistent.

FIG. 7 is a state transition diagram of the state flag at the time of executing each memory transaction.
12 is a summary of how the status flag changes as a result of the control of the cache control sequencer according to FIGS. 6, 8 and 11. Hereinafter, the state flag 113 of the cache 11 will be described.

In FIG. 7, the status "INVALID" indicates that the data entry managed by the status flag 113 is invalid. The state "CLEAN" indicates that the data entry managed by the state flag 113 has not been rewritten even once after being read from the main memory. Although the same value as the main memory is stored in the data entry, the latest value may be stored in the data entry of another cache. The state "DIRTY" indicates that the data entry managed by the state flag 113 is read from the main memory and then rewritten with the latest value one or more times, and the value is not reflected in the main memory. The latest value is stored in the data entry. In each of these states, the state transitions as shown in FIG. 7 depending on the processing. Hereinafter, the circled numbers correspond to those in FIG. 7.

When the LOAD instruction is issued from the processor 10 to the data in the "INVALID" state,
Cache miss processing is performed, and the status flag is "CLE
Transition to "AN".

When the STORE instruction is issued from the processor 10 to the data in the "INVALID" state, the cache miss process is once executed and the state flag transits to "DIRTY".

When the LOAD instruction is issued from the processor 10 to the data in the "CLEAN" state, the cache read hit process is executed and the state flag transits to "CLEAN".

When the STORE instruction is issued from the processor 10 to the data in the "CLEAN" state, the cache write hit process is executed and the state flag transits to "DIRTY".

When a snoop hit is made to the write back process of the external bus master for the data in the "CLEAN" state, the consistency maintaining operation (invalidation transaction from another processor) is executed and the state flag is set to "INVALID". Transition to ".

When the LOAD instruction is issued from the processor 10 to the data in the "DIRTY" state, the cache read hit process is executed and the state flag remains "DIRTY".

When the STORE instruction is issued from the processor 10 to the data in the "DIRTY" state, the cache write hit process is executed and the state flag remains "DIRTY".

When the write-back process to the main memory is executed for the data in the "DIRTY" state, the state flag transits to "CLEAN".

For data in the "DIRTY" state,
When a snoop hit is made to the write-back processing of the external bus master, the consistency holding operation (invalidation transaction from another processor) is executed, and the status flag transits to "INVALID".

By changing the states as described above, the consistency between the cache block and the main memory in the configuration of FIG. 1 can be maintained. <Bus Arbiter> Next, a configuration for giving an implicit shared bus use permission to the cache by the bus arbiter in order to realize the low-priority write-back, which is a feature of the present invention, will be described with reference to FIGS. To do.

FIG. 9 is a block diagram of the bus arbiter 16.

The shared bus request signal (BR1 *) 161 of the cache 11 and the shared bus request signal (BR2 *) 162 of the cache 21 are input from the caches 11 and 21 as part of the control bus 153. The shared bus request signals 161, 162 are true (requested) when L.

A shared bus grant signal (BG1 *) 165 for the cache 11 and a shared bus grant signal (BG2 *) 166 for the cache 21 are output. These signals are also true (request permission) when L.

Further, the bus arbiter 16 is also supplied with a bus busy signal 167 indicating whether each bus master is using the shared bus (BB *: L indicates that a certain bus master is using the bus) 167. There is. The bus arbiter 16 is a synchronous circuit and has a system clock (B
CLK) 168, each signal is latched at each rising edge 169
a to 169e, and the combinational circuit 160 transits each state according to the signal.

FIG. 10 shows an example of the arbitration timing of the shared bus. In the present embodiment, each shared bus master issues a bus use request as shown in FIG. 10, and at the rising time t1 of the bus clock (BCLK) at which BB * = H is detected,
If you recognize that you have been granted the bus permission (BG * = L), assert BB * to L in the next bus cycle to declare the use of the shared bus, and then use the shared bus yourself. While continuing to assert BB *,
It is assumed that shared bus arbitration is in progress.

The basis of this arbitration algorithm is to start arbitration of the right to use the bus after detecting the transition of BB * from H to L (that is, after a new bus master starts using the bus). The bus permission is given to the bus master having the highest priority at the time.

The priority order is as follows at the start of arbitration.

First, the following two groups are classified based on the presence / absence of a bus use request.

Priority A: Bus master issuing a bus request Priority B: Bus master not issuing a bus request but having the right to use the bus now, however, priority A> priority B.

In the priority A group, the order of each bus master is determined by the round robin method.

That is, assuming that there are N bus masters (N = 2 in this embodiment), the bus master number i (0≤i≤)
N-1) is using the bus i + 1 (mod N)> i + 2 (mod N)>…> i + N-2 (mod N)> i + N-1
(mod N)> i. According to this order, the bus use right is given to the bus master issuing the bus request.

Only when no bus master issues a bus request, the bus use permission is given to the bus master having the right to use the bus based on the priority B as it is. The usage permission that is issued even when there is no usage request is called an implicit usage permission.

The arbitration ends at the stage (when BG * is asserted) when the next bus master is decided according to the above-mentioned priority. However, if the bus master determined by the arbitration is based on the implicit bus use permission, and before the bus master that has received the implicit permission recognizes its own bus use right at BB * = H, another bus master When a bus use request is issued from the server, arbitration is performed.

In FIG. 10, first, the cache 11
When the shared bus request BR1 * is issued from (bus master 1) and the bus arbiter 16 detects it at the timing t1, the enable signal BG1 * is output in time for the next clock timing t2. Then, the cache 11 outputs the bus busy signal BB * and occupies the bus. If the bus request BR2 * is output from the cache 21 (bus master 2) in the meantime, it is detected at timing t3 and the permission signal BG2 * is issued according to the priority. The cache 21 waits while the cache 11 is using the bus, recognizes that at the timing t5 when the shared bus 15 becomes free, and outputs the bus busy signal BB * to use the bus.

When the cache 21 stops requesting the bus,
That is, when BR2 * is set to H, the bus arbiter 16
Since no common bus request is issued from any of the bus masters, the cache 21 which is the bus master currently in use.
Will continue to give permission to use the bus. Cache 2
Although No. 1 once releases the bus, it detects that the use permission is continuously given at timing t6 and continues to use the bus.

In this example, the cache write-back processing is performed at this timing, that is, the timing shown in FIG. 10B, and this is steps S809, S in FIG.
Corresponding to 810.

As described above, in FIG. 10, BG2 * is given to the bus master 2 even after BR2 * changes to H ((a) in the figure), but this portion is an implicit bus use permission. Yes, in contrast, the bus master 2 is BR2
Bus is used again without asserting *.
((B) in the figure) By doing so, the bus arbiter 16 can give the implicit use permission of the bus to the bus master who was using the bus immediately before when the shared bus is free. it can. <Write-back Control (Explanation by Signal)> How the low-priority write-back is executed when the implicit bus use permission is given in this way will be described with reference to FIG. This is step S80 in FIG.
This will be a more detailed description of 9,810.

In FIG. 2, when there is no access from outside the cache, the cache control sequencer issues the value of the internal register 196 to the address -m171 and checks the status of the status flag 113 obtained thereby through the status signal line 192. To do. As a result, when the block is judged to be "DIRTY", if the implicit shared bus use permission signal is received to the shared bus control interface 156, the "DIRT" is transmitted.
Y ”block to write back low priority SC
Notification is made via the ont signal line 195.

Next, it is confirmed that BG1 * 165 is L at the rising edge of the bus clock BCLK168 satisfying BB * = H (that is, implicit bus use permission) even though BR1 * 161 is not in a state to be asserted. The recognized shared bus control interface 156 is B
Drive B * low to declare the use of the shared bus.
Since the obtained bus use right is implicit, it does not hinder the operation of other bus masters.

The cache control sequencer 111, which has recognized that it has obtained the right to use the shared bus 15, generates an address to be written back from the address-m171 and the upper address address-h'173 fetched by the address-m171. It is supplied to the shared bus address I / F 154 and driven onto the shared bus 15. At the same time, the data on the SRAM 114 to be selected at that time is selected by the select signal 193 for the selector obtained by passing the comparator control signal 176 through the comparator 115, and is driven onto the Data signal line 174. The data is driven onto the shared bus through the shared bus data I / F 155, and the write back operation for the main memory 12 is executed.

At the same time, the cache 21 snoops the bus, and when the above write-back operation is executed, the inside of its own cache is inspected, and if the corresponding entry exists, its cache is checked. The status flag 113 is invalidated.

With this mechanism, the performance of a system using a protocol that guarantees the consistency of the cache memory when a synchronization instruction (hereinafter referred to as a SYNC instruction) is issued from the processor. In order to improve performance, a data block that will be written back from the cache memory to the main memory when a SYNC instruction is issued in the future is written in advance when the shared bus is not used by another bus master. It will be possible to restore the system and improve the performance of the system.

[0093]

Other Embodiments In the previous embodiment, the cache control sequencer 111 gives the implicit bus use permission by the bus arbiter 16 even if there is a low priority write-back request in the cache. It was not possible to write it back to the main memory 12 unless I waited for. In this method, if a bus master that does not have a write-back request has an implicit bus use permission, the bus master does not use the bus, and another bus master has a low-priority write-back request, Will reduce the efficiency of bus usage.

Improving that, even when an implicit bus use permission is given to a certain bus master, when that bus master does not use the bus, another bus master has a write-back request of low priority. In this case, the method of improving the bus usage efficiency by canceling the implicit bus usage permission given to the bus master and granting the bus usage permission to the bus master with the low-priority write-back request is explained. The second embodiment will be described.

The configuration of the entire system, the configuration of the cache system, and the flow of each processing are the same as those of the first embodiment in FIGS.

FIG. 12 shows a control procedure when the cache performs the write-back in the second embodiment. What is different from FIG. 8 in the first embodiment is that one path is newly added as an implementation method in the case of low priority write-back. In the present embodiment, write-back is performed in the following manner: 1: When a SYNC instruction is issued from the processor 2: A cache miss occurs and the replacement target is "DIR".
When the "TY" block is selected 3: When the "DIRTY" block exists inside the cache and the shared bus is free In addition to the above three, 4: When the "DIRTY" block exists inside the cache and the shared bus Is not granted permission (including the case where other bus masters are given implicit permission)
However, there are four cases where other bus masters are not using the bus.

The cases of 1 to 3 have already been described in the previous embodiment, and the description thereof will be omitted. In the case of 4, the right to use the shared bus is not given to itself, but it is determined that the bus is in that state because no other bus master is also using the bus. Also, the write back of 4 will be referred to as a low priority write back.

FIG. 12 shows the above. Step S
Steps 1201 to S1210 are steps S801 to S810.
However, if the implicit shared bus use permission is not given in step S1209, the bus busy signal BB is H for a certain period of time, that is, remains unused for a certain period of time (step S1211). -Ye
s), and issues a shared bus request (step S121
2) WRITE back the DIRTY data is executed (step S1213). Note that the write-back in step S1213 issues a shared bus request even though it is a low-priority write-back, so that the use permission for the bus request is confirmed in the same manner as in the high-priority step S60.
It will be called from 1.

The apparatus and procedure for realizing Case 4 will be described in detail below.

In FIGS. 2 and 9, the cache control sequencer 111 issues the value of the internal register 196 to the address -m171 when there is no access from the outside of the cache, and the state of the state flag 113 obtained by this is sent to the status signal. Check through line 192. When it is determined that the block is "DIRTY" as a result, if the shared bus use permission signal is received by the shared bus control interface 156, that "DI" is received.
RTY ”block to write back low priority S
-Notify via the Cont signal line 195.

The shared bus interface 156 that has received the low-priority write-back request waits for an implicit permission to use the bus. At the same time, the state of the shared bus is monitored, and the state in which the bus master is not using the bus even though the implicit bus use permission is given to other bus masters (shared bus inactive state) Check for any.

In the case of the present embodiment, the shared bus inactive state is recognized as a state in which the BB * signal 167 is H for a certain period of time T or more when the implicit bus use permission is not given to itself. To be done.

Here, the constant time T is a value determined as the protocol of the shared bus, and T = 2 when the protocol shown in FIG. 10 of the first embodiment is used.

Shared bus control interface 15 which recognizes T ≧ 2 and recognizes that the shared bus is inactive
6 drives the bus request signal BR1 * to L to obtain the right to use the bus. As a result, the shared bus control interface 156, which has received the bus use permission in the form of the permission signal BG1 * = L, drives the BB * signal 167 to L and implements low-priority write-back.

When the cache control sequencer 111 recognizes that it has acquired the right to use the shared bus, it generates an address to be written back from the address-m171 and the upper address address-h'173 fetched by the address-m171 and shares it. It is supplied to the bus address interface 154 and driven onto the shared bus. At the same time, the data on the SRAM 114 to be selected at that time is selected by the select signal 193 for the selector obtained by passing the comparator control signal 176 through the comparator 115, and is driven onto the Data signal line 174. The data is driven onto the shared bus through the shared bus data interface 155, and the write back operation for the main memory 12 is executed.

The shared bus control interface 156 that has once received the bus use permission deasserts BR1 * at that time, and thereafter executes the subsequent low-priority write-back based on the implicit bus use permission.

At the same time, the cache 20 snoops the bus, and when the above write-back operation is executed, the inside of its own cache is inspected, and if the corresponding entry exists, it is checked. The status flag 113 is invalidated.

With this mechanism, in a system using a protocol in which the consistency of the cache memory is guaranteed at the time when the SYNC instruction for synchronization is issued from the processor, in order to improve its performance, SYNC will be added in the future.
Data that will be written back from cache memory to main memory at the time the instruction is issued.
The block can be written back in advance when the shared bus is not used by another bus master, and the system performance can be improved. Further, in contrast to the previous embodiment, in the present embodiment, when the shared bus is vacant, the right to use is acquired and the write back is performed even if the right to use the bus is not given. Even a bus master other than the bus master using the bus can perform write-back with the use permission accompanying the bus request and the implicit permission to use the bus given subsequently. Therefore, write back can be performed frequently, and concentration of write back transactions can be prevented.

[0109]

As described above, the information processing apparatus and the control method therefor according to the present invention, in a parallel computer adopting a loose memory consistency model, maintain cache coherency for further improving its performance. By providing an operating mechanism, avoiding a decrease in the utilization efficiency of the interconnection network due to the concentration of traffic on the interconnection network at the synchronization point, and reducing the processing overhead associated with the synchronization operation to improve the overall system processing capacity. It has the effect of

[0110]

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a system for implementing the present invention.

FIG. 2 is a diagram showing a configuration of a cache used in a configuration example of the present invention.

FIG. 3 is an LO used in the first embodiment of the present invention.
7 is a flowchart showing a control procedure when executing an AD instruction.

FIG. 4 is an ST used in the first embodiment of the present invention.
6 is a flowchart showing a control procedure when executing an ORE instruction.

FIG. 5 is an LO used in the first embodiment of the present invention.
7 is a flowchart showing a control procedure at the time of a cache miss of AD / STORE instruction execution.

FIG. 6 is a flowchart showing a write-back processing procedure of cache “DIRTY” data used in the first embodiment of the present invention.

FIG. 7 is a state transition diagram of cache state flags in the embodiment of the present invention.

FIG. 8 is a flowchart showing a control procedure when performing write back of the cache used in the first embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a shared bus arbiter according to the embodiment of the present invention.

FIG. 10 is a diagram showing an example of a bus arbitration protocol used in the embodiment of the present invention.

FIG. 11 is an S used in the first embodiment of the present invention.
7 is a flowchart showing a control procedure when executing a YNC instruction.

FIG. 12 is a flowchart showing a control procedure until the cache write-back used in the second embodiment of the present invention is executed.

[Explanation of symbols]

 10, 20: Processor 11, 21: Cache 12, 22: Main memory 14, 24: Processor bus 15, 25: Shared bus 16, 26: Shared bus arbiter 111: Cache control sequencer 112: Address tag 113: Status flag 114: SRAM 115: Comparator 116: Selector 144: Processor Bus Address Interface 145: Processor Bus Data Interface 146: Processor Bus Control Interface 151: Shared Address Bus 152: Shared Data Bus 153: Shared Control Bus 154: Shared Bus Address Interface 155: Shared Bus data interface 156: Shared bus control interface 160: Bus arbiter internal combinational circuit 161: Shared bus request signal 1 (B R1 *) 162: Shared bus request signal 2 (BR2 *) 165: Shared bus grant signal 1 (BG1 *) 166: Shared bus grant signal 2 (BG2 *) 167: Bus busy signal (BB *) 168: Bus clock signal ( BCLK) 170: addr-h 171: addr-m 172: addr-l 173: addr-h '174: Data 175: cache block control 176: comparator control signal 190: processor bus IF control signal 191: shared bus IF control Signal 192: Status signal 193: Select signal 194: L-Cont signal 195: S-Cont signal

Claims (13)

[Claims] 1. An information processing system comprising: a plurality of processors; a plurality of connection network users including a cache memory and a main memory attached to each processor; and a connection network interconnecting the connection network users. In the system, when the processing of each processor reaches a predetermined stage, execute the coherency processing to maintain the coherency of the contents of the data block existing in the cache memory attached to the processor. Information processing system characterized by. 2. Before the processing by the processor reaches the predetermined stage, if the state of the connection network satisfies a predetermined condition, the contents of the data block existing in the cache memory are The consistency maintaining process for maintaining consistency is executed.
The information processing system as described. 3. The information processing system according to claim 2, wherein the condition satisfied by the connection network is that the connection network user does not use the connection network. 4. An arbitration unit that arbitrates the use of the connection network by the connection network user is further connected to the connection network, and the arbitration unit detects that the connection network is not used, 4. The information processing system according to claim 3, wherein a condition is determined, and a permission to use the connection network is given to one of the connection network use subjects according to the result. 5. The information processing system according to claim 1, wherein the coherency holding process writes back the updated data block existing in the cache memory to the main memory. 6. The information processing system comprises:
The information processing system according to any one of claims 1 to 4, wherein a consistency model is adopted. 7. Bus means, memory means connected to the bus means, a plurality of bus master means for holding data read from the memory means using the bus means and updating the data, the bus Bus management means for issuing permission to use the bus means to any of the plurality of bus master means when the means is not used by any of the bus master means, the bus master means having reached a predetermined time point. In this case, and when the use permission is issued, the updated data held by using the bus means is written back to the memory means. 8. The bus management means, when no bus master means is using the bus means after the use of the bus means according to the permission of use to the use request of the bus means from the bus master means. 8. The information processing apparatus according to claim 7, wherein the bus master means that has used the bus means immediately before is issued permission to use the bus means. 9. The bus master means that has not obtained permission to use the bus means uses the bus means if the bus master means that has obtained permission to use the bus means does not use the bus means for a predetermined time or more, 9. The stored updated data is written back to the memory means.
The information processing device according to 1. 10. The processor further comprises processor means connected to the bus master means, the bus master means writing back the updated data read from the memory means to the memory means in accordance with a predetermined instruction issued from the processor means. The information processing apparatus according to any one of claims 7 to 9, characterized in that. 11. The bus master unit 1 checks if another bus master unit writes data back to the memory unit and whether the data is duplicated and read from the memory unit to the bus master unit. The information processing apparatus according to any one of claims 7 to 10, wherein the data is invalidated when being read out. 12. An information processing device for duplicatively holding data stored in a memory means by a cache means connected to each of a plurality of processors, wherein the data stored in the cache means is the memory means. Determining means for determining whether the data stored in the memory is read and updated, and the cache means for accessing the memory means from none of the cache means according to the determination result by the determining means. First writing back the data read and updated by any of the means to the memory means,
And write-back means for writing back the data read and updated by the cache means to the memory means when a predetermined time is reached. Processing equipment. 13. A method of controlling an information processing apparatus, wherein data stored in a memory means is redundantly held by a cache means connected to each of a plurality of processors, wherein the data stored in the cache means is: A determination step of determining whether the data stored in the memory means is read and updated, and a case where the memory means is not accessed from any of the cache means according to the determination result of the determination step Writing back the data read and updated by any of the cache means to the memory means,
And a second write-back step of writing back the data read and updated by the cache means to the memory means when a predetermined time is reached. A method for controlling a processing device.