JPH0748659B2 - Phase-locked oscillator - Google Patents
Phase-locked oscillatorInfo
- Publication number
- JPH0748659B2 JPH0748659B2 JP62322935A JP32293587A JPH0748659B2 JP H0748659 B2 JPH0748659 B2 JP H0748659B2 JP 62322935 A JP62322935 A JP 62322935A JP 32293587 A JP32293587 A JP 32293587A JP H0748659 B2 JPH0748659 B2 JP H0748659B2
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- phase
- output
- controlled oscillator
- circuit
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、通信装置等において、主に周波数変換等の目
的で設置される位相同期発振器に関し、特に入力信号と
出力信号の位相関係を一定に保つ位相同期発振器に関す
るものである。Description: TECHNICAL FIELD The present invention relates to a phase-locked oscillator mainly installed for the purpose of frequency conversion in a communication device or the like, and more particularly to a constant phase relationship between an input signal and an output signal. The present invention relates to a phase-locked oscillator kept at.
従来の位相同期発振器の一例を第３図に示し説明する。 An example of a conventional phase locked oscillator will be described with reference to FIG.
第３図に示すように、位相同期発振器は、位相比較回路
10と、電圧制御発振器40とから成っている。As shown in FIG. 3, the phase-locked oscillator has a phase comparison circuit.
It consists of 10 and a voltage controlled oscillator 40.
入力端子100に加えられた入力信号と出力端子200に出力
される出力信号は位相比較回路10に導かれている。位相
比較回路10は両信号の位相を比較し、その位相差に応じ
て、例えば第４図に示す位相比較特性に従った電圧を発
生する。The input signal applied to the input terminal 100 and the output signal output to the output terminal 200 are guided to the phase comparison circuit 10. The phase comparison circuit 10 compares the phases of both signals and generates a voltage according to the phase comparison characteristic shown in FIG. 4, for example, according to the phase difference.
この位相比較回路10に出力電圧は電圧制御発振器40の制
御電圧として加えられている。電圧制御発振器40は、加
えられる制御電圧に応じて発振周波数が変化する発振器
であり、この電圧制御発振器40の出力が出力信号として
出力端子200に送出される。The output voltage is applied to the phase comparison circuit 10 as the control voltage of the voltage controlled oscillator 40. The voltage controlled oscillator 40 is an oscillator whose oscillation frequency changes according to the applied control voltage, and the output of this voltage controlled oscillator 40 is sent to the output terminal 200 as an output signal.
このような従来の位相同期発振器において、電圧制御発
振器40の出力周波数が入力信号の周波数より低下する
と、位相比較回路10に加えられる出力信号の位相は入力
信号位相に比して遅れることになる。このため、位相比
較回路10は出力信号位相の遅れ量に比例してより高い制
御電圧を発生し、電圧制御発振器40に与える。この結
果、電圧制御発振器40の出力周波数は上昇する。同様
に、出力周波数が入力信号より高くなった場合は、入力
信号に対する出力信号の位相が進み、この結果、位相比
較回路10の出力電圧が低下し、電圧制御発振器40の発振
周波数は低下する。従って、電圧制御発振器40の出力周
波数は最終的に常に入力信号の周波数と等しくなり位相
同期した出力信号が得られる。In such a conventional phase-locked oscillator, when the output frequency of the voltage controlled oscillator 40 becomes lower than the frequency of the input signal, the phase of the output signal applied to the phase comparison circuit 10 is delayed compared with the input signal phase. Therefore, the phase comparison circuit 10 generates a higher control voltage in proportion to the delay amount of the output signal phase and supplies it to the voltage controlled oscillator 40. As a result, the output frequency of the voltage controlled oscillator 40 increases. Similarly, when the output frequency becomes higher than the input signal, the phase of the output signal with respect to the input signal advances, and as a result, the output voltage of the phase comparison circuit 10 decreases and the oscillation frequency of the voltage controlled oscillator 40 decreases. Therefore, the output frequency of the voltage-controlled oscillator 40 is always always equal to the frequency of the input signal, and the phase-locked output signal is obtained.
しかしながら、第３図に示した構成によるものにあって
は、使用する電圧制御発振器の個別特性等によって入力
信号と出力信号との位相関係を正確に定めることができ
ないという難点がある。However, the configuration shown in FIG. 3 has a drawback in that the phase relationship between the input signal and the output signal cannot be accurately determined due to the individual characteristics of the voltage controlled oscillator used.
すなわち、まず、上記の説明から明らかなように、従来
の位相同期発振器では、入力信号と出力信号の間に入力
信号周波数と電圧制御発振器40の自走発振周波数の差に
相当する定常位相差が発生している。That is, first, as is apparent from the above description, in the conventional phase-locked oscillator, the steady phase difference corresponding to the difference between the input signal frequency and the free-running oscillation frequency of the voltage controlled oscillator 40 is present between the input signal and the output signal. It has occurred.
従って、上述した従来の位相同期発振器では、電圧制御
発振器40の自走発振周波数が入力信号周波数と異なる場
合は入出力信号間に両信号の周波数差に相当する定常位
相誤差が生じ、制御電圧を変化させて位相同期を確立す
るので電圧制御発振器40の自走発振周波数が変化すると
入出力信号間の位相も変化する。Therefore, in the conventional phase-locked oscillator described above, when the free-running oscillation frequency of the voltage controlled oscillator 40 is different from the input signal frequency, a steady phase error corresponding to the frequency difference between the input and output signals occurs, and the control voltage is changed. Since the phase synchronization is established by changing the phase, the phase between the input and output signals also changes when the free-running oscillation frequency of the voltage controlled oscillator 40 changes.
一方、一般に複数の、すなわち個々の電圧制御発振器の
自走周波数は各々異なり、制御電圧に対する出力周波数
の変化量も各々異なる。さらに、１つの電圧制御発振器
について見ても、その自走周波数は温度変動電源変動お
よび経時変化等により製造後にも変化する。On the other hand, generally, a plurality of, ie, individual, voltage controlled oscillators have different free-running frequencies, and the amount of change in the output frequency with respect to the control voltage also differs. Furthermore, even when looking at one voltage controlled oscillator, its free-running frequency changes after manufacturing due to temperature fluctuations, power supply fluctuations, changes over time, and the like.
この結果、従来の位相同期発振器では、入力信号と出力
信号の位相関係を厳密に定めることができないという欠
点を有していた。As a result, the conventional phase-locked oscillator has a drawback that the phase relationship between the input signal and the output signal cannot be determined exactly.
本発明の目的は、簡単な構成により入力信号と出力信号
の位相を電圧制御発振器の個別特性等によらず一定に保
つ位相同期発振器を提供することにある。An object of the present invention is to provide a phase-locked oscillator that keeps the phases of an input signal and an output signal constant with a simple configuration regardless of individual characteristics of the voltage controlled oscillator.
本発明の位相同期発振器は、 制御電圧に応じて発振周波数が変化する電圧制御発振器
と、 入力信号と前記電圧制御発振器の出力信号の位相を比較
し、両信号の位相差に比例した電圧を発生する第１の位
相比較回路と、 入力信号を1/2周期分移相する移相回路と、 この移相回路の出力信号と前記電圧制御発振器の出力信
号の位相を比較し、両信号の位相差に比例した電圧を発
生する第２の位相比較回路と、 前記第１の位相比較回路の出力電圧と第２の位相比較回
路の出力電圧を加算する電圧加算回路と、 この電圧加算回路の出力信号に含まれる高周波成分を抑
圧し、前記電圧制御発振器に制御電圧を与える低域ろ波
器とを有することを特徴としている。The phase-locked oscillator of the present invention compares the phase of an input signal and the output signal of the voltage-controlled oscillator with a voltage-controlled oscillator whose oscillation frequency changes according to the control voltage, and generates a voltage proportional to the phase difference between the two signals. And a phase shift circuit for shifting the input signal by 1/2 cycle, comparing the phases of the output signal of this phase shift circuit and the output signal of the voltage controlled oscillator, and comparing A second phase comparison circuit that generates a voltage proportional to the phase difference, a voltage addition circuit that adds the output voltage of the first phase comparison circuit and the output voltage of the second phase comparison circuit, and the output of this voltage addition circuit A low-pass filter that suppresses high-frequency components contained in the signal and supplies a control voltage to the voltage-controlled oscillator.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の位相同期発振器の構成を示
すブロック図であり、また、第２図はその位相同期発振
器の位相比較特性の説明に供する説明図であって、具体
的には第２図（ａ），（ｂ）及び（ｃ）は位相同期発振
器内における第１及び第２の２つの位相比較回路の位相
比較特性及びこれら両者を合成した位相比較特性を示し
ている。FIG. 1 is a block diagram showing a configuration of a phase locked oscillator according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram for explaining the phase comparison characteristics of the phase locked oscillator. 2 (a), (b) and (c) show the phase comparison characteristics of the first and second phase comparison circuits in the phase locked oscillator and the phase comparison characteristics obtained by combining both.
なお、第１図の位相同期発振器の各構成部分のうち、第
３図に示した従来の位相同期発振器と同一符号を付した
ものは同等の機能を有している。Among the components of the phase-locked oscillator shown in FIG. 1, those given the same reference numerals as those of the conventional phase-locked oscillator shown in FIG. 3 have the same functions.
第１図に示すように、本発明に従う位相同期発振器は、
位相比較回路10と電圧制御発振器40の他、移相回路50、
位相比較回路11、電圧加算回路20及び低域ろ波器30を備
えている。As shown in FIG. 1, the phase-locked oscillator according to the present invention is
In addition to the phase comparison circuit 10 and the voltage controlled oscillator 40, a phase shift circuit 50,
A phase comparison circuit 11, a voltage addition circuit 20, and a low-pass filter 30 are provided.
入力信号が供給される入力端子100には、位相比較回路1
0の一方の入力端が接続されると共に、移相回路50が接
続されており、また移相回路50には位相比較回路11の一
方の入力端が接続されている。各位相比較回路10,11の
他方の入力端には、電圧制御発振器40から出力端子200
へ与えられる出力信号がそれぞれ供給されるようになっ
ており、また、各位相比較回路10,11の出力が電圧加算
器20に与えられるようになっている。そして、この電圧
加算回路20と電圧制御発振器40との間に低域ろ波器が挿
入されている。The phase comparison circuit 1 is connected to the input terminal 100 to which the input signal is supplied.
One input terminal of 0 is connected and the phase shift circuit 50 is also connected, and one input terminal of the phase comparison circuit 11 is connected to the phase shift circuit 50. The other input terminal of each phase comparison circuit 10, 11 is connected to the output terminal 200 from the voltage controlled oscillator 40.
To the voltage adder 20. The output signals of the phase comparators 10 and 11 are supplied to the voltage adder 20. A low pass filter is inserted between the voltage adder circuit 20 and the voltage controlled oscillator 40.
位相比較回路10は、第１の位相比較回路であり、入力端
子100より与えられる入力信号と出力端子200に出力され
る出力信号、すなわち電圧制御発振器40の出力信号の位
相を比較し、両者の位相差に応じて第２図（ａ）の特性
に従って電圧を発生する。The phase comparison circuit 10 is a first phase comparison circuit, compares the phases of the input signal given from the input terminal 100 and the output signal outputted to the output terminal 200, that is, the output signal of the voltage controlled oscillator 40, and A voltage is generated according to the characteristic of FIG. 2 (a) according to the phase difference.
移相回路50は、入力端子100に与えられた信号を1/2周期
分、即ち、πラジアンだけ移相する機能を有し、特に入
力信号のデューティ比が50％であればこれは簡単なイン
バータ回路により実現される。The phase shift circuit 50 has a function of shifting the signal applied to the input terminal 100 by 1/2 cycle, that is, by π radians. In particular, if the duty ratio of the input signal is 50%, this is simple. It is realized by an inverter circuit.
位相比較回路11は、第２の位相比較回路であって、これ
は前記の移相回路50の出力信号と出力端子200に出力さ
れる信号、すなわち電圧制御発振器40の出力信号の位相
を比較し、両者の位相差に応じて、第２図（ｂ）に示す
位相比較特性に従った電圧を発生する。The phase comparison circuit 11 is a second phase comparison circuit, which compares the phases of the output signal of the phase shift circuit 50 and the signal output to the output terminal 200, that is, the output signal of the voltage controlled oscillator 40. , According to the phase difference between the two, a voltage according to the phase comparison characteristic shown in FIG. 2B is generated.
電圧加算回路20は、前述の第１の位相比較回路10の出力
電圧と第２の位相比較回路11の出力電圧を加算する。こ
の結果、この電圧加算回路20の出力は入力信号と出力信
号の位相差に応じて第２図（ｃ）に示す如き特性に従っ
て電圧を発生する。The voltage addition circuit 20 adds the output voltage of the first phase comparison circuit 10 and the output voltage of the second phase comparison circuit 11 described above. As a result, the output of the voltage adder circuit 20 generates a voltage according to the characteristic shown in FIG. 2C according to the phase difference between the input signal and the output signal.
ここに、第２図（ｃ）に示す特性は、第２図（ａ）及び
第２図（ｂ）の両者を合成したものとなっており、電圧
加算回路20はこれに従って電圧を発生する。The characteristic shown in FIG. 2 (c) is a combination of both FIG. 2 (a) and FIG. 2 (b), and the voltage adding circuit 20 generates a voltage accordingly.
低域ろ波器30は、電圧加算回路20の出力信号に含まれる
不要な高周波成分を抑圧する。電圧制御発振器40は、低
域ろ波器からの制御電圧がΔＶだけ変化した場合に、そ
の出力周波数がΔｆだけ変化するものとする。The low-pass filter 30 suppresses unnecessary high-frequency components contained in the output signal of the voltage adding circuit 20. It is assumed that the voltage controlled oscillator 40 changes its output frequency by Δf when the control voltage from the low pass filter changes by ΔV.
このように、第１図の位相同期発振器は、制御電圧に応
じて発振周波数が変化する電圧制御発振器40と、入力信
号と電圧制御発振器40の出力信号の位相を比較し、両信
号の位相差に比例した電圧を発生する第１の位相比較回
路10と、入力信号を1/2周期分だけ移相する移相回路50
と、この移相回路50の出力信号と電圧制御発振器40の出
力信号の位相を比較し、両信号の位相差に比例した電圧
を発生する第２の位相比較回路11と、第１の位相比較回
路10の出力電圧と第２の位相比較回路11の出力電圧を加
算する電圧加算回路20と、この電圧加算回路20の出力信
号に含まれる不要な高周波成分を抑圧し、電圧制御発振
器40に制御電圧を与える低域ろ波器30を有している。As described above, the phase-locked oscillator of FIG. 1 compares the phases of the input signal and the output signal of the voltage-controlled oscillator 40 with the voltage-controlled oscillator 40 whose oscillation frequency changes according to the control voltage, and determines the phase difference between the two signals. The first phase comparison circuit 10 that generates a voltage proportional to the phase shift circuit 50 that shifts the phase of the input signal by 1/2 cycle.
And a second phase comparison circuit 11 that compares the phases of the output signal of the phase shift circuit 50 and the output signal of the voltage controlled oscillator 40 and generates a voltage proportional to the phase difference between the two signals, and the first phase comparison circuit. A voltage adder circuit 20 that adds the output voltage of the circuit 10 and the output voltage of the second phase comparison circuit 11, and an unnecessary high frequency component included in the output signal of the voltage adder circuit 20 is suppressed and controlled by the voltage controlled oscillator 40. It has a low-pass filter 30 for applying a voltage.
以上の構成を有する位相同期発振器では、既述した如
く、入出力信号の位相差に対する制御電圧特性が第２図
（ｃ）に示すように２つの変曲点P1，P2を有するＳ字状
となる。In the phase-locked oscillator having the above structure, as described above, the control voltage characteristic with respect to the phase difference between the input and output signals has an S-shape having two inflection points P 1 and P 2 as shown in FIG. 2 (c). Become a state.
いま、電圧制御発振器40の出力周波数が入力周波数に比
しΔｆだけ低い場合を考える。この時、電圧制御発振器
40の出力周波数と入力周波数と等しくするためには制御
電圧をΔＶだけ高める必要がある。Now, consider a case where the output frequency of the voltage controlled oscillator 40 is lower than the input frequency by Δf. At this time, the voltage controlled oscillator
In order to make the output frequency of 40 equal to the input frequency, it is necessary to raise the control voltage by ΔV.
しかして、本発明に従う位相同期発振器では、制御電圧
特性が第２図（ｃ）に示したような特性を呈するものと
なっているので、従来のものと異なり、入力信号に対す
る出力信号の位相がわずかでも遅れれば、制御電圧はP1
以上となる。ここで、ΔＶとP1間に、 P1＞ΔＶ …（１） なる関係が成立するよう、２つの位相比較回路10,11お
よび電圧加算回路20を構成すれば、Δｆの周波数低下に
対して同期に要する制御電圧（ΔＶ）以上の制御電圧、
すなわちP1（P1＞ΔＶ）なる電圧が電圧制御発振器40に
加えられる。In the phase-locked oscillator according to the present invention, the control voltage characteristic exhibits the characteristic as shown in FIG. 2 (c), so that the phase of the output signal with respect to the input signal is different from the conventional one. With a slight delay, the control voltage is P 1
That is all. Here, if the two phase comparison circuits 10 and 11 and the voltage addition circuit 20 are configured so that the relationship P 1 > ΔV (1) holds between ΔV and P 1 , it is possible to reduce the frequency of Δf. A control voltage equal to or higher than the control voltage (ΔV) required for synchronization,
That is, a voltage P 1 (P 1 > ΔV) is applied to the voltage controlled oscillator 40.
この結果、電圧制御発振器40の出力周波数は入力周波数
以上となり、出力信号位相は入力信号に対して進むこと
になる。このようにして出力信号の位相がわずかでも入
力信号よりも進み位相となると、前述と同様にして、今
度は制御電圧はP2以下となり、電圧制御発振器40の出力
周波数を低下させ、出力信号位相を遅らせる。この結
果、出力信号位相が入力信号に比して遅れれば、再び前
述と同様にして電圧加算回路20からP1なる電圧が出力さ
れる。このように、この位相同期発振器では、電圧加算
回路20からP1またはP2の２つの電圧が交互に出力される
ことになる。As a result, the output frequency of the voltage controlled oscillator 40 becomes higher than the input frequency, and the output signal phase leads the input signal. In this way, even if the phase of the output signal becomes even more advanced than the input signal, the control voltage will be P 2 or less this time, and the output frequency of the voltage controlled oscillator 40 will be lowered, and the output signal phase Delay. As a result, if the output signal phase lags behind the input signal, the voltage addition circuit 20 outputs the voltage P 1 again in the same manner as described above. Thus, in this phase-locked oscillator, the voltage adder circuit 20 alternately outputs two voltages P 1 and P 2 .
ここで、P1およびP2を電圧制御発振器40の安定度によっ
て生じる周波数変動を補正するのに必要な制御電圧以上
とすれば、上記の説明から明らかのように、出力信号の
位相は常に入力信号位相と等しくなり、定常位相誤差を
生じない。なお、前述のように電圧加算回路20の出力電
圧は通常P1またはP2のいずれかであるが、電圧制御発振
器40に対しては低域ろ波器30を介して加えられるため平
滑化されており、これにより不要なジッタ等は十分抑圧
することができる。Here, if P 1 and P 2 are equal to or higher than the control voltage necessary to correct the frequency fluctuation caused by the stability of the voltage controlled oscillator 40, the phase of the output signal is always input as is apparent from the above description. It becomes equal to the signal phase, and steady phase error does not occur. As described above, the output voltage of the voltage adding circuit 20 is normally either P 1 or P 2 , but is smoothed because it is applied to the voltage controlled oscillator 40 via the low-pass filter 30. As a result, unnecessary jitter and the like can be sufficiently suppressed.
以上説明したように本発明によれば等価的に位相比較範
囲の中心部付近のループゲインを無限大とする構成とす
ることにより、実用上入出力信号間の定常位相誤差が発
生しない。従って本発明の位相同期発振器では入力信号
に対する出力信号の位相を正確に定めることができる効
果がある。さらに本発明によれば、温度変動、電源変
動、経時変化等に対しても出力信号位相が変化しない位
相同期発振器が実現できる。As described above, according to the present invention, the loop gain in the vicinity of the center of the phase comparison range is equivalently set to infinity, so that a steady phase error between input and output signals does not practically occur. Therefore, the phase-locked oscillator of the present invention has the effect of being able to accurately determine the phase of the output signal with respect to the input signal. Further, according to the present invention, it is possible to realize a phase-locked oscillator in which the output signal phase does not change with respect to temperature fluctuations, power supply fluctuations, changes over time, and the like.
第１図は本発明の一実施例の位相同期発振器の構成を示
すブロック図、 第２図は第１図の位相同期発振器内の２つの位相比較回
路の位相比較特性及び両者を合成した位相比較特性を示
す特性図、 第３図は従来の位相同期発振器の構成を示すブロック
図、 第４図は第１図中の位相比較回路の位相比較特性図であ
る。 10,11…位相比較回路 20…電圧加算回路 30…低域ろ波器 40…電圧制御発振器 50…移相回路 100…入力端子 200…出力端子FIG. 1 is a block diagram showing a configuration of a phase locked oscillator according to an embodiment of the present invention, and FIG. 2 is a phase comparison characteristic of two phase comparison circuits in the phase locked oscillator of FIG. FIG. 3 is a characteristic diagram showing characteristics, FIG. 3 is a block diagram showing a configuration of a conventional phase locked oscillator, and FIG. 4 is a phase comparison characteristic diagram of the phase comparison circuit in FIG. 10, 11 ... Phase comparison circuit 20 ... Voltage addition circuit 30 ... Low-pass filter 40 ... Voltage controlled oscillator 50 ... Phase shift circuit 100 ... Input terminal 200 ... Output terminal
Claims (1)
圧制御発振器と、 入力信号と前記電圧制御発振器の出力信号の位相を比較
し、両信号の位相差に比例した電圧を発生する第１の位
相比較回路と、 入力信号を1/2周期分移相する移相回路と、 この移相回路の出力信号と前記電圧制御発振器の出力信
号の位相を比較し、両信号の位相差に比例した電圧を発
生する第２の位相比較回路と、 前記第１の位相比較回路の出力電圧と第２の位相比較回
路の出力電圧を加算する電圧加算回路と、 この電圧加算回路の出力信号に含まれる高周波成分を抑
圧し、前記電圧制御発振器に制御電圧を与える低域ろ波
器とを有することを特徴とする位相同期発振器。1. A voltage-controlled oscillator whose oscillation frequency changes according to a control voltage, and a phase of an input signal and an output signal of the voltage-controlled oscillator are compared to generate a voltage proportional to a phase difference between the two signals. The phase comparison circuit of, and a phase shift circuit that shifts the input signal by 1/2 cycle, compares the output signal of this phase shift circuit and the output signal of the voltage controlled oscillator, and is proportional to the phase difference between both signals. A second phase comparison circuit that generates the generated voltage, a voltage addition circuit that adds the output voltage of the first phase comparison circuit and the output voltage of the second phase comparison circuit, and an output signal of the voltage addition circuit. A low-pass filter that suppresses a high-frequency component that is generated and applies a control voltage to the voltage-controlled oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62322935A JPH0748659B2 (en) | 1987-12-22 | 1987-12-22 | Phase-locked oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62322935A JPH0748659B2 (en) | 1987-12-22 | 1987-12-22 | Phase-locked oscillator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01165226A JPH01165226A (en) | 1989-06-29 |
| JPH0748659B2 true JPH0748659B2 (en) | 1995-05-24 |
Family
ID=18149274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62322935A Expired - Lifetime JPH0748659B2 (en) | 1987-12-22 | 1987-12-22 | Phase-locked oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0748659B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3824172B2 (en) * | 1995-08-14 | 2006-09-20 | 株式会社ルネサステクノロジ | PLL circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62165436A (en) * | 1986-01-17 | 1987-07-22 | Nec Corp | Phase comparator |
-
1987
- 1987-12-22 JP JP62322935A patent/JPH0748659B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01165226A (en) | 1989-06-29 |
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