JPH0748201B2 - Digital signal processing system - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital signal processing system for performing arithmetic processing on a digital signal sequence.

[Prior Art] FIG. 5 shows, for example, the conventional digital signal processor DSSP1 (Digital Speech Si
FIG. 6 is a block diagram showing a configuration of an arithmetic unit of the gnal Processor 1). In FIG. 5, 1 is a dual port internal data memory capable of reading and writing two data at the same time, and 2 is an address of read or write data. A data address generator for calculation, 3 is a data bus used for internal transfer of data associated with operation, 4 and 5 are selectors, 6 is a register for holding data to be operated, 7 is a register for holding operation data, and 8 is multiplication. , 9 is a register for holding the output of the multiplier 8, 10 and 11 are selectors, 12 is an arithmetic and logic operation unit, 13 is a selector, 14 is an accumulator for holding the output of the operation unit 12 and used for accumulation, 15 Is an external address register, 16 is an external data register, and 17 is an external memory.

Next, the operation will be described.

The operation when performing 3-input 1-output calculation is shown below. However, each unit such as the arithmetic unit 12, the multiplier 8, the address generator 2, the internal data memory 1, the selectors 4,5, 10, 11, and 13 is controlled on the basis of the instruction micro mode. Addition and subtraction,
Collecting two-input arithmetic operations for finding maximum and minimum values,
Let a _i b _i and the multiplication be a _i × b _i . Here, the above-mentioned arithmetic operation and multiplication are combined to define a 3-input 1-output operation by the following equation.

X _i = (a _i b _i ) × c _i − (1) Y _i = (a _i × b _i ) c _i − (2) (i = 1 to N) where a _i , b _i , c _i are It is assumed that they are stored in the internal data memory 1 as independent data series. For example,
FIG. 6 shows a processing flow when the 3-input operation of the expression (1) is executed by the DSSP1. First, the operation in parentheses, a _i b _i, is _converted into two data series A {a _i | i = 1 to N}, B {b _i | i = 1 to N}.
And the data sequence of (a _i b _i ) to the external memory 17
Store a part of it. Next, the data series C {c _i | i = 1 to N}
And the data series of the operation result of the above a _i b _i are read at the same time and the multiplication which is the second operation is performed and the output data series of (a _i b _i ) × c _i is stored in the internal data memory 1. Actual
In the DSSP1, in FIG. 7, the data address generation unit 2
After setting the data address value to the start address of each of the two data series A and B to set the simple increment mode, the two data series A and B are sequentially set.
The data of 2 is read from 2P-RAM1 to register 6 and register 7. In the selectors 10 and 11, the registers 6 and 7 are selected, the arithmetic logic unit 12 performs arithmetic operation (a _i b _i ), and the selector 13 selects the arithmetic logic unit.
The 12 side is selected and stored in one of the accumulators 14 and then stored in the external memory 17 via the data bus 3. At this time, since the external memory address is linked to one of the internal data memory addresses in the address generator 2, the simple increment mode is set. Next, again in the data address generation unit 2, the data address value is set so as to be the start address of the data series C and the data series of (a _i b _i ), and the data of the internal data memory 1 to c _i is registered in the register 6 Read out, meanwhile, external memory 17
The data from (a _i b _i ) are read into the register 7 by selecting the data bus 3 side in the selector 5. However, in order to match the read timings of the data series C and the data series of (a _i b _i ), it is necessary to read two instructions from the external memory 17 in advance. The read two data are multiplied by the multiplier 8, the result is stored in the register P9, passes through the arithmetic and logic unit 12 in the next cycle, and is stored in any one of the accumulators 14,
It is stored in the arithmetic logic unit 12 via the data bus 3.

Since the above operation is performed in parallel by pipeline processing, it takes (N + 3) machine cycles in the case of arithmetic operation from reading of N data series to storage of the processing result in the external memory 17. Next, after performing an empty read from the external memory 17 twice (2 machine cycles) (timing adjustment), N data sequences are multiplied and stored in the internal data memory 1 (N + 3) machine cycles, other addresses. Since two instructions are required for the initial setting,
The total cycle is (2N + 10) cycles. Similarly, the calculation of equation (2) requires (2N + 10) cycles.
As described above, it can be seen that it takes about 2N machine cycles (when N is sufficiently large) to execute a 3-input 1-output operation on N data series by a processor such as DSSP1 which can perform a maximum 2-input operation.

A case of accumulating the 3-input 1-output calculation result will be described below.

In the case of the expression (3), the multiplication result (register P9) of (a _i b _i ) and c _i and the accumulated value up to the middle are used as the input of the arithmetic logic operation unit 12, and the addition result is again the same accumulator. The number of processing cycles is (2N + 1
0) Invariant with cycles. However, in the case of equation (4),
Since the data sequence of (a _i × b _i ) c _i stored in the shared internal data memory 1 is read again and accumulated by the sequential arithmetic logic unit 12, N cycles are newly required, and the total number of cycles is ( 3N + 10).

[Problems to be Solved by the Invention]

Since the conventional digital signal processing system is configured as described above, when performing a 3-input 1-output calculation for three independent data series, the 3-input 1-output calculation is divided into 2 stages and a 2-input 1-output calculation is performed. In addition to performing the output operation twice, there is a problem that the operation processing time becomes long because of processing such as address control and transfer to the memory.

The present invention has been made to solve the above-mentioned problems, and it is possible to perform three-input one-output operation at a time and to omit processing such as address control for storing an intermediate result and transfer to a memory. It is an object of the present invention to obtain a digital signal processing system capable of performing 3-input 1-output calculation at high speed.

[Means for Solving the Problems]

According to the digital signal processing method of the present invention, the first, second and third data storage means (first and second data memory) each store three data sequences each having N elements.
23, 24, a temporary vector register group 29), a calculation means (calculator 36), a multiplication means (multiplier 38), and the third
And a delay means (latch 31) for delaying the output data from the data storage means for a predetermined time and outputting it to the arithmetic means or the multiplying means. The instruction for performing the data read processing from the data storage means of No. 3 and the selection processing of the input data to the arithmetic means and the multiplication means is included, and the first, second, third The data from the third data storage means at the same time, and the data from the third data storage means is held in the delay means.
Each data from the second data storage means is selected to obtain the first processing result by the arithmetic means or multiplication means, and then the first processing result and the data held in the delay means are selected. The three-input one-output calculation is performed by obtaining the second processing result by the calculation means or the multiplication means.

[Operation] The following processing is performed by one instruction of the microprogram.

First, data is read out simultaneously from the first to third data storage means. At this time, the data from the third data storage means is held in the delay means, and each data from the first and second data storage means is selected and output to the arithmetic means or the multiplication means. 1 Obtain the processing result. Next, the first processing result and the data held in the delay means are selected and output to the arithmetic means or the multiplying means to obtain the second processing result which is the result of the 3-input 1-output operation.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 20 and 21 are first and second address generators that independently generate read data addresses, 22 is a third address generator that generates write data write destination addresses, and 23 and 24 are first and second address generators, respectively. , The second address generator 20,
A data memory that reads data according to 21 and writes according to the address information of the third address generator, 2
5,26 are independent first and second data buses for transferring read data from the first and second data memories 23 and 24, 2
Reference numeral 7 denotes a register that holds data transferred from the first and second data buses 25 and 26, and 29 that can hold a plurality of data as a register group including a plurality of readable and writable registers. Temporary vector register group, 30
Is an address pointer that controls the address of the temporary vector register group 29, 31 is a latch, 32, 33, 34, 3
5 is a selector that selects one of the two input data, 36 is an arithmetic unit that performs arithmetic logic operation on the two data, 37 is a register that holds the output of the arithmetic unit 36, and 38 is two data Is a register for holding the output of the multiplier 38, 40 is an output selector for selecting and outputting either the output of the arithmetic unit 36 or the output of the multiplier 38, and 41 is an accumulator. An adder for arithmetic operation, 42 is an accumulator as a plurality of accumulated value holding registers for holding the output of the adder 41, and 43 is write data to the first and second data memories 23 and 24 or input / output with external circuits. A third data bus for transferring data, 44 is an external interface circuit for inputting / outputting data to / from an external circuit, and 101 and 111 are signal lines to the third data bus 25.

Next, the operation will be described.

In FIG. 1, a data series A having N elements A = {a _i
| i = 1 to N}, B = {b _i | i = 1 to N}, C = {c _i | i = 1
˜N} are stored in advance in the first data memory 23, the second data memory 24, and the temporary vector register group 29 as first to third data, respectively. The operation when performing 3-input 1-output calculation under the above conditions is shown below. At the same time, the calculation processing flow will be described with reference to FIG.

First, first, the first address of the input data 3 series as the first to third data and the output result storage destination are respectively
Initialization is performed by the second address generators 20, 21, the address pointer 30, and the third address generator 22. After that, each address generator performs a simple increment operation.

The first data memory 23 corresponds to the first address generator 20, the second data memory 24 corresponds to the second address generator 21, respectively, and the temporary vector register group 29 corresponds to the address pointer 30. 2 Data memory 23, 24
The temporary vector register group 29 reads data based on the addresses indicated by the first and second address generators 20 and 21 and the address pointer 30, respectively. However, the first
Since it is possible to input to the second data buses 25 and 26 from the first and second data memories 23 and 24, respectively, there are two outputs from the first and second data memories 23 and 24 to the specific data bus. Only one of them is valid and the other one is controlled to be in a high impedance state. For example, register 27
When inputting the data a _i of
_i is output, and the second data memory 24 outputs the first data bus 2
The signal line 111 for output to 5 is set to a high impedance state. The same applies to the second data bus 26. As described above, the first and second data a _i and b _i are set in the registers 27 and 28.

The following two equations are defined as a three-input operation and the processing method thereof will be shown below.

X _i = (a _i b _i ) × c _i − (1) Y _i = (a _i × b _i ) c _i − (2) where (a _i b _i ) is for two input data a _i , b _i It represents an arithmetic and logical operation for obtaining addition, subtraction, maximum value, minimum value, etc., and (a _i × b _i ) represents multiplication.

First, an explanatory diagram of the processing timing of the equation (1) will be described with reference to FIG. First, the selector 32 selects the register 27 side and the selector 33 selects the register 28 side. The two selected first and second data is a (a _i and b _i) performs computed by the computing unit 36 (a _i b _i), and stores the result to register 37. On the other hand, the third data c _i of the temporary vector register group is delayed by one step by the latch 31, and in the next step, the selector 34 selects the register 37 side and the selector 35 selects the latch 31 side. The output data (a _i b _i ) and the third data c _i are multiplied by the multiplier 38, and the multiplication result (a _i b _i ) × c _i is stored in the register 39.
This value is output from register 39 in the next step. The fifth selector 40 selects the register 39 side, and outputs the output data (a _i b _i ) × c _i based on the address indicated by the third address generator 22 via the third data bus 43. Transfer to data memory 23, 24. In addition, the data memory by the initial setting of the address of the address generator and the address pointer, the data read processing from the register group, the data bus, each selector, the arithmetic unit, the multiplier, the adder for accumulation, etc.
It is controlled by the instructions of a microprogram incorporated in the digital signal processor.

In the digital signal processor, data read, operation execution, and data write are continuously executed by pipeline processing, so that operation control of each unit can be performed in parallel. Therefore, when the above-described 3-input 1-output arithmetic operation is performed on the data series having N elements, it takes (N + 4) cycles from reading the first data to writing the final data processing result in the memory.

Next, an explanatory diagram of the processing timing of the equation (2) will be described with reference to FIG. The data set of 3 input data is the same as the case of the above formula (1). When executing the equation (2), the selector 34 selects the register 27 side and the selector 35 selects the register 28, the multiplier 38 executes (a _i × b _i ), and the result is set in the register 39. Selector 32 in next step
The latch 31 side is selected by the selector 33 and the register 39 side is selected by the selector 33. The arithmetic unit 36 executes (a _i × b _i ) c _i and sets it in the register 37. The data in register 37 is
By selecting the register 37 side with the selector 40, the data is written in the first and second data memories 23 and 24.

That is, in the case of the formula 2, as in the case of the formula (1), (N + 4) cycles are required.

From the above, when the same arithmetic processing is executed as described in the operation and operation of the conventional technique, the three-input one-output arithmetic processing speed is (2N + 10) / (N + 8) times, or N times that of the DSPP1.
Is large, the processing speed is about double.

In addition, when obtaining the accumulation of the above three-input one-output calculation, the accumulation result or the initial value up to the middle is stored in the accumulator 42 as the accumulated value holding register, and the accumulated value and the three-input one-output calculation result are sequentially stored. Is added by the adder 41 and stored again in the accumulator 42 as a cumulative value holding register. Therefore, there is no increase in the processing cycle due to the accumulation.

A first data pair is composed of the first data a _i of the first data bus 25 and the second data b _i of the second data bus 26, and is read from the temporary vector register group 29. Output data of the third data c _i and the multiplier 38 (a _i × b _i ).
Form the second data pair, and the third data c _i and the output data (a _i b _i ) of the arithmetic logic unit 36 form the third data pair.

〔The invention's effect〕

As described above, according to the present invention, the first to third data are simultaneously read out, and the arithmetic logic operation and the multiplication are selectively performed by the program.
The combination order of input 1 output operation is variable, and high speed 3
There is an effect that the operation of one input and one output can be executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing unit for digitally processed signals according to an embodiment of the present invention, and FIG. 2 is a diagram showing a flow chart of a 3-input 1-output calculation processing according to an embodiment of the present invention. 3 and 4 are explanatory diagrams of arithmetic processing timing according to an embodiment of the present invention, and FIG. 5 is a diagram showing a configuration of an arithmetic processing unit of DSSP1 which is an example of a conventional digital signal processor, and FIG. Is 3 in DSSP1
FIGS. 7 (a) and 7 (b) are views showing a flow chart of the input / output calculation processing, and FIGS. 20 ... First address generator, 21 ... Second address generator, 22 ... Third address generator, 23,24 ... First and second data memory, 25,26 ... First and second Data bus, 27,28 ...
… Registers, 29 …… Temporary vector registers, 30
...... Address pointer, 31 …… Latch, 32,33,34,35,40
...... Selector, 36 …… Calculator, 37,39 …… Register, 38
…… Multiplier, 41 …… Adder, 42 …… Accumulator, 43
...... Third data bus, 44 …… External interface circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A digital signal processing method in a digital signal processor for executing fetching, decoding, reading of data, operation and writing of an operation result by a built-in microprogram, in a digital signal processing system having N elements. The output data from the first, second and third data storage means for storing one data series each, one for the second data storage means, the calculation means, the multiplication means, and the third data storage means are delayed for a predetermined time, and The built-in microprogram includes at least data read processing from the first, second, and third data storage means, and a delay means for outputting to the calculation means or the multiplication means. And a command for selecting input data to the multiplying means are included. In accordance with the instruction of the system, the data is read from the first, second and third data storage means at the same time, the data from the third data storage means is held in the delay means, and the first, second and third data storage means are held. Selecting each data from the data storing means to obtain the first processing result by the calculating means or the multiplying means, and then selecting the first processing result and the data held in the delay means to select the above. A digital signal processing system characterized in that a three-input one-output calculation is performed by obtaining a second processing result by the calculation means or the multiplication means.