JPS6220590B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pipeline fast Fourier transform device that performs Fourier transform at high speed by pipeline calculation.

To perform the Fourier transform digitally,
A discrete Fourier transform is performed on discrete samples in both the time domain and the frequency domain, and only on a finite number of samples. Input time series data, i.e. discrete samples in the time domain, x
(p), spectral components, that is, discrete samples in the frequency domain, X(k), and the number of sample points is N=
2 ^m , therefore p is 0 to N-1, similarly k is an integer from 0 to N-1, and the twiddle factor is W=e ^-j 〓〓
, and W ^p corresponds to each point on the unit circle on the complex plane (one point of the Nth root of 1). In this case, the discrete Fourier transform can be expressed by the following equation (1).

As an algorithm for calculating this discrete Fourier transform at high speed, there is a method of performing the calculation by repeating the basic calculation of so-called butterfly calculation. For example, the Cooley-Chukey algorithm is as follows. That is, if the sample input signal is divided into even and odd numbers, equation (1) can be written as the following equation (2).

This means that the discrete Fourier transform made up of samples at N points is divided into two discrete Fourier transforms A and B made up of N/2 points. Furthermore, within the range of k between N/2 and N-1, W ^k =-W ^k- . Therefore, within this range of k, A−W ^k− 〓×
It is generally calculated as B. That is, fast Fourier transform can be performed by recursively repeating the operations of A+W ^k B and A-W ^k B within the range of k from 0 to N/2-1. In this calculation, as shown in Figure 1, for inputs A, B, and twiddle factor W ^k , the output of A+W ^k B is A', and the output of A-W ^k B is
B′, and this is called a butterfly operation. These A, B, A′,
B' and W have a real part and an imaginary part, so this butterfly operation calculates the following equation.

For example, the input time series samples are 16 from x ₀ to x ₁₅ .
In the case of , as shown in Figure 2, the first stage performs butterfly calculations on two inputs shifted by 8 points, the second stage performs butterfly calculations on the results of the calculations, and so on. In the case of a lever, since 16 = 2 ⁴ , the discrete frequency spectrum is obtained by butterfly operation in the fourth stage.
X ₀ to X ₁₅ are obtained.

Since the fast Fourier transform is thus obtained by repeating butterfly calculations, pipeline calculations have traditionally been used. However, since the data combinations and twiddle factors of the calculations performed in each calculation stage are different for each stage, the overall circuit configuration is complex, and many delay elements such as shift registers are used to determine the data combinations. was becoming a major issue. On the other hand, when a calculation is performed for one stage under software control, the result is stored in memory and read out to perform the butterfly calculation for the next stage.
In this case, it is necessary to generate a storage address for the memory using a special address generation circuit that differs from stage to stage, and in this case, the calculation speed is not very high because the calculation is performed for each stage.

An object of the present invention is to provide a pipeline fast Fourier transform device that has a simple circuit configuration and can perform calculations at high speed.

According to the present invention, first and second memories for input/output, a third memory for storing twiddle factors, and an arithmetic unit for performing butterfly computation using a pipeline method are provided corresponding to each arithmetic stage. . In addition, two buffer memories are provided to output the final calculation results, and the calculations at each stage are controlled by a common control unit.Furthermore, an address register unit is provided in common to generate addresses for accessing the memories at each stage. . The result of the butterfly operation performed in the pipeline method at each stage is written to the input/output memory of the next stage that is not being read at that time, that is, the writing side, and the pipeline operation for all stages as a whole is performed. . Furthermore, as mentioned earlier, the address for accessing each memory is generated from a common address register unit, and the write address line for storing the operation result and the write address of the i-th stage memory are generated from a common address register unit. The lines are connected with only the lower i bits shifted cyclically by one bit in the upper direction.

FIG. 3 shows an example of a fast Fourier transform device according to the present invention. In this example, N pieces (N=2 ^m ) of input time series samples x ₀ to x _-1 are input from a terminal 11 and subjected to Fourier transform. If the number of samples is N=2 ^m , the calculation stage is S ₁
m stages S n to S _n are provided. Each calculation stage is provided with two memories, first and second memories M _i1 and M _i2 for input/output. Here, i is an integer from 1 to m. Also, the third twiddle factor
A memory M _i0 is provided, and each arithmetic unit AU _i is provided.

All memories of each arithmetic stage are addressed by addresses from a common address register unit 12. That is, the read address line 13
are the first and second input/output memories M _i1 of each stage,
The write address line 14 is connected to the first and second input/output memories _{M i1 and} M _i2 of each stage, respectively. In each of these stages, one of the first and second memories M _i1 and M _i2 for input/output is in a state of being read, and at that time, it is accessed by the address on the read address line 13, and the other is used for writing. , write address line 14
Accessed at the above address. In addition, at each stage, first and second memories M _i1 ,
Each data read from M _i2 and the third memory M _i0 for twiddle factors is supplied to the corresponding arithmetic unit AU _i . The results computed by each arithmetic unit AU _i are supplied to the first and second input/output memories M _{i +} 1 , ₁ , M _i+1 , ₂ of the next stage S i+1 and used for reading at that time. Address line 14 for writing to the memory that is not
It will be written as specified by the address above.

Input/output memory M ₁₁ for the first stage S ₁ ,
Data to be Fourier transformed from the input terminal 11 is written to _M12 . Further, the calculation result of the calculation unit AU _n of the final stage S _n is written into one of the output buffer memories M ₀₁ and M ₀₂ . These output memories M ₀₁ and M ₀₂ also have readout lines 13
and write line 14, respectively. These buffer memory M ₀₁ ,
The data read from M ₀₂ is sent out from the output terminal 15.

The entire device is controlled by a control unit 16. Address register unit 12 is therefore also controlled by this control unit 16. The address register unit 12 generates a new read address from a terminal 17 and a new write address from a terminal 18 by calculating the microinstruction from the control unit 16 with a counter, and transfers these to the read address line 13. ,
It is applied to the write address line 14. Each arithmetic unit AU _i performs this butterfly computation in a pipelined manner, and the computation results are supplied to the next stage as described above. Therefore, stages _S1 to _Sn are sequentially connected in cascade. Moreover, they operate in parallel, that is, they operate in a pipeline as a whole.

In other words, for example _, in the case of N ₌ 16, as shown _{in FIG} . In the calculation period _T2 , the data written in the first input/output memory _M11 is read out, and at the same time the twiddle factor stored in the third memory _M10 is read out, and the calculation unit AU uses these read data to read out the twiddle factor stored in the third memory M10. In _{step 1} , a butterfly operation is performed, that is, a butterfly operation as described for the first stage in Fig. 2 is performed, and the results of this operation are successively stored in the second memory for input/output of the second stage.
Written in M ₂₁ . At the same time, the next time series data is taken in from the input terminal 11 to the second input/output memory _M12 .

In the next calculation interval _T3 , the second stage memory _M12 and the third memory _M20 for twiddle factors are read out simultaneously, and the butterfly calculation in the second stage shown in FIG _{. 2} is performed in the calculation unit AU2. The result is written to the first input/output memory _M31 in the third stage. Also, at this time, the new data is stored in the first memory for input/output of the first stage.
Written in M ₁₁ . In the same way, the calculation results are sequentially sent to the next calculation stage, and the calculation results from the previous stage are input and calculated at the same time.
For the data first input to the calculation stage _S1 at _T1 , a butterfly calculation is performed in the fourth stage in the calculation interval _T5 , and this is written to the output buffer _M01 .

Since the address register unit 12 is commonly used, in this example, when the input data of each stage is sequentially read out from the top in the figure in FIG. 2, the calculation result of each stage is transferred to the memory of the next stage. When writing to , there are cases where the data is written to the same address location as the read address at the time, but there are cases where it is necessary to convert the write address. The conversion is different at each stage, and this conversion is performed as follows. In the i-th stage, the write address line 14 and the i-th bit are sequentially shifted to the upper bit by one bit, so that the i-th (most significant) bit becomes the least significant bit. Connect to the write address line of the stage's input/output memory.

That is, as shown in FIG. 5, the calculation results P ₀ to P ₁₅ of the second stage are read addresses, that is, the order of calculation is expressed in binary numbers from the lowest b ₁ to the most significant b _4.
Among them, the lower two bits b ₁ and b ₂ are shifted one bit at a time to the upper side according to i=2, that is, the second bit b ₂ is the lowest bit b ₁
The least significant bit _b1 is the address transferred to the second bit _b2 . Writing is performed to the input/output memory of the second stage specified by this address.

Similarly, the calculation results of the second stage Q ₀ to Q ₅
As shown in FIG. 6, the lower three bits _b1 to _b3 corresponding to the order of the calculation are cyclically shifted by one bit toward the upper side. That is, the third most significant bit _b3 is moved to the least significant bit _b1 , the second bit _b2 is moved to the position of the third bit _b3 , and the least significant bit _b1 is moved to the second bit _b2. . The write address thus obtained becomes the write address for the input/output memory of the third stage. Similarly, when writing the calculation results R ₀ to R ₁₅ of the third stage to the input/output memory of the fourth stage as shown in FIG.
Only the lower 4 bits, that is, _b1 to _b4 , are cyclically shifted by one bit to the upper side. Therefore, the most significant bit _b4 is moved to the least significant bit _b1 to obtain the write address. Note that when the write address for the input/output memory of the first stage is inputted in the order of the input data x ₀ to x ₁₅ , the write address for that order is the most significant bit b ₄ as shown in Figure 8. The least significant bit _b1 is swapped, and the third bit _b3 and second bit _b2 are swapped to obtain the write address.

To generate such a write address, an address indicating the reading or operation order is generated from the address register unit 12 to the write address line 14, and the write address is connected to the write address line 14 and the input/output memory of each stage. address line and the 9th line
Just connect as shown in the figure. That is, in the first stage _S1 , the most significant bit and the least significant bit are exchanged and connected, the second and third bits are exchanged and connected, and in the second stage _S2 , the second bit and the first bit are connected. Only the bits are exchanged, and in the third stage _S3 , the third bit _B3 of the address line 14 is connected to the first bit of the memory address, the second bit is connected to the third bit of the memory, and the first bit is connected to the memory address. Connect to the second bit, respectively. Hereinafter, connections as shown in FIG. 9 may be made.
If the connections shown in FIG. 9 are made, write addresses corresponding to each stage can be obtained by simply generating write addresses in order like read addresses, and a common address generating means can be used.

The control unit 16 controls the entire device by decoding and executing a microprogram.
The command field is as shown in FIG. 10, for example. The arithmetic unit AU _i in each stage is also controlled by the control unit 16, and performs butterfly computation by pipeline computation as described above. This arithmetic unit is as shown in FIG. That is, the instruction state of the microinstruction is given as shown in FIG. 12, and by decoding this instruction, D ₁ to D ₆ , S 1 to S ₁ as shown in FIG.
_S4 Furthermore, a SUB control signal is generated and an instruction as shown in FIG. 13 is executed. In Figure 12
Rows D5 and D6 are AS1 and AS2 as shown in Figure 13.
indicates the processing content of the instruction, and AS3 indicates the storage location of the processing result. i.e. for example
AS1=0, AS2=1 is a move command, and AS3
is 0 (D5 = 0 in Figure 12), the execution result of the move command is stored in the accumulator ACCA in Figure 11 to which D5 is given, and AS3 is 1 (D5 = 0 in Figure 12).
If D6=1 in FIG. 2), the execution result of the move instruction is stored in the accumulator ACCB in FIG. 11 to which D6 is given. The input A in Figure 1 of the data read from the input/output memory using the instruction shown in Figure 13 is the register LR.
Input data B is stored in register JR, the twiddle factor is stored in register KR, and then the data in registers JR and KR are multiplied by a multiplier AUL,
The result is stored in register MR. Furthermore, this multiplication result is stored in the accumulator ACCA or ACCB. The multiplication result ^WkB passes through the multiplexer _Mpx3 , the exclusive OR circuit _X0R , and further passes through the multiplexer _Mpx2 to the adder ADD. All “0” or all “1”, and in the case of the former, add the output and the contents of register LR.
A' is obtained, and in the latter case, when adding it to the contents of the register LR, "1" is further added to obtain the complement of W ^k B, and B' is obtained as the addition result. Data is input and each part is controlled by these so that the butterfly operation shown in FIG. 1 is executed in a pipeline manner. The calculation result is sent to the next stage through multiplexer M _px4 .

FIG. 14 shows a time chart of an example of the operation of the pipeline butterfly operation in the arithmetic unit. As shown in the figure, the butterfly operation is performed separately for the real part and the imaginary part as shown in equation (4). First, data B is multiplied by the imaginary part of the twiddle factor, and then the real part is multiplied. Multiplication is performed, then the real part and the imaginary part are multiplied, and together with this, the multiplication results are added - and the real part of data A is taken in, and these additions are performed, and the addition result is is transferred to the memory MU of the next stage as Re(A') at the next clock. Thereafter, the calculation of equation (4) is similarly executed in a pipelined manner.

As described above, according to the present invention, butterfly calculations are performed in a pipelined manner within each stage, and pipelined calculations are performed in the entire stage, increasing the multiplier usage efficiency to nearly 100%. It operates at high speed, and its structure is extremely simple because it uses a common control unit and address register unit for generating addresses for each stage.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the display of butterfly calculation,
Fig. 2 is a diagram showing butterfly computation at each stage of fast Fourier computation, Fig. 3 is a block diagram showing an example of a pipeline fast Fourier transform device according to the present invention, and Fig. 4 is a diagram for explaining the pipeline computation operation. , and FIGS. 5 to 7 are diagrams showing the relationship between the calculation order and the write address to explain the write address, respectively. FIG. 8 is a diagram showing the relationship between the order of input data and the write address, and FIG. 9 is a diagram showing the relationship between the order of input data and the write address. 10 is a diagram showing an example of converting a write address by connecting a write address line, FIG. 10 is a diagram showing a microinstruction field, FIG. 11 is a block diagram showing an example of an operation unit, and FIG. 12 is an example of an operation unit. Figure 13 is a diagram showing the relationship between signals that control each part of the unit and microinstructions, Figure 13 is a diagram showing an example of the contents of the instructions shown in Figure 12, and Figure 14 is a time diagram showing an example of pipeline operation of the operation unit. It's a chat. 11: Input terminal, 12: Address register unit, 13: Read address line, 14: Write address line, 15: Output terminal, 16: Common control unit, _S1 to _Sn : Stage, _M11 to _Mn2 : Input/output _M10 to _Mn0 : Third memory for twiddle factors, _AU1 to _AUn : Arithmetic unit, _M01 ,
_M02 : Output buffer memory.

Claims (1)

[Scope of Claims] 1. A plurality of stages consisting of first and second memories for input/output, a third memory in which twiddle factors are stored, and an arithmetic unit that performs butterfly computation using a pipeline method, and a final computation result. is stored in the first and second output buffer memories, and the butterfly calculations in each stage are performed in a pipeline manner, and the results of the calculations are stored in the first and second memories for input/output of the next stage. a control unit that writes to one memory and controls all stages to perform pipeline operations as a whole;
and an address register unit for generating a common address for accessing each memory in each of the stages. 2. The write address for the i-th stage and the write address line from the address register unit are connected so that the lower i bits are cyclically shifted by 1 bit in the upper direction. A pipeline fast Fourier transform device according to claim 1.