JPH0748168B2 - Timer processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a timer processing method in a system for accessing a timer circuit connected to an external bus and sequentially reading the count value and the status thereof. A timer circuit that counts the clock and outputs the count value and the status of underflow or overflow is provided for the purpose of preventing the reading error due to the influence, and the count value and the status of the timer circuit are respectively In a computer system that performs read timer processing via the same bus at a sequential count value read timing and a status read timing, a status register accessed via the bus and an underflow or overflow of the timer circuit. A latch for temporarily holding the status of the timer and a gate for selecting the status output of the latch at the count value reading timing and outputting to the status register, and reading the count value of the timer circuit at the count value reading timing. At this time, the gates are controlled simultaneously, the status output is set in the status register through the latch, and the status register can be read at the subsequent status reading timing.

[Industrial application field]

The present invention relates to a timer processing method in a computer system, and more particularly to a timer processing method in a system that accesses a timer circuit connected to an external bus and sequentially reads its count value and status.

[Conventional technology]

In many conventional computer systems, a timer circuit provided to inform the CPU of preset timing is
It is connected to an internal bus that can be directly accessed by the CPU. In this case, there was no big problem because access time was not delayed much.

However, in a system in which the timer circuit is connected to an external bus such as an I / O bus that requires bus arbitration (bus right acquisition control), access to the timer circuit cannot be obtained without acquiring the bus right. However, there were times when delays occurred and accurate timing control became impossible.

FIG. 5 shows an example of such a conventional system. In FIG. 5, 1 is a computer unit, 2 is a CPU, 3 is a main memory, 4 is an internal bus, 5 is an I / O bus interface, 6 is an I / O bus, 7 is a timer circuit, and 8 is on the main memory 3. Is a software timer, 9 is a timer control program for controlling the software timer 8, and 10 is a status register.

The timer circuit 7 is a cyclic counter that receives a clock pulse as an input and counts down from a fixed value or counts up to a fixed value, and is configured by hardware. The output of the timer circuit 7 differs depending on the count value and whether the counter is down-counting or up-counting.
It consists of a status indicating the presence or absence of output.

The software timer 8 is a timer controlled by the timer control program 9 in order to generate clock data for date and time analysis, for example, and its bit width is larger than that of the timer circuit 7. Timer control program 9
Accesses the timer circuit 7, reads the count value and the status of the timer circuit 7, and repeats the operation of updating the lower bit part and the upper bit part of the software timer 8 with the respective values. Here, the lower bit part of the software timer 8 has the same length as the bit width of the count value read from the timer circuit 7.

To read the count value of the timer circuit 7 and the status,
The status is performed from the status register 10 separately from the hardware configuration restrictions.

The status register 10 has a value that directly reflects the status change during the operation of the timer circuit 7.

When the timer control program 9 first reads the count value from the timer circuit 7, the corresponding lower bit part of the software timer 8 is updated with that value, and then the status is read from the timer circuit 7 to check whether the status underflows or overflows. If it is indicated that it has occurred, the upper bit portion of the software timer 8 is updated by -1 or +1.

In this way, the lower bit part of the software timer 8 is updated correspondingly every time the count value of the timer circuit 7 is read, and the upper bit part shows that the status read from the timer circuit 7 is under Updated every time a flow or overflow is indicated.

[Problems to be Solved by the Invention]

In the conventional example of FIG. 5, the cycle in which the timer control program 9 executes the instruction to read the value of the timer circuit 7 is not constant depending on the processing state of the CPU 2, and the bus use right is assigned by the bus arbitration of the I / O bus 6. You may not be able to obtain it immediately. Therefore, a considerable time difference may occur between the timing of reading the count value from the timer circuit 7 and the timing of reading the status.

As a result, as illustrated in FIG. 6, underflow occurs when the count value is read from the timer circuit 7, but the count of the timer circuit 7 advances when the status is read next time. However, there is a problem in that the underflow may have already disappeared, and a status read error may occur, causing an error in the software timer 8.

[Means for Solving the Problems]

According to the present invention, the underflow or overflow status output of the output status from the timer circuit occurs only for a short time when the counter mechanism counts down from zero to full count or from full count to zero. Paying attention to the influence of timing delay, the status is set in the status register when the count value is read from the timer circuit, and it is held until the status is read. If an underflow or overflow occurs, The status is read reliably regardless of the time difference between reading the count value and reading the status.

FIG. 1 is a block diagram of the principle of the present invention, and is shown as an improved version of the conventional system shown in FIG. 5 for convenience.

In the figure, 1 is a computer unit, 6 is an I / O bus, 7 is a timer circuit, and 8
Is a software timer, 10 is a status register, 11 is a status writing control circuit, 12 is a latch, and 13 is a gate.

The reading of the count value and the status from the timer circuit 7 is performed twice as indicated by. The status is read from the status register 10.

The status write control circuit 11 includes a latch 12 that temporarily holds the underflow or overflow status output of the timer circuit 7, and a gate 13 that writes the status held in the latch 12 to the status register 10 at the timing of reading the count value. Become.

[Work]

In FIG. 1, when the count value is read from the timer circuit, the status write control circuit 11 writes the status held in the latch 12 at that time to the status register 10.

The next time the status is read, the status held in status register 10 is read,
There is no chance that the status reading will fail due to the time difference between and.

Further, when the count value is read from the timer circuit 7, no underflow or overflow has occurred,
If it occurs immediately after that, the latch 12 in the status write control circuit 11 temporarily holds this status, sets it in the status register 10 at the timing when the next count value is read, and then reads the status. Read it at the timing.

The latch 12 is reset at the end of the read timing of the count value, and the status register 10 is reset at the end of the read timing of the status to prevent double reading of the status.

〔Example〕

The principle configuration of the present invention shown in FIG. 1 can be directly applied to the conventional system of FIG. 5, in which case the computer unit 1 side does not need to be changed.

FIG. 2 to FIG. 4 show the operation timing in such an embodiment divided into case 1, case 2, and case 3. In this embodiment, the timer circuit 7 performs a countdown operation and outputs an underflow (borrow) when the count value is 0.

2 to 5, "clock" is the count clock of the timer circuit 7, "count value" is the current value of the count result, and "count value read" and "status read" are from the computer unit 1, respectively. The given read timing, "underflow" is the underflow output of the timer circuit 7, "latch" is the output value of the latch 12 in FIG. 1, and "status" is the output value of the status register 10 in FIG.

In case 1 in FIG. 2, underflow does not occur during reading of the count value of the timer circuit and during reading of the status, so the underflow status cannot be read.

In case 2 of FIG. 3, an underflow does not occur at the timing of reading the count value, but an underflow occurs at the timing of reading the next status. This underflow output is immediately set in the latch 12,
It is set in the status register 10 at the timing of reading the subsequent count value, and is read at the timing of reading the status thereafter.

In case 3 of FIG. 4, an underflow occurs at the timing of reading the count value. Latch in this case
The status is set in the status register 10 via 12 and is read at the timing of the subsequent status reading.

In this way, even if an underflow occurs at any timing, reading is performed without omission.

〔The invention's effect〕

According to the present invention, even if the timer circuit is connected to an external bus such as an I / O bus and the access timing is delayed, the count value and status can be reliably read without being aware of the timing delay. Therefore, it is possible to eliminate the decrease in accuracy in applications such as using these read results for controlling the software timer.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIGS. 2 to 4 are operation timing diagrams of cases 1 to 3 of the embodiment of the present invention, and FIG. 5 is a block diagram of an example of a conventional system, FIG. FIG. 4 is an operation timing chart of the conventional system. In Fig. 1, 1: Computer unit 6: I / O bus 7: Timer circuit 8: Software timer 10: Status register 11: Status write control circuit 12: Latch 13: Gate

Claims (1)

[Claims] 1. A timer circuit that counts clocks and outputs the count value and an underflow or overflow status. The count value and the status of the timer circuit are sequentially read and read, respectively. In a computer system that performs read timer processing via the same bus depending on timing, a status register accessed via the bus, a latch that temporarily holds the underflow or overflow status of the timer circuit, and the latch Status output of the timer circuit is selected at the count value reading timing and output to the status register. When the count value of the timer circuit is read at the count value reading timing, the gate is simultaneously controlled. Timer processing method, and sets a status output to the status register via the latch, characterized in that reading the status register in the subsequent status read timing.