JPH0746329B2 - Micro computer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro computer device having a ROM as a memory, and more particularly to a micro computer device suitable for performing a data check of a memory.

[Conventional technology]

To perform a data check of a conventional microcomputer computer having a ROM as a memory, for example, JP-A-60-10
As shown in Japanese Patent No. 8944, when the power is turned on, the address corresponding to the ROM data is generated by the address generation circuit,
A parity bit is generated by the parity generator using the data pattern from the ROM, and this parity bit is RA.
By storing the data in M, the data in the ROM was parity checked after this.

[Problems to be solved by the invention]

In the above-mentioned conventional data check, since parity bit is generated by the data pattern of ROM, the memory space is limited to only the ROM mounting area. If the conventional data check is applied to the entire area of the memory space, the parity check cannot be performed in the non-mounted area of the memory element, or the random pattern of the memory non-mounted area (the pattern of the normal memory non-mounted area is Since a parity bit is generated by all “1”), there is a problem that a parity error does not occur even if the memory non-mounted area is accessed.

An object of the present invention is to provide a microprocessor device capable of performing parity check by generating and storing a parity bit capable of parity check for all areas of a memory space by a pattern of a memory element.

[Means for solving problems]

As for the above-mentioned problem, regarding the memory non-mounted area, information that the memory is not mounted is read (data A), written (data B) to one address, then instantaneously read (data C), and finally It is solved by reading again (data D) after a while and comparing and obtaining those data.

[Action]

According to the above means, when the respective data have the following relationships, it is detected whether the memory is ROM, RAM or not mounted.
(I) ROM area when data A = D and data B ≠ C, (ii) RAM area when data B = C = D, (iii) data A = D and data B = C and data B When ≠ D, the memory is not mounted.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

FIG. 1 is a hardware configuration diagram showing an embodiment of a microcomputer computer according to the present invention. In FIG. 1, reference numeral 1 is a microprocessor MPU, 2 is a program memory ROM for storing a program of the MPU 1, and has ROM and RAM mounting areas of memory elements and non-mounting areas of memory elements in the entire memory space. 3 is a parity memory RAM that stores parity bits corresponding to the data of each memory address for checking the data of ROM 2 at an address corresponding to each memory address, and 4 is a memory element mounted at each memory address of ROM 2. A mounting state display memory RAM that stores mounting state information indicating whether or not each memory address is present.

5 is RAM MR (memory read) signal 5a or RAM MW (memory write) signal depending on MR (memory read) signal 1a of MPU1
RAM WRITE CTL (write control) circuit that outputs 5b and DATA CTL (data control) signal 5c.
Is a power-on detector, and 7 is a manual signal generator (MANUAL). DATA 8 forcibly outputs to the data bus 18 a data pattern (instruction word without execution: skip) in which the MPU 1 is in no operation by disconnecting the data bus 15 and the data bus 18 by the signal 5c of the RAM WRITE CTL5. A CTL (data control) circuit 9 is a "0" GEN (generator) for generating a "0" data pattern which is no operation in this case.

10 is an address decoder (ADDR DECOD) that sequentially decodes the addresses of all memory spaces of ROM2 by the address bus.
E). Reference numeral 11 is a parity check generator (PTY CHECK GEN) that generates parity bits according to the data output from ROM2. Reference numeral 12 is a memory mounting detection circuit (MOUNT) for detecting whether the memory device is ROM or RAM or not mounted according to the data output from ROM2.
DET). 13 is a parity error detection circuit (PTY ERR D
ET) and 14 are error processing circuits (ERR). Reference numeral 15 is a data bus, 16 is an address bus, 17 is an OR gate, and 18 is a data bus.

FIG. 2 is a detailed structural example diagram of the RAM WRITE CTL5 of FIG. In FIG. 2, 20 is a flip-flop (FF), 21
Is a delay circuit, 22 is an EX-OR circuit, 23 is a NAND circuit, 24 and 25 are inverter circuits, 26 is a tri-state gate circuit, and 27 is a pull-up resistor. Fig. 3 shows R in Fig. 2
AM WRITE CTL5 This is a time chart for signals. FIG. 4 is a detailed configuration example diagram of the DATA CTL 8 of FIG. In FIG. 4, 41 and 42 are inverter circuits, 43 and 44 are NAND circuits, 4
Reference numerals 5,46,47 are tristate gate circuits.

FIG. 5 is a conceptual diagram showing a memory configuration example of the ROM2, RAM3, 4 in FIG. In FIG. 5, there is an area in which the ROM and RAM of the memory element are mounted and an unmounted area in which neither the ROM nor the RAM of the memory element is mounted in the entire memory space (address 0 to address N) of the ROM2. In other words, ROM2 has an area where neither memory element ROM nor RAM exists as a memory unmounted area, but it is assumed that neither a socket nor an edge exists on the circuit, and neither ROM nor RAM is mounted on the socket. Is. FIG. 6 is a time chart for determining whether the ROM2, the RAM, or the unmounted area of the ROM2 of the memory mounting detection circuit 12 of FIG. Further, FIG. 7 is a flow chart for explaining the operation of FIG.

Now, when power is turned on to the microprocessor device of FIG. 1, the detection signal 6a by the power-on (POWER ON) detector 6 or the signal generator (MANUAL) 7 by the manual 7
The signal 7a by means of the OR gate 17 and the signal 17a by the RAM
Tell WRITE CTL5. The RAM WRITE CTL5 processes the MR (memory read) signal 1a output by the MPU1 which started operation when the power was turned on as follows.

In RAM WRITE CTL5 in Fig. 2, the power-on signal 17a is FF20.
The data CTL signal 5c is output. One MPU1
The MR (▲ ▼) signal 1a from the Becoming 5a or processed It will be decided whether it will be 5b. At this time, the RAM MR signal 5a and RA are controlled by the inverter circuit 25 and pull-up resistor 27.
M MW signal 5b is always selected to be either. RAM MW signal 5b
The delay circuit 21, the EX-OR circuit 22, the inverter circuit 24, and the NAND circuit 23 are used for the time chart of the signal in the RAM WRITE CTL5 of FIG. As shown by, the time T is earlier than the trailing edge of ▲ ▼ signal 1a from MPU1. It is processed so that the trailing edge of it rises. The RAM in Figure 3
The MR (▲ ▼) signal from MPU1 is displayed after the power is turned on (POWER ON) for the time chart of the signal in WRITE CTL5. 5a or The timing of conversion to 5b and the timing of controlling the READ (write) and WRITE (write) modes for the RAMs 3 and 4 by the signal 10a from the address decoder (ADDR DECODE) 10 in FIG. 1 are shown.

In the mode to write RAS information to RAM (RAM WRITE mode), MR signal output by MPU1 in Fig. 1 starts operation.
The ROM2 is read by 1a, the address corresponding to the entire addressable memory space of the ROM2 is started from address 0 by the MPU1, and the contents of the memory according to the addresses on the address bus 16 are sequentially output to the data bus 15. Output. A parity bit is generated by the parity check generator (PTY CHECK GEN) 11 according to the pattern of the output data. Meanwhile, MR signal output from MPU 1
a is input to RAM3 as a RAM WRITE signal 1b processed by the above RAM WRITE CTL5. As a result, the parity bit from the parity checker / generator 11 is RA.
Memorized in M3.

While writing parity bit according to the data pattern of ROM2 to this parity RAM3, DATA CTL8 is RAM WRI
Data bus 15 and data bus 18 by signal 5c of TE CTL5
The MPU1 is forcibly output to the data bus 18 by disconnecting the data pattern. Of FIG.
DATA CTL8 shows one of the data buses 15 and 18, and the "0" data pattern generated by "0" GEN9 is forcibly controlled by the DATA CTL signal 5c of RAM WRITE CTL5. Pour on. As a result, the MPU1 detects the no-operation instruction and advances the address to 1 to read the next address of ROM2 without executing it.
Is output. In this way, when the MPU 1 finishes outputting all the addresses of all the memory spaces of the ROM 2, the parity RAM 3 stores the parity bit information for all the memory spaces.

Next, the address decoder 10 decodes the final address of the entire memory space of ROM2 from the address bus 16 and outputs the signal 10a.
To RAM WRITE CTL5. This makes RA in Fig. 2
DATA CTL signal 5c by switching the state of FF20 of M WRITE CTL5
By controlling the MR signal 1a of MPU1 to RAM WRITE CT.
Output from L5 to RAM3,4 as RAM MR signal 5a. Also RA
The DATA CTL signal 5c from M WRITE CTL5 causes DA in FIG.
TA CTL8 connects the data bus 15 and the data bus 18.

In the RAM read-only mode (RAM READ mode) after the above signal switching, the MPU1 restarts the address corresponding to the entire memory space of the ROM2 from the address 0 by the MR signal 1a, and sequentially outputs the addresses. In accordance with the address on the address bus 16, the microprogram repeats writing (writing) and reading (reading) for all addresses in the entire memory space of the ROM 2 at the timing of FIG. The memory mounting detection circuit (MOUNT DET) 12 determines whether the memory element is ROM, RAM, or not mounted by comparison as follows. That is, first, the content of the memory is read and stored for one address (data A), and then data B other than data A is written and stored in the memory of the same address (data B). The contents of the memory at the same address are read out and stored therein (data C), and after a while, the contents of the memory at the same address are read out again (data D).

Accordingly, the memory mounting detection circuit 12 determines the memory mounting state by the following relational expression. That is, (i) ROM mounting area when data A = D and data B ≠ C, (ii) RAM mounting area when data B = C = D, (iii) data A = D and data B = C and When the data B ≠ D, the memory non-mounting area is set (“and” is the AND condition of AND).

Note that the above relational expression uses the characteristic (principle of dynamic RAM) that the data B written in is temporarily stored by the floating capacitance in the memory unmounted area. In other words, the RO of the memory element is
The circuit is open because M or RAM is not mounted, but there is a slight capacitance such as stray capacitance. Therefore, according to the timing shown in FIG. 6, the above data B is written in the unmounted area of the memory,
When the same area is immediately read with, the data C at that time
As a result, the pattern of the data B written by the electric charge accumulated by the capacitance such as the floating capacitance can be read (data B = C). However, even if the same area is read after a certain period of time, as the data D at that time, the charge accumulated in the capacitance such as the stray capacitance is discharged, so the pattern of the written data B disappears and cannot be read ( Usually all
“1”) (pattern B ≠ D). Thus, the relational expression for determining whether the above memory device is ROM, RAM or not mounted is (i) ROM
In case of mounting area, data A = D (read data of ROM is unchanged) and data B ≠ C (writing to ROM is impossible)
Becomes (Ii) Data B = C in case of RAM mounting area
= D (the data written to the RAM is the same as the pattern of the written data even if it is read immediately or after a while). (Iii) In the case of the memory unmounted area, the data is A = D = fixed pattern (the data read when it is stable over time becomes the normal fixed pattern all “1” because the memory is not mounted), and the data B = C and data B ≠ D (depending on the characteristics of the above unmounted area).

When the memory mounting detection circuit 12 detects whether the memory area is the ROM mounting area, the RAM mounting area, or the memory non-mounting area for the entire memory space of ROM2 as described above, the memory status display bit indicating the memory status is displayed.
At the same time as storing in the ROM4, the parity bit for detecting the parity error is written from the parity checker / generator 11 to the parity RAM3 for the address of the memory unmounted area.

Then run a normal program to output the output data 3a of parity RAM3 and the output data 4a of memory mounting status display RAM4.
By comparing the output data pattern of ROM2 with the parity checker / generator 11 and checking the data of ROM2, if a parity error occurs in the mounted area of the memory, or if the address of the non-mounted area of the memory is accessed, Signal of the Parity Chez Car Generator 11 at
Parity error detection circuit (PTY ERR DET) 13
Data is input to the error processing circuit (ERR) 14
Parity error processing is performed by informing.

As described above, according to the present embodiment, in a memory parity check of a device (microcomputer device) equipped with a microcomputer, the first address to the last address of the memory are sequentially read at power-on, and the read pattern is read. To generate a parity bit and write it to the 1-bit parity RAM corresponding to the address of the memory, and to write the information that the unmounted area of the memory is not mounted to the 1-bit memory mounting status display memory. A parity check ROM for the configured memory space is not required, and a parity check error can be detected in the memory unmounted area.

〔The invention's effect〕

As described above, according to the present invention, the parity check ROM for the memory space configured by the ROM of the microcomputer device is not necessary, and the parity check error can be detected in the memory non-mounted area without fail. Become.

[Brief description of drawings]

FIG. 1 is a hardware configuration diagram showing an embodiment of the microcomputer device according to the present invention, and FIG. 2 is the RAM of FIG.
Detailed configuration diagram of the WRITE control circuit, FIG. 3 is a signal timing chart of FIG. 2, FIG. 4 is a detailed configuration diagram of the DATA control circuit of FIG. 1, and FIG. 5 is a memory configuration of the ROM and RAM of FIG. An example diagram, FIG. 6 is a determination time chart of the memory mounting detection circuit of FIG. 1, and FIG. 7 is an operation flow chart of FIG. 1 ... MPU, 2 ... ROM, 3 ... Parity RAM, 4 ... Mounting status display memory, 5 ... RAM WRITE control circuit, 6 ... Power-on detector, 8 ... DATA control circuit, 9 ... "0" generation circuit, 10 ... Address decoder,
11 ... Parity checker / generator, 12 ... Memory mounting detection circuit, 13 ... Parity error detection circuit, 14 ...
… Error processing circuit.

Front Page Continuation (72) Inventor Masato Satake 5-2-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Omika Plant (56) References JP-A-60-108944 (JP, A) JP-A 58-125125 (JP, A) JP-A-56-134397 (JP, A) JP-A-57-117187 (JP, A)

Claims (1)

[Claims] 1. A parity check of a memory area by writing means for generating a parity bit based on a data pattern read by accessing the memory area and writing the parity bit in the parity storage means, and a parity bit written in the parity storage means. In a microcomputer device including a parity check means for performing the above, for each address in the memory area, the data at that address is first read to be data A, and then data other than data A is written to the same address to be data B, and instantaneously. The data of the same address is read out as data C, and after a while, the data of the same address is read again as data D. When A = D and B ≠ C, ROM is mounted. When B = C = D, RAM is mounted. When A = D and B = C and B ≠ D, the judgment method for judging the memory non-mounting Wherein the writing means, the determining means microcomputer system, characterized in that to generate parity bits as a parity error for the address of the memory area where it is determined that the memory unimplemented written in the parity storage means.