JPH0746325B2 - Data processing system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory used in, for example, a data processing device and provided with a lock warning mechanism.

Related Applications The subject matter related to this application is disclosed in the following co-pending US applications, all of which are assigned to the same assignee as the present invention.

1. US application 718,753 filed on April 1, 1985, "Memory controller with page having variable number of levels of conversion table".
The inventors were William Mall Keshlear, William C. Moyer, and John Zolnowsky.

2. US application 718,669 filed April 1, 1985, "Memory controller with page with variable conversion table size". Inventors William C. Moyer, John Zolnowsky, and William
Mall Keshlear.

3. U.S. application 718,608, filed April 1, 1985, "Memory Controller With Pages With Selected Translation Table Index". Inventor Mi Chael W. Cruess, William Mall Keshl
ear, and John Zolnowskey.

2. Description of the Related Art Certain applications, such as controlling memory in a data processing system, utilize a cache to maintain relevant information for different periods of use. For example, in the paged memory controller (PMMU) described in some of the above-mentioned co-pending applications, logical-to-physical address translation data is maintained in a translation data cache. Also,
Often we want to be able to access certain code / data pages quickly and reliably. For this reason, one solution that requires these page translations to be available in the cache for the required duration is to use each translation in the cache (transl
ator), when set, provides a lock indicator that prevents the removal of the conversion data to provide vacancy for another conversion data. When a given page is no longer needed, the PMMU can be instructed by the processor to reset the lock indicator for the conversion data for that page, making it a candidate for exchange. be able to.

In some situations, processing activity may cause the cache to fill up with translated data that is locked. If this happens, the PMMU will not be able to cache the new converted data. as a result,
The PMMU will effectively be prevented from performing conversions for which the conversion data was not previously in cache. One solution to this problem is to have the PMMU interrupt the processor as soon as the last input is locked, so that the processor can take remedial action immediately. This solution could be acceptable on a system where the operating system's memory control routines are always accessible (eg, because the associated translation data resides in something locked in the cache). One example of such a system is US Pat.
No. 084,226.

However, in general, this solution is inherently risky, and is an independent means of accessing the memory control routines, dedicating a portion of the cache to the required translated data,
Or another emergency release mechanism is needed.

It is an object of the invention to provide a mechanism for issuing a warning signal when all but a predetermined number of inputs in the cache are locked.

Another object of the invention is that the last entry in the cache is
The goal is to provide a mechanism to ensure that the input is not locked if it would otherwise be locked.

In carrying out these and other objects of the invention, in one form, each storage location is associated with an associated lock lock adapted to be selectively set and reset. It has an indicator. Stores an operand in a selected one of the storage locations and a selected one of the storage locations only if the associated lock indicator is reset, and locks depending on the lock signal that mixes with the stored operands. Circuitry is provided for use in combination with a cache having control logic that sets an indicator and resets a lock indicator for a particular storage location in response to a signal indicating that the storage location should be unlocked. In accordance with the present invention, this circuit is coupled with lock indicators at all storage locations to generate a lock warning signal when all lock indicators except a predetermined number of lock indicators are set. Is equipped with. In the preferred form, the control logic is prohibited by the lock warning signal from setting the lock indicator associated with the storage location even if the operand stored therein has a lock signal associated with it.

(Example) The data processing device 12 and the data
A data processing system 10 having a bus 16 and a memory 14 coupled thereto via an address bus 18. A memory controller with page (PMMU) 20 translates the logical portion of the address sent from the processing unit 12 via the address bus 18 to the memory 14 into the corresponding portion of the physical address. PMMU
Multiple storage locations associated with 20 each of which have respective associated lock indicators 26a-26n
There is a translated data cache 20 having 24a-24n. For each logical address sent from the processing unit 12, the PMMU 20 searches the conversion data cache 22 for the corresponding logical-physical conversion data. If not found, processor 12 is forced to abandon the access cycle and releases buses 16 and 18 to allow PMMU 20 to access a set of translation tables stored in memory 14 and place them in translation data cache 22. -Be able to determine the physical address translation data. Subsequently, when processor 12 resumes the abandoned access cycle, PMMU 20 uses the new translation data in the translation data cache to determine the proper physical address to send to memory 14. Then, if the processing unit 12 accesses the logical address of the same logical page again, the PMMU
20 reuses the conversion data of the conversion data cache 22.

When all storage locations 24a-24n of the transform data cache 22 are full due to processing activity of the processing unit 12, the PMMU 20 uses an appropriate exchange algorithm to determine which existing transform data to exchange with the new transform data. I have to decide. In order to prevent certain translation data from being considered as candidates for this translation algorithm, each translation descriptor of the translation table stored in memory 14 comprises a lock field. PMMU20 converted data cache
This lock field is "locked" when using a specific conversion descriptor to construct the conversion data to put in 22.
If so, the PMMU 20 sets the lock bit 26x at the storage location 24x selected to store the corresponding conversion data. Specific Lock Bit 26x
Corresponding storage location as long as is set
24x is never a candidate for an exchange algorithm.

In order to detect when the conversion data cache 22 may be filled with locked conversion data, a lock warning circuit 28 is wire-ORed to the corresponding inverting buffers 30a-30n and node 34 to pull down transistor 32a.
.About.32n and connected to each of the lock bits 26a-26n. In general, when the voltage on node 34 rises above a certain level due to all but one of the lock bits 26a-26n being set, the self-biased sense amplifier 36 locks to the PMMU 20 via the level shifter 38. Send a warning signal.

In the illustrated form, sense amplifier 36 is a CMOS with the input coupled to node 34 and the output coupled to node 42.
It has an inverter 40 and a pair of n-channel transistors 44 and 46 which supply current to node 34 at a rate determined by the voltage applied to node 42. The transistor 44 is
Operating in depletion mode to deliver a trickle current to node 34, transistor 46 connects node 34 to node 42
The current is supplied at a rate substantially proportional to the voltage applied to.
The current in transistors 44 and 46 is from the PMMU20 to the inverter.
It is provided by P-channel transistor 48 in response to an enable signal provided via 50. When there is no enable signal, transistor 48 does not supply current, but n-channel transistor 52 draws current from node 34, so the voltage on node 34 is below the switch point of inverter 40.

In the preferred embodiment, transistor 46 is sized to provide about the same amount of current as one of transistors 32a-32n can draw, so that both transistors 44 and 46 are connected to pull-down transistors 32a-32n. Corresponding lock bit 26a, only one of which is reset
The voltage applied to the node 34 can be set higher than the switch point of the inverter 40 as long as it is conducted by ~ 26n. However, when two or more of lock bits 26a-26n are reset, transistors 44 and 46
Will be extra powered by the sum of the active pull-down transistors 32a-32n, causing the voltage on node 34 to drop below the switch point of inverter 40. Thus, the voltage on node 42 is
It depends on the number of ~ 26n reset.

Level shifter 38 has its input coupled to node 56 and its output
A CMOS inverter 54 coupled to the PMMU 20, an n-channel transistor 58 that draws current from node 56 in response to an enable signal, and a pair of n-channel transistors that supply current to node 56 at a rate determined by the voltage at node 42. It consists of 60 and 62. Sense amplifier 36
As in the case of, the transistor 60 has a depletion
Mode to deliver the trickle current to node 56,
Supplies current to node 56 at a rate substantially proportional to the voltage across node 42. Transistors 60 and 58 and / or 62 are replaced by transistors 44 and 46, respectively.
By making it the same size as
Move 42 levels to normal logic level. Thus, the inverter 54 is only reset when only one of the lock bits 26a-26n is reset, that is, from a different perspective, all but one of the lock bits 26a-26n are set. The lock warning signal will be generated as long as it is present.

In response to the lock alert signal, the PMMU 20 can set an appropriate status indicator, or otherwise alert the processor 12 that the translation data cache 22 may be filled with locked translation data. Emit. In the preferred form, the lock warning signal is the lock bit 26x of the remaining unlocked storage location 24x.
PMMU 20 reserves at least one storage location in the conversion data cache 22 for storing new conversion data. In this way, performance will be reduced, but at least system 10 can continue to operate until processor 12 can resolve the problem.

When a particular page is no longer needed, the processor 12
The PMMU 20 can be instructed to "flush" the corresponding conversion data from the conversion data cache 22. In response, PMMU 20 sets an indicator that the particular storage location 24x containing this conversion data is no longer valid, or at least a candidate for exchange. If the associated lock bit 26x is set, the PMMU 20 should also reset this lock bit 26x. In other words, these locked storage locations 24a-24n can be unlocked by special instructions of the processor 12, but at least one of the storage locations 24a-24n is always unlocked.

Although the lock alert mechanism has been described herein as triggering when all but one of the storage locations 24a-24n are set to have the associated lock bit 26a-26n set, the embodiment shown in the figures shows a selected number. Can be modified to generate a lock warning signal when all storage locations 24a-24n except their storage locations have their associated lock bits 26a-26n set. Similarly,
PMMU 20 may otherwise respond to the lock alert signal without departing from the spirit and scope of the present invention.

[Brief description of drawings]

The accompanying drawings are schematic block circuit diagrams of lock warning circuits constructed in accordance with the present invention. 12 ... Data processing device, 14 ... Memory, 20 ... Memory controller with page, 22 ... Conversion data cache, 24a
~ 24n ... storage location, 26a-26n ... lock bit, 30a-30n ... inverting buffer, 36 ... sense amplifier, 38 ... level shifter, 40, 50, 54 ... inverter.

Front Page Continuation (72) Inventor James G. Gay, Auto Meadow Drive 501, Full Gerville, Texas 78660, USA 501 (72) Inventor Jesse Earl Wilson Texas 78758, Austin, Silvery Drive 1009 (56) References JP-A-54-89437 (JP, A)

Claims (1)

[Claims] 1. A data processing system (10) having a lock warning mechanism for a cache, the data processing device (12) providing a logical address for conversion to a physical address, coupled to the data processing device. An address bus (18) coupled to the address, the memory (14) providing data to the data processing device and addressed by a physical address, the data processing device and the memory A memory controller (20) coupled to the memory controller by the address bus, and a cache (22) coupled to the memory controller, the cache being logically connected to a plurality of storage locations.
Storing physical address translation data, each storage location having an associated lock indicator configured to be selectively set and reset by the data processing device, the contents of each storage location being Non-replaceable as long as the associated lock indicator is set, and whether or not only as many storage locations have the associated lock indicator set, and all of the storage locations in the cache A lock warning circuit (28) coupled to the lock indicator of the memory controller and also to the memory controller, the lock warning circuit being configured to lock the memory controller when a predetermined number of storage locations of the cache are locked. By providing a lock warning signal to To prevent that all of the entry of the serial cache is disabled replacement is locked,
The memory controller notifies the data processor that the cache is at risk of being completely filled with a locked storage location in response to receiving a lock warning signal from the lock warning circuit. A data processing system (10) having a lock warning mechanism for a cache characterized by the above.