JPS62156744A - Cash memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a cache memory used, for example, in a data processing device and equipped with a lock warning mechanism.

RELATED APPLICATIONS Subject matter related to this application is disclosed in the following co-pending United States applications, all of which are assigned to the same assignee as the present invention.

1. U.S. Application No. 718.753 filed April 1, 1985
"Paged memory controller with variable number of translation table levels." Inventor: William Hall KeShle
ar1Wi! ! iam C.) Foyer, and John Zolnowsky02.April 1, 1985
U.S. Pat. Inventor: Willi
am C,)tover, John Zolnows
ky, and William Hall Keshl.
ear 03. U.S. Application No. 71 filed April 1, 1985
8.6081 Paged Memory Controller with Selective Translation Table Index. Inventor: Hichael W. Crues
s, William Hall, eshlear, and JOhri Zolnowsky.

BACKGROUND OF THE INVENTION Certain applications, such as controlling the memory of a data processing system, utilize caches to maintain related information that has different lifetimes. For example, in paged memory controllers (PMMtJ), as described in some of the co-pending applications mentioned above, the logical-to-physical address translator is maintained in a translator cache. Also, it is often desirable to have reliable and quick access to certain code/data pages. For this reason, these page translators must be available in cache for the required period of time. One solution has been to associate each translator in the cache with a lock indicator that, when set, prevents removal of the translator to make room for another translator. When a given page is no longer needed, the PMMU can be instructed by the processor to reset the lock indicator of the translator for that page, thereby making this translator a candidate for replacement. be able to.

In some situations, processing activity may fill up the cache with a locked translator.

When this happens, the PMMU is unable to cache new translators. As a result, P.M.
The MU will effectively be prevented from performing translations for which its translator was not previously in the cache. One solution to this problem is to have PMMIJ interrupt the processor as soon as the last input is locked, so that the processor can immediately take remedial action. This solution may be acceptable in systems where the operating system's memory control routines are always accessible (eg, because the associated translator resides in a locked cache). An example of such a system is shown in U.S. Pat.
It is shown in 84,226@.

(Problem to be Solved by the Invention) However, in general, this solution is inherently risky and requires a separate means of accessing the memory control routines, dedicating part of the cache to the necessary translators, or Other emergency release mechanisms are required.

It is an object of the present invention to provide a mechanism for generating a warning signal when all but a predetermined number of entries in the cache are locked.

Another object of the invention is that the last entry in the cache is
To provide a mechanism to prevent the input from becoming locked even if it would otherwise be locked.

SUMMARY OF THE INVENTION In carrying out these and other objects of the present invention, in one form, each storage location has associated locks that are adapted to be selectively set and reset.
a plurality of storage locations for operand storage, with an indicator, storing the operand in a selected one of the storage locations only if the associated lock indicator is reset, and locking associated with the stored operand; A circuit for use in conjunction with a cache having control logic for setting a lock indicator in response to a signal and resetting the lock indicator for a particular storage location in response to a signal indicating that the storage location should be unlocked. is provided. In accordance with the present invention, this circuit is coupled to lock indicators of all storage locations to generate a lock warning signal when all but a predetermined number of lock indicators are set. It has logic. In a preferred form, the control logic is prohibited by a lock warning signal from setting a lock indicator associated with a storage location even if the operand stored therein has a lock signal associated with it.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Illustrated in the accompanying drawings is a data processing system 10 having a data processing device 12 and a memory 14 coupled thereto via a data bus 16 and an address bus 18. Paged memory management wJ unit (PMMU) 20 translates logical portions of addresses sent from processing unit 12 to memory 14 via address bus 18 into corresponding portions of physical addresses. Associated with PMMU 20 are respective associated lock indicators 26a-26.
a plurality of storage locations 24a-24n comprising n
There is a translator cache 20 having: In response to each logical address sent from processing unit 12, PMMU 20 caches translator cache 22 for the corresponding logical-to-physical translator.
Explore. If not found, processing unit 12 is forced to abandon the access cycle and free bus 16.18 so that PMMU 20 can use the appropriate logic to access the set of translation tables stored in memory 14 and place them into translator cache 22. - Be able to determine the physical address translator. Subsequently, when processor 12 resumes the abandoned access cycle, PMMU 20 uses the new translator in the translator cache to determine the correct physical address to send to memory 14.

Thereafter, when the processing device 12 accesses the logical address of the same logical page again, the PMMU 20t, l: the translator in the translator cache 22 is reused.

All storage locations 24a-24n of translator cache 22 for processing activity of processing unit 12
Once it is full, PMMU 20 must decide which existing translator to replace with a new one using an appropriate replacement algorithm. To ensure that no particular translator is considered a candidate for this exchange algorithm, each translation descriptor of the translation table stored in memory 14 is provided with a lock field. PMM
When LI 20 uses a particular translator descriptor to configure the translators it places in translator cache 22, if this lock field contains a "lock" value, then
PMMU 20 sets the lock bit 26x of the selected storage location 24X to store the corresponding translator. As long as a particular lock bit 26x is set, the corresponding storage location 24X will not be a candidate for the exchange algorithm.

In order to detect when the translator cache 22 is likely to be full of locked translators, a lock warning circuit 28 connects the corresponding inverting buffers 30a-30n and the node 3.
Lock bits 26a-- through pull-down transistors 328-32n wire-ORed to lock bits 26a--
26n.

Generally, the voltage across node 34 is set to lock bit 26.
When all but one of a through 26n rise above a certain level to be set, self-biased sense amplifier 36 sends a lock warning signal to PMMU 20 via level shifter 38.

In the illustrated form, sense amplifier 36 includes a CMOS inverter 40 having an input coupled to node 34 and an output coupled to node 42;
A pair of n-channel transistors 44 and 46 provide current at a rate determined by the voltage across the transistor. Transistor 44 operates in a depletion mode to provide a trickle current to node 34, and transistor 46 provides current to node 34 at a rate substantially proportional to the voltage across node 42. The current for transistors 44 and 46 is provided by P-channel transistor 48 in response to an enable signal provided from PMMU 20 via inverter 50. In the absence of an enable signal, transistor 48 does not source current, but n-channel transistor 52 conducts current from node 34 so that the voltage across node 34 is below the switch point of inverter 40.

In the preferred embodiment, transistors 44 and 46 are both sized to provide approximately the same amount of current as one of transistors 328-32n can conduct.
As long as only one of 2a-32n is conductive with the corresponding lock bit 26a-26n being reset, the voltage across node 34 can remain above the switch point of inverter 40. However, when two or more of lock bits 26a-26n are reset, transistors 44 and 46 will be powered as much as the sum of active pulldown transistors 32a-32n, and node 34 will be powered. This voltage is below the switch point of inverter 40. Thus, the voltage across node 42 is locked ◆Bit 268
It will vary depending on the number that has been reset, ~26n.

Level thick 38 includes a CMOS inverter 54 having an input coupled to node 56 and an output coupled to PMMU 20, an n-channel transistor 58 that conducts current from node 56h1 in response to an enable signal, and node 4.
It consists of a pair of n-channel transistors 60 and 62 that supply current to node 56 at a rate determined by the voltage of 2. As in the case of sense amplifier 36,
Transistor 60 provides a trickle current to node 56 in a depletion mode, and transistor 62 provides current to node 56 at a rate substantially proportional to the voltage across node 42. Transistors 60 and 58 and/or 62 are replaced by transistors 44 and 58 and/or 62, respectively.
46 causes inverter 54 to transition the level of node 42 to a normal logic level. In this way, inverter 54 locks bits 26a-2.
If only one of lock bits 6n is reset, that is, if you look at it another way, lock bit 26
A lock warning signal will be generated only when all but one of a to 26n are set.

In response to the lock warning signal, PMMU 20 may set appropriate status indicators or otherwise inform processing unit 12 that translator cache 22 may become full of locked translators. issue a warning. In a preferred form, the lock warning signal inhibits the setting of the lock bit 26x in the remaining unlocked storage locations 24x, so that the PMMU 20 reserves at least one storage location in the translator cache 22 for the new translator. . In this manner, performance will be degraded, but at least system 10 can continue to operate until processing unit 12 can resolve the problem.

When a particular page is no longer needed, processing device 12
may instruct PMMTJ 20 to "flush" the corresponding translator from translator cache 22. In response, PMMU 20 determines that the particular storage location 24x containing this translator is no longer valid. Sets an indicator of being present or at least a candidate for replacement. If the associated lock bit 26x is set, the PMMtJ 20 must also reset this lock bit 26x. In other words: These locked storage locations 24a-24n can only be unlocked for a particular orientation of the processing device 12, while storage locations 24a-24n
At least one of 24n is always unlocked.

Lock warning mechanism is stored here at location 248~2
All but one of the 4n associated lock bits 26a
Although described as being triggered when setting .about.2B+1, the embodiment shown in the figure is triggered when setting
-24n can be modified to generate a lock warning signal when causing the associated lock bits 28a-26n to be set.

Similarly, PMMU 20 may respond to the lock warning signal in other manners without departing from the spirit and scope of the invention.

[Brief explanation of drawings]

The accompanying drawing is a schematic block diagram of a lock warning circuit constructed in accordance with the present invention. 12...Data processing device, 14...Memory, 2
0...Memory-based m+ device with page, 22...Translator cache, 24a-24n...Storage location, 268-26n...Lock bit, 30
a~30n... Inverting buffer, 36... Sense amplifier, 38... Level shifter, 40.50.54.
...Inverter.

Claims (1)

Claims: 1. A plurality of storage locations for operand storage, each storage location having an associated locking indicator adapted to be selectively set and reset; and an associated locking indicator. means for storing an operand in a selected one of said storage locations only if said stored operand is reset, setting said lock indicator in response to a lock signal associated with said stored operand; control means for resetting a lock indicator of said one storage location in response to a signal indicating that said one storage location is to be unlocked; A cache memory comprising: lock warning signal means for generating a lock warning signal when all lock indicators except the indicator are set. 2. In response to said lock warning signal, said control means prohibits setting a lock indicator associated with said one storage location even if a stored operand has said lock signal associated with it; A cache memory according to claim 1.