JPH0746061A - Differential amplifier simiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To equalize in-phase output and anti-phase levels when one side of the input terminal of the differential amplifier semiconductor integrated circuit in a microwave band is used by grounding one side for high-frequency. CONSTITUTION:The source electrode of a first electric filed-effect transistor (hereinafter referred to as FET) F1 and the source electrode of a second FET F2 are connected and constant current source ISS is connected at the connection point. In a differential amplifier circuit where microwave signals are inputted in the gate electrode of the FET F1 and the gate electrode of the FET F2 is grounded for high-frequency, two resistors of RA and RC are series connected as the drain load of the FET F1 and the output is taken out from the center point. Thus, the output level can be equalized in a microwave band.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit formed by using FETs, and particularly to a differential amplifier circuit used in a microwave band.

[0002]

2. Description of the Related Art A conventional differential amplifier circuit includes a first FET (F1) and a second FET (F2) as shown in FIGS.
Source electrode is connected, a constant current source is connected to that electrode, and RD is connected to the drain bias (+ VDD) supply side.
It has a load resistance of 1 = RD2 = RD. This circuit is often used as an unbalance-balance conversion circuit. When a high-frequency signal is input to the gate of F1, the gate of F2 is grounded at a high frequency.
In the area where the phase rotation can be ignored, a balanced output Vo
1, the unbalanced output Vo2 has a reverse phase (180 ° difference).

However, when the FET differential amplifier circuit is used with unbalanced inputs, the transconductance (g
Since m) is small, the amplitude level difference becomes large even in the low frequency region. Furthermore, as the frequency to be handled becomes higher, the phase shifts from 180 ° due to the high frequency characteristics of the FET's gm and pass phase, and the differential The frequency characteristics as amplification deteriorated and the operation up to several hundred MHz was the limit. This conventional case is shown in FIGS.
The operation will be described with mathematical expressions with reference to FIGS. 0-a to 10-c.

FIG. 8 is a circuit diagram of a conventional embodiment when a differential amplifier using FETs is used with an unbalanced input. First, the operation in the low frequency region will be considered. FIG. 9 is an equivalent circuit diagram in the low frequency region where the capacitance is negligible in FIG.

Now, the first FET (F1) and the second FET
The respective outputs Vo1 and Vo2 of (F2) are obtained and their levels are compared.

The relationship between the gate-source voltage of each of these FETs and Vgs1 and Vgs2 is given by the equation 1.2.

Vgs1 = Vi1-RSS (gm * Vgs1 + gm * Vgs2) Vgs2 = -RSS (gm * Vgs1 + gm * Vgs2) Here, considering Vgs1 from (Equation 2), gm * RSS * Vgs1 = -Vgs2-gm * RSS * Vgs2 Therefore, Vgs1 is expressed as in Equation 3.

Vgs1 = − (Vgs2 + gm * RSS * Vgs2) / (gm * RSS) = − (1 + gm * RSS) Vgs2 / (gm * RSS) Here, Vi1 is calculated from one equation: Vi1 = Vgs1 + gm * RSS * Vgs1 + gm *. RSS * Vgs2 = (1 + gm * RSS) Vgs1 + gm * RSS * Vgs2 Substituting (Equation 3) into (Equation 4) Vi1 =-(1 + gm * RSS) ((1 + gm * RSS) * Vgs2 / (gm * RSS)) + gm * RSS * Vgs2 Furthermore, Vi1 / Vgs2 =-(1 + 2gm * RSS) / (gm * RSS) Therefore, the signal output (Vo2) of the second FET is Vo2 =-(gm * RSS / (1 + 2gm * RSS)) * RD. * Gm * Vi1 On the other hand, the signal output (Vo1) of the first FET is: Vgs1 =-(1 + gm * RSS * Vgs2 / (gm * RSS) =-((1 + gm * RSS) * ((-gm * RSS / (1 + 2gm * RSS) * Vi1)) / (gm * RSS) = ((1 + gm * RSS) / (1 + 2gm *) From RSS)) * Vi1, Vo1 = ((1 + gm * RSS) / (1 + 2gm * RSS)) * gm * Vi1 * RD From this, the ratio of Vo1 and Vo2 is calculated from (5) and (6). Vo1 / Vo2 =-((1 + gm * RSS) / gm * RSS) =-(1 + 1 / gm * RSS), and the output of the FET F1 does not have the same level, and the phases differ by 180 °. This is qualitatively because the FET F2 is grounded at the gate and a signal is input from the source electrode and is not in a perfectly balanced state.

Next, the high frequency characteristics of Vo1 and Vod will be considered. When the differential amplifier is used with unbalanced inputs, it is considered that F1 in FIG. 8 operates as a source ground and F2 operates as a gate ground. The high frequency operation of F1 is approximately replaced by a source grounded equivalent circuit as shown in FIG. 10-a.

Since R _GD is much larger than R _DS, it can be omitted, and C _CD can be neglected at about 1/10 of G _GS , so that the high frequency characteristic is as shown in the equivalent circuit of FIG. 10-c. becomes, 1 / Rsh = 1 / R DS + 1 / RD = (RD + R DS) / R DS * RD Csh = Cgs + C DS and an output power Vo1 is, Vo1 = -gm * Vgs / ( 1 / Rsh + jω * Csh) = - gm * Rsh * Vgs / (1 + jω * Rsh * Csh), and the voltage gain is Vo1 / Vgs = Avh = −gm * Rsh / (1 + jω * Rsh * Csh).

Here, the gain Avm at the middle frequency where the influence of the electrostatic capacitance can be neglected can be expressed as Avm = -gm * Rsh since the equivalent circuit can be written as shown in FIG. 10-b. The ratio of the voltage gain Avh is as follows: Avh / Avm = 1 / (1 + jω * Rsh * Cch), and as the frequency increases, the magnitude of the output voltage Vo1 decreases and the phase lags. FIG. 5 shows a calculation example of the frequency characteristic of the output amplitude in the embodiment described above. It can be seen that the levels are not uniform from the low frequency range.
Further, FIG. 6 shows a calculation example of frequency characteristics for the phases of the outputs of F1 and F2. The solid line connecting the + signs is the output phase of F1, the solid line connecting the □ is the output phase of F2, and the phase rotation of F2 operating as the gate ground is the F1 output operating as the source ground. It can be seen that the phase rotation is smaller than the phase rotation, and the higher the frequency, the more it deviates from 180 degrees.

As described above, when the FET differential amplifier circuit is used with an unbalanced input, there is a disadvantage that the difference in amplitude level becomes large because the mutual conductance (gm) of the FETs we use today is small, and the frequency to be handled is high. However, due to the high frequency characteristics of the FET, the frequency characteristics as differential amplification are inferior because of the influence of the phase shift from 180 °, and the operation up to several hundred MHz is limited.

[0013]

In the conventional FET differential amplifier circuit, the drain load resistors RD1 and RD2 are selected to have the same resistance value in order to make the operating points at DC equal. For this reason, there is a problem that the two output levels cannot be made equal to the signal because the gm of the input FET is small.
When the gate width of the FET used to increase gm is increased, the output level unbalance in the low frequency region is improved, but the accompanying increase in the input capacitance between the FET gate and the source increases the frequency characteristic of gm. In the high frequency region such as the microwave band, gm is rather reduced, and the phase difference between the two outputs deviates from 480 °. There was a problem that I could not take it out.

[0014]

A differential amplifier semiconductor integrated circuit according to the present invention comprises a source electrode of a first FET and a second FET.
Differential amplification in which the microwave signal is input to the gate of the first FET and the gate of the second FET is grounded to the high frequency droplet. In the circuit, this problem can be solved by connecting two resistors in series as the drain load of the first FET and extracting the output from the midpoint thereof.

[0015]

1 and 2 are equivalent circuit diagrams of the present invention. The preferred operation of the present invention will be described with reference to these figures.

The source electrodes of the FETs F1 and F2 are connected, and a constant current source is connected to the connection point. A drain load RB is connected to F2, and RA and RC are connected in series as drain loads to F1. The output of F1 is RA and R
Extracted from the connection point (A) of C, the output of F2 is extracted from the connection point of the drain of F2 and RB.

In this case, the signal outputs Vo1 and Vo2 of the first FET (F1) and the second FET (F2) are (5),
From the relationship of the equation (6), Vo2 =-(gm * RSS / (1 + 2gm * RSS)) * RB * gm * Vi1 Vo1 = ((1 + gm * RSS) / (1 + 2gm * RSS)) * gm * Vi1 * RA. . From this, the ratio of Vo1 and Vo2 is Vo1 / Vo2 =-((1 + gm * RSS) / gm * RSS) * RA / RB. Here, Vo1 and Vo2 are at the same level, that is, V
In order to set o1 / Vo2 = -1, RA may be selected so that (1 + gm * RSS) / gm * RSS = RB / RA, and RA = RB * gm * RSS / (1 + gm * RSS). . Substituting the 16th equation into the 13th equation for confirmation, Vo1 = ((1 + gm * RSS) / (1 + 2gm * RSS)) * gm * Vi1 * (RB * gm * RSS / (1 + gm * RSS) = (gm * rss / (1 + 2gm * RSS)) * RB * gm * Vi1 = -Vo2 is obtained, which makes it possible to make the output levels (Vo1, Vo2) the same and RB = RA +
By setting RC, the DC bias point (operating point) on the drain side of the FET can be made the same for F1 and F2.

Further, the characteristic in the high frequency region is that by selecting RA as the drain load, the conventional load resistance RD = RB.
R = RB-RC, and Rs of 8
In the relational expression (Equation 11) of the voltage gain in the low frequency region and the high frequency region, the value of h becomes small. Avh / Avm = 1 / (1 + jω * Rsh * Csh) When Rsh becomes small, the decrease amount of Vo1 in the high frequency region becomes It becomes smaller and the phase delay is improved as well. As a result, the deviation from the phase difference of 180 ° in the high frequency region is also improved.

FIG. 3 shows 6 GHz when the present invention is implemented.
The amplitude / phase difference vs. resistance value variation characteristics at are shown. Vo1
The output levels of Vo and Vo2 can be made equal by selecting the resistance values of RA and RC. At this time, it is understood that the phase difference from 180 degrees can also be reduced.

In the present invention, only the gain for the signal is changed between F1 and F2, the DC operating point is set equal, and V
_{Since the DS} (drain-source voltage) is the same, it is stable against changes in current such as temperature characteristics.

FIG. 4 shows an example of frequency characteristics of output amplitude when the present invention is carried out. It can be seen that the output levels are aligned from the low frequency range. Further, FIG. 5 shows the difference between the frequency characteristics of the phase characteristics and the conventional example. The solid line connecting the ◯ marks is the output phase of F1 in this embodiment, and the phase difference from the solid line connecting the □ marks showing the output phase of the FD is greater than that of the conventional example shown by the solid line connecting the + marks. You can see that it is improved in the high range.

The above invention can be applied to the case where the input format is two inputs.

FIG. 6 shows a circuit diagram of the second embodiment. The output is taken out from the connection points (A, B) of the drain loads RA and RC and RB and RD, which are connected in series, and when the drain loads RA and RB are changed while maintaining the relationship of RC + RC = RB + RD. There is an advantage that the level can be easily adjusted.

[0024]

As described above, according to the present invention, it is possible to equalize the output levels by connecting two series resistors to the output side load of the differential amplification semiconductor integrated circuit and taking out the output from the midpoint thereof. Value is very high.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an embodiment of a differential amplification semiconductor integrated circuit.

FIG. 2 is an equivalent circuit diagram of an embodiment of a differential amplification semiconductor integrated circuit.

FIG. 3 shows amplitude / phase difference vs. resistance variation characteristics of the embodiment.

FIG. 4 shows amplitude-frequency characteristics of the embodiment.

FIG. 5 shows amplitude-frequency characteristics of a conventional circuit.

FIG. 6 is a comparison of the phase-versus-frequency characteristics of the conventional example and the example of the present invention.

FIG. 7 is an equivalent circuit in the case of the embodiment (F1 and F2 balanced input).

FIG. 8 is an equivalent circuit of a conventional differential amplification semiconductor integrated circuit.

FIG. 9 is an equivalent circuit of a differential amplification semiconductor integrated circuit.

FIG. 10 is an equivalent circuit of a conventional FET semiconductor integrated circuit.

[Explanation of symbols]

F1, F2 FET RA, RB, RC. RD, RSS Load resistance Vi1 Input signal Vo1, Vo2 Output signal Iss Constant current source V _DD , V _SS DC power supply A, B Intermediate point gm Transconductance Vgs1, Vgs2 Gate-source voltage G1 Gate D1, D2 Drain S1, S2 source Rg Gate resistance R _GD Gate-drain resistance R _DS Gate-source resistance Cgs Gate-source capacitance C _GD Gate-drain-in capacitance G _DS Drain-source capacitance

Front Page Continuation (72) Inventor Toshiyuki Nagai 3-20-4 Nishishimbashi, Minato-ku, Tokyo Nidec Engineering Co., Ltd.

Claims (1)

[Claims] 1. A first field effect transistor (hereinafter FE)
The source electrode of T) is connected to the source electrode of the second FET, and a constant current source (current source) is connected to the source electrode of
High-frequency signal is input to the gate of the FET of the
In a semiconductor integrated circuit that constitutes a differential amplifier circuit in which the gate of T is grounded at high frequency, two resistors are connected in series as the drain load of the first FET, and the sum of the resistance values of the two FETs is the second FET. Equal to the resistance value connected to the drain of, and its connection point and the second FE
A differential amplification semiconductor integrated circuit, wherein an output is taken out from a drain electrode of T.