JPH0745828A - Insulated-gate field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a concentration gradient of an impurity in a depth direction by stepwisely varying a source region and a drain region from a high impurity concentration region to a low impurity concentration region in the depth direction by altering an implanting depth of ions. CONSTITUTION:A P-type well 302, an element isolation region 307, an element forming region, a thermal oxide film 303 and a gate electrode 305 are sequentially formed on a silicon substrate 301. then, with the electrode 305 as a mask arsenic is ion implanted under conditions of 5E14cm<-2>, 500keV to form a low concentration region N<-> type layer 306. Thereafter, after a silicon dioxide is deposited, an entire surface is etched, and the silicon dioxide 308 remains only on a sidewall of the electrode 305. Then, with the electrode 305 and the silicon 308 are masks arsenic is ion implanted under conditions of 5E15cm<-2>, 35keV to form a high concentration region 309, and then the impurity is activated by using a quick heat processing method. Thus, a profile of the impurity can be redistributed in a shallow depth, and a profile having a small concentration gradient of the impurity to a depth direction can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an insulated gate field effect transistor and a method of manufacturing the same, and is particularly resistant to the short channel effect and has a small junction capacitance between a source region and a drain region. The present invention relates to a structure of an effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art A MOS FET, which is a typical example of an insulated gate field effect transistor, will be described below. Figure 1
Shows three typical structures of MOS FET,
In the figure, (a) is an SD (Single Drain) M
Structure of OS FET, (b) LDD (Lightl)
y Doped Drain) MOS FET structure, and (c) is GDD (Graded Doped).
Drain) This is the structure of the MOSFET. SD is the first invented structure. After that, as the device becomes finer, the reliability of Nch MOS FET is deteriorated due to hot carriers, and LDD was devised.

The manufacturing characteristic of the LDD shown in FIG. 1B is that after the gate electrode 101 is formed, an N ⁻ layer 102 having a low impurity concentration is formed in the source / drain regions, and a mask is used for impurity ion implantation. After forming the oxide film 103 to be formed on both sides of the gate electrode, the N ⁺ layer 104 having a high impurity concentration is formed in the source / drain regions. N ^-
The layer 102 relaxes the electric field to improve reliability with respect to hot carriers.

Further, the structural feature of the GDD shown in FIG. 1C is that the N ⁻ layer 106 is formed so as to surround the entire N ⁺ layer 105 in the source / drain regions. The reliability against hot carriers is improved, and the N ⁻ layer has the effect of increasing the withstand voltage of the entire junction between the source / drain regions. The manufacturing feature is N first
^- After the impurity serving as the layer ion implantation, in addition to heat treatment, widened the area is to heat treatment again impurities then a N ⁺ layer by ion implantation.

From the standpoint of high breakdown voltage and high reliability, the structure and manufacturing method of the LDD and GDD could be used, but the miniaturization of the MOS FET has progressed and the gate length is 0.5 μm.
When it is less than m, the influence of the short channel effect becomes remarkable in addition to the above problem. There are two methods for suppressing the short channel effect: (1) increasing the impurity concentration in the well and (2) thinning the impurity layer in the source / drain regions. MOS with a gate length of 0.5 μm or less in the structure of the LDD and GDD described above
In the FET, it is difficult for GDD to thin the impurity layer in the source / drain regions. Therefore, attempts have been made to reduce the short channel effect while maintaining high reliability by applying the above-mentioned two means for suppressing the short channel effect to the LDD structure.

[0006]

However, increasing the impurity concentration of the well increases the NP junction capacitance between the N ⁺ layer in the source / drain region and the P-type well, which results in a high speed device. There is a problem that it becomes an obstacle. On the other hand, one of the specific manufacturing methods for thinning the impurity layers in the source / drain regions is a rapid thermal heating method, which has been studied in recent years. This is a method of preventing the redistribution of impurities and thinning the impurity layer by performing activation after the impurity ion implantation in a short time. FIG. 2 shows an impurity depth profile 201 after activation by a conventional electric furnace and an impurity depth profile 202 after activation by a lamp annealing method which is an example of a rapid thermal heating method. As shown in FIG. 2, in the lamp annealing method, the depth of penetration of impurities is certainly small, but
It can be seen that the concentration gradient in the depth direction increases conversely. This causes an increase in the N--P junction capacitance between the N.sup. ⁺ Layer in the source / drain region and the P-type well, and there is a problem that the increase in the concentration of the well hinders the speedup of the device.

An object of the present invention is to solve the above-mentioned problems, and the purpose thereof is to provide a structure of an insulated gate field effect transistor which is not easily affected by the short channel effect and has a small junction capacitance of the source / drain regions, and its structure. It is to provide a manufacturing method.

[0008]

According to the present invention, in order to achieve the above object, in the step of forming the source region and the drain region, the step of ion-implanting the impurities for forming the source / drain regions is divided into two steps. We devised a method to reduce the concentration gradient in the depth direction in the source / drain regions. That is, a manufacturing method has been devised which includes a second step of ion-implanting impurities into the source / drain regions in a shallower manner than the first step, in addition to the first step of ion-implanting impurities into the source / drain regions as in the prior art. Further, in addition to the above-mentioned impurity ion implantation step, a step of performing a heat treatment by a rapid thermal heating method after the first and second steps in order to suppress redistribution of the implanted impurities and keep the impurity layer thin Devised a method.

That is, according to the second aspect of the invention, the second conductivity type source and drain regions are formed on the surface of the first conductivity type semiconductor substrate with the channel region interposed therebetween.
And a method of manufacturing an insulated gate field effect transistor having a gate electrode formed on the channel region via an insulating film, wherein an impurity is ion-implanted as a step of forming the second conductivity type source region and drain region. Forming a high-impurity region and a low-impurity region in the depth direction of the source region and the drain region, including a first step of performing the ion implantation and a second step of implanting ions shallower than the first step. Characterize.

Further, the invention according to claim 2 is characterized in that, in the manufacturing method, after the first step and the second step of ion implantation, a heat treatment is performed by using a rapid thermal heating method. .

The invention according to claim 3 is the first aspect.
An insulated gate having a second conductivity type source region and a drain region formed across a channel region on the surface of a conductivity type semiconductor substrate, and a gate electrode formed on the channel region via an insulating film. Type field effect transistor, including a first step of ion-implanting an impurity and a second step of ion-implanting shallower than the first step as a step of forming the source region and the drain region of the second conductivity type, A high impurity region and a low impurity region are formed in the depth direction of the source region and the drain region, or a rapid thermal heating method is performed after the first step and the second step of the ion implantation. It is characterized in that it includes a step of heat treatment using.

[0012]

In other words, according to the present invention, the source / drain regions are ion-implanted with impurities by changing the ion implantation depth in the first step and the second step.
The drain region is gradually changed from the high impurity concentration region to the low impurity concentration region in the depth direction to reduce the concentration gradient of the impurities in the depth direction. In addition, after the first and second steps, heat treatment is performed by a rapid thermal heating method such as a lamp annealing method to suppress redistribution of the implanted impurities and keep the impurity layer thin.

[0013]

The present invention will be described in more detail with reference to the examples shown in the drawings. Here, an LDD MOS FET, which is one of the insulated gate field effect transistors, will be described as an example. FIG. 3 shows an LDD MOS F according to the present invention.
It is the schematic which shows the manufacturing method of ET, and especially (c) shows the structure at the time of completion. The manufacturing method according to the present invention will be described below in the order of FIGS.

(A) Boron is ion-implanted into the silicon substrate 301, and then a heat treatment is performed to redistribute the implanted boron so that the P-type well 302 has a concentration of 1 × 10 ¹⁷ cm ^-3.
To form. Next, the element isolation region 30 is formed by the LOCOS method.
7 and the element formation region are formed, and 1 is formed on the surface of the element formation region.
A thermal oxide film 303 having a thickness of 00 angstrom is formed. Phosphorus-doped polysilicon is deposited on the thermal oxide film 303 to a thickness of 3500 angstroms, and a gate electrode 305 is formed on a portion to be a channel region 304 by a photolithography etching technique. Then the gate electrode 30
5 as a mask, arsenic 5E14cm ^-2 , 50 KeV
Ion-implanted under the conditions of the low concentration region N ⁻ layer 306 of impurities
To form.

(B) 150 silicon dioxide by CVD method
After 0 angstrom deposition, the entire surface is etched to leave the silicon dioxide 308 only on the side wall of the gate electrode 305. Here, the gate electrode 305 and the silicon dioxide 3
08 as a mask, arsenic was again added to 5E15 cm ^-2 , 35
Ion implantation is performed under the condition of KeV to form a high concentration region N ⁺ layer 309 of impurities.

(C) The impurities are activated by using a rapid thermal heating method (for example, a lamp annealing furnace) under conditions of 1000 ° C. and 20 seconds. As a result, where activation of a conventional electric furnace causes the impurity profile to be redistributed deeply as indicated by 201 in FIG. 2, it can be redistributed shallowly as indicated by 401 in FIG. Further, since the source / drain region is formed from two regions of N ⁺ 309 and N ^- 306 having different concentrations, the concentration gradient in the depth direction of the impurity is smaller than in the conventional case where only N ⁺ 309 is formed. Profile can be realized. Next, silicon dioxide 310 serving as an interlayer insulating film is deposited to 5000 angstroms by the CVD method, and contact holes 311 are formed above the source / drain regions by the photolithography etching technique. Finally, Al is deposited to 6000 angstrom and patterned by photolithography etching technique to form an electrode 312.

The LDD MOS intended in the above steps
The FET is completed. Although the present embodiment has been described with reference to LDD, the present invention can be applied to SD. Further, although Nch is taken as an example, it can be similarly applied to Pch.

[0018]

As described above, according to the present invention, in the step of forming the source and drain regions of the second conductivity type, by changing the implantation depth of the impurities in the first and second steps, the impurities can be changed. The concentration gradient in the depth direction of can be reduced. Furthermore, according to the present invention, by performing heat treatment using the rapid thermal heating method after the above steps, it is possible to keep the impurity layer thin and activate the impurities without changing the concentration gradient thereof. As a result of the above, according to the present invention, it is possible to provide an insulated gate field effect transistor which is not easily affected by the short channel effect and has a small junction capacitance in the source / drain regions.

[Brief description of drawings]

FIG. 1A is a sectional view showing a structure of an SDD MOS FET. (B) is a sectional view showing a structure of an LDD MOS FET. (C) is a GDD MOS F
It is a sectional view showing a structure of ET 1.

FIG. 2 is a comparison diagram of impurity concentration curves in a source / drain region in the case of heating by an electric furnace and the case of rapid thermal heating.

3A to 3C are LDD MOs according to the present invention.
It is sectional drawing which shows the structure in the manufacturing process of SFET.

FIG. 4 is an impurity concentration curve diagram in the source / drain regions in the case of the manufacturing method of the present invention.

[Explanation of symbols]

101 Gate Electrode 102 N ^- Layer 103 Si Oxide Film 104 N ⁺ Layer 105 N ⁺ Layer 106 N ^- Layer 201 Impurity Concentration Curve after Heating by Electric Furnace 202 Impurity Concentration Curve after Heating by Rapid Thermal Heating 301 Si Substrate 302 P-Type Well 303 Thermal oxide film 304 Channel region 305 Gate electrode 306 N ⁻ layer 307 Element isolation region 308 SiO ₂ 309 N ⁺ layer 310 SiO ₂ 311 serving as an interlayer insulating film 312 Contact electrode 312 Al electrode

Claims (3)

[Claims] 1. A source / drain region of a second conductivity type formed with a channel region on a surface of a semiconductor substrate of a first conductivity type, and an insulating film formed on the channel region. In a method of manufacturing an insulated gate field effect transistor having a gate electrode, a first step of implanting impurities as a step of forming the second conductivity type source region and a drain region, and an ion shallower than the first step. A method of manufacturing an insulated gate field effect transistor, comprising a second step of implanting, and forming a high impurity region and a low impurity region in a depth direction of the source region and the drain region. 2. The insulated gate electric field according to claim 1, further comprising a step of performing heat treatment using a rapid thermal heating method after the first step and the second step of ion implantation. Effect transistor manufacturing method. 3. A source / drain region of a second conductivity type formed on the surface of a semiconductor substrate of the first conductivity type with a channel region interposed therebetween, and formed on the channel region with an insulating film interposed therebetween. In an insulated gate field effect transistor having a gate electrode, a first step of ion-implanting an impurity and a step of ion-implanting shallower than the first step as a step of forming the source region and the drain region of the second conductivity type. Characterized by including the step 2 and forming a high impurity region and a low impurity region in the depth direction of the source region and the drain region, or the first step and the second step of the ion implantation. An insulated gate field effect transistor, characterized by including a step of performing a heat treatment using a rapid thermal heating method after.