JPH0745786A - Composite integrated circuit parts - Google Patents

Composite integrated circuit parts

Info

Publication number
JPH0745786A
JPH0745786A JP5191299A JP19129993A JPH0745786A JP H0745786 A JPH0745786 A JP H0745786A JP 5191299 A JP5191299 A JP 5191299A JP 19129993 A JP19129993 A JP 19129993A JP H0745786 A JPH0745786 A JP H0745786A
Authority
JP
Japan
Prior art keywords
integrated circuit
ceramic substrate
film
thin film
composite integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5191299A
Other languages
Japanese (ja)
Inventor
Michio Arai
三千男 荒井
Katsuto Nagano
克人 長野
Yukio Yamauchi
幸夫 山内
Naoya Sakamoto
直哉 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
TDK Corp
Original Assignee
Semiconductor Energy Laboratory Co Ltd
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd, TDK Corp filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP5191299A priority Critical patent/JPH0745786A/en
Priority to US08/242,813 priority patent/US5643804A/en
Priority to KR1019940011146A priority patent/KR100273826B1/en
Publication of JPH0745786A publication Critical patent/JPH0745786A/en
Priority to US08/812,453 priority patent/US5877533A/en
Priority to US09/226,215 priority patent/US6410960B1/en
Priority to KR1019990046276A priority patent/KR100311675B1/en
Priority to KR1020010009793A priority patent/KR100351399B1/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Formation Of Insulating Films (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To provide a composite integrated circuit parts wherein a ceramic substrate is used and a thin-film integrated circuit element having a good characteristic is obtained. CONSTITUTION:In a composite integrated circuit part, on a ceramic substrate 101 whereon a thin-film integrated circuit 103 is formed, a layered type capacitor 106, a layered type inductor 107 and resistors are provided respectively, or a layered body composed of the capacitor 106, the inductor 107 and the resistors is provided. In this composite integrated circuit part, a glass layer 102 having a silicon oxide as its main component is formed in between the ceramic substrate 101 and the thin-film integrated circuit 103, and thereby, the irregularity of the surface of the ceramic substrate 101 is made flat.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は複合集積回路部品に係
り、特に薄膜集積回路を形成したセラミック基板上に、
受動素子回路を構成する積層体を形成した複合集積回路
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite integrated circuit component, and more particularly to a ceramic substrate having a thin film integrated circuit formed thereon.
The present invention relates to a composite integrated circuit in which a laminated body forming a passive element circuit is formed.

【0002】[0002]

【従来の技術】薄膜集積回路を形成した基板と積層法に
より形成された積層型コンデンサや積層型インダクタ又
は抵抗あるいはこれらの混成部品を組合わせた構造の複
合集積回路部品は従来より知られている。
2. Description of the Related Art A composite integrated circuit component having a structure in which a substrate on which a thin film integrated circuit is formed and a multilayer capacitor, a multilayer inductor or a resistor formed by a lamination method, or a hybrid component thereof is combined has been conventionally known. .

【0003】積層法による積層型コンデンサは一般に、
誘電体の原料粉末とバインダーを混ぜてペースト化した
ものを、容易に剥離できる仮支持基板上にシート状に印
刷する。次にこの上に電極用導体材料ペーストを積層印
刷し、これを交互に積層印刷して積層体を形成する。次
にこの積層体の上に、同様にして磁性材料と導体材料ペ
ーストを積層印刷してインダクタンス部分を積層する。
それからこの積層体を乾燥させた後、仮支持板からの積
層体を、例えば800℃〜950℃位の高温度で焼成し
て剥離し、インダクタ、コンデンサ、抵抗を含む回路素
子を形成した積層体を得る。
Multilayer capacitors by the lamination method are generally
The raw material powder of the dielectric and the binder are mixed to form a paste, which is printed in a sheet shape on a temporary supporting substrate that can be easily peeled off. Next, an electrode conductor material paste is laminated and printed thereon, and this is alternately laminated and printed to form a laminate. Next, a magnetic material and a conductor material paste are similarly laminated and printed on the laminated body to laminate the inductance portion.
Then, after the laminated body is dried, the laminated body from the temporary support plate is baked at a high temperature of, for example, about 800 ° C. to 950 ° C. and peeled off to form a circuit element including an inductor, a capacitor, and a resistor. To get

【0004】図6に、このように形成された積層体と集
積回路チップを組合わせた複合集積回路を示す。図6に
おいて、積層型インダクタ61、積層型コンデンサ6
2、抵抗体63と導体68から成る抵抗回路などで構成
される積層体64上に金属膜67を介して、ベアの集積
回路チップ65を搭載し、この集積回路チップ65の取
り出し端子と、積層体64の電極パット66とをワイヤ
ボンディングで接続後、プラスチックあるいはセラミッ
クなどでパッケージ69を形成して複合集積回路部品と
している。
FIG. 6 shows a composite integrated circuit in which the laminated body thus formed and an integrated circuit chip are combined. In FIG. 6, a multilayer inductor 61 and a multilayer capacitor 6
2. A bare integrated circuit chip 65 is mounted on a laminated body 64 composed of a resistance circuit composed of a resistor 63 and a conductor 68 with a metal film 67 interposed therebetween. After connecting the electrode pad 66 of the body 64 by wire bonding, a package 69 is formed of plastic or ceramic to form a composite integrated circuit component.

【0005】ところがこのような複合回路部品では、仮
支持基板上に積層体を積層に印刷した後、この仮支持基
板を除去するなど、煩雑な工程が必要である。このよう
な不都合をなくすために、薄膜集積回路を形成した基板
上に積層型のコンデンサ、積層型のインダクタあるいは
抵抗又はこれらを組合わせた積層体を形成することも試
みられている。
However, such a composite circuit component requires complicated steps such as printing the laminate on the temporary supporting substrate in a laminated manner and then removing the temporary supporting substrate. In order to eliminate such inconvenience, it has been attempted to form a laminated capacitor, a laminated inductor or a resistor, or a laminated body combining these on a substrate on which a thin film integrated circuit is formed.

【0006】[0006]

【発明が解決しようとする課題】前記の構成の複合集積
回路部品の薄膜集積回路を形成する基板として、安価に
入手できるセラミック基板を使用することがある。とこ
ろがセラミック基板表面には凹凸があるため、ダイレク
トに薄膜集積回路素子形成用の半導体層を形成すると、
セラミック基板表面の凹凸が、該半導体層表面に影響
し、例えば半導体素子のチャネル長が変化して回路素子
の特性を損なうという問題点がある。
As a substrate for forming a thin film integrated circuit of the composite integrated circuit component having the above-mentioned structure, a ceramic substrate which can be obtained at low cost may be used. However, since the surface of the ceramic substrate has irregularities, when a semiconductor layer for forming a thin film integrated circuit element is directly formed,
The unevenness of the surface of the ceramic substrate affects the surface of the semiconductor layer, and there is a problem that the channel length of the semiconductor element is changed and the characteristics of the circuit element are impaired.

【0007】従って本発明の目的は薄膜集積回路を形成
する基板としてセラミック基板を用いて特性の良好な、
安価でコンパクトな複合集積回路部品を提供することで
ある。
Therefore, an object of the present invention is to use a ceramic substrate as a substrate for forming a thin film integrated circuit, which has good characteristics.
An object is to provide an inexpensive and compact composite integrated circuit component.

【0008】[0008]

【課題を解決するための手段】本発明は前記問題点を解
決するために、薄膜集積回路を形成したセラミック基板
上に、積層型コンデンサ、積層型インダクタあるいは抵
抗あるいはこれらを複合した積層体を設けた複合集積回
路部品において、薄膜集積回路を形成するセラミック基
板の表面に酸化シリコンを主成分とするガラス層を形成
して、基板表面の凹凸を平坦化してから薄膜集積回路素
子を形成するものである。
In order to solve the above-mentioned problems, the present invention provides a multilayer capacitor, a multilayer inductor or a resistor or a multilayer body combining these on a ceramic substrate on which a thin film integrated circuit is formed. In a composite integrated circuit component, a thin film integrated circuit element is formed by forming a glass layer containing silicon oxide as a main component on the surface of a ceramic substrate forming a thin film integrated circuit and flattening the unevenness of the substrate surface. is there.

【0009】なお、前記セラミック基板と前記ガラス層
の間に熱伝導のよい高融点金属又はそのシリサイドから
成る放熱層を設けることもできる。
A heat-dissipating layer made of a refractory metal having good heat conductivity or a silicide thereof may be provided between the ceramic substrate and the glass layer.

【0010】[0010]

【作用】本発明の構成にすることにより、セラミック基
板の表面の凹凸がその後半導体プロセスに十分耐える、
耐熱性のあるガラス材料層によって平坦化することが出
来、該基板上にチャネル長が短く揃った特性のよい回路
素子を形成することができる。
With the structure of the present invention, the unevenness of the surface of the ceramic substrate can sufficiently withstand the subsequent semiconductor process,
The heat-resistant glass material layer can be used for flattening, and a circuit element having a short channel length and good characteristics can be formed on the substrate.

【0011】[0011]

【実施例】本発明の実施例を図1〜図5によって説明す
る。図1は本発明の一実施例の概略構成図である。
Embodiments of the present invention will be described with reference to FIGS. FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

【0012】図1において、100は混成集積回路部
品、101はセラミック基板、102はフォスフォシリ
ケートグラス(PSG)膜、103は薄膜トランジスタ
(TFT)等の形成された薄膜集積回路、104はパッ
ト電極、105は層間絶縁膜、106は積層型コンデン
サ、107は積層型インダクタ、108は電極、109
は取り出し電極を示す。
In FIG. 1, 100 is a hybrid integrated circuit component, 101 is a ceramic substrate, 102 is a phosphosilicate glass (PSG) film, 103 is a thin film integrated circuit formed with a thin film transistor (TFT), 104 is a pad electrode, 105 is an interlayer insulating film, 106 is a multilayer capacitor, 107 is a multilayer inductor, 108 is an electrode, 109
Indicates an extraction electrode.

【0013】図1に示す混成集積回路部品100のセラ
ミック基板101の表面は耐熱性のあるSiO2 を主成
分とする、例えばPSG膜102でコーティングされて
いる。このPSG膜102はセラミック基板の表面の凹
凸を平坦化するだけの厚さがある。このPSG膜102
は、その後、半導体プロセスを850℃以上の温度で行
うため、これに耐え得るようにSiO2 膜を主成分とす
るガラス膜から成る。
The surface of the ceramic substrate 101 of the hybrid integrated circuit component 100 shown in FIG. 1 is coated with, for example, a PSG film 102 whose main component is heat resistant SiO 2 . The PSG film 102 is thick enough to flatten the irregularities on the surface of the ceramic substrate. This PSG film 102
After that, since the semiconductor process is performed at a temperature of 850 ° C. or higher, it is composed of a glass film containing a SiO 2 film as a main component so as to withstand this.

【0014】また、セラミック基板101の放熱を良好
にするためにこのPSG膜102は10μm以下にする
ことが望ましい。本発明のPSG膜102で平坦化され
たセラミック基板101上にTFT等の薄膜集積回路を
形成されたものの上に、層間絶縁膜105を介して積層
型コンデンサ106、積層型インダクタ107から成る
積層体が形成されている。
Further, in order to improve heat dissipation of the ceramic substrate 101, it is desirable that the PSG film 102 has a thickness of 10 μm or less. A laminated body composed of a multilayer capacitor 106 and a laminated inductor 107 with an inter-layer insulating film 105 on a thin film integrated circuit such as a TFT formed on a ceramic substrate 101 flattened with a PSG film 102 of the present invention. Are formed.

【0015】図2は本発明の実施例で用いられる薄膜集
積回路に用いられるTFTの概略説明図、図3〜図4は
このTFTの製造工程説明図である。図2〜図4におい
て、101はアルミナ等のセラミック基板、102は本
発明の酸化シリコンを主成分とするガラス層で、例えば
PSG膜、203はTFT等の素子を形成する活性シリ
コン膜、204はゲート絶縁膜、205はゲート電極、
206、207はソース・ドレイン領域、208はPS
G膜、209はドープドシリコン電極層を示す。
FIG. 2 is a schematic explanatory view of a TFT used in a thin film integrated circuit used in an embodiment of the present invention, and FIGS. 3 to 4 are explanatory views of a manufacturing process of this TFT. 2 to 4, 101 is a ceramic substrate such as alumina, 102 is a glass layer containing silicon oxide as a main component of the present invention, for example, a PSG film, 203 is an active silicon film forming an element such as TFT, and 204 is A gate insulating film, 205 a gate electrode,
206 and 207 are source / drain regions, 208 is PS
G film, 209 indicates a doped silicon electrode layer.

【0016】図2ではセラミック基板101上に酸化シ
リコンを主成分とするガラス層102が形成されてセラ
ミック基板の表面が平坦化された上に、TFTが形成さ
れている。
In FIG. 2, a glass layer 102 containing silicon oxide as a main component is formed on a ceramic substrate 101 to flatten the surface of the ceramic substrate and then a TFT is formed.

【0017】図3、図4はこのTFTの製造工程説明図
である。まずアルミナから成るセラミック基板101の
表面にトリエトキシリンP(OC2 5 3 とテトラエ
トキシシランSi(OC2 5 4 をスピンコートし、
950℃で酸素雰囲気中で5時間アニールする。これに
より酸化シリコンを主成分とするガラス層102として
の、5μmの厚さのPSG膜から成るリフロー膜を得る
(図3(A)参照)。
3 and 4 are explanatory views of the manufacturing process of this TFT. First, triethoxyphosphorus P (OC 2 H 5 ) 3 and tetraethoxysilane Si (OC 2 H 5 ) 4 are spin-coated on the surface of a ceramic substrate 101 made of alumina,
Anneal at 950 ° C. in oxygen atmosphere for 5 hours. Thus, a reflow film made of a PSG film having a thickness of 5 μm is obtained as the glass layer 102 containing silicon oxide as a main component (see FIG. 3A).

【0018】ここで、セラミック基板表面の凹凸を平坦
化するための膜として、本実施例の如くSiO2 を主成
分とするガラスを用いるのは、その後のTFTを形成す
るための半導体プロセスを850℃以上で行うので、こ
れに十分耐えるための耐熱性を有することと、熱膨張係
数が両者と大きく相違しないことによる。
Here, as the film for flattening the irregularities on the surface of the ceramic substrate, the glass containing SiO 2 as the main component is used as in the present embodiment, and the semiconductor process for forming the subsequent TFT is 850. Since it is performed at a temperature of not less than 0 ° C., it has heat resistance enough to withstand this, and the coefficient of thermal expansion is not so different from both.

【0019】また、このPSG膜が蓄熱しないように1
0μm以下の厚さにすることが望ましい。これにより放
熱のよい安価な基板を得ることができる。次にこのPS
G膜102上にアモルファスシリコン(α−Si)膜2
03’を減圧CVD法により500〜6000Åの厚さ
に形成する(図3(B)参照)。
Also, to prevent the PSG film from accumulating heat, 1
It is desirable to set the thickness to 0 μm or less. This makes it possible to obtain an inexpensive substrate with good heat dissipation. Next this PS
Amorphous silicon (α-Si) film 2 on the G film 102
03 'is formed to a thickness of 500 to 6000Å by the low pressure CVD method (see FIG. 3 (B)).

【0020】この時の成膜条件は以下の通りである。 Si2 6 100〜500 SCCM He 500 SCCM 反応圧力 0.1〜1 Torr 成膜温度 430〜500℃ 次にこのα−Si膜203’を所定のアイランド状にパ
ターニングした後、約600℃の温度で約40時間、窒
素雰囲気中で熱処理し結晶化し、活性シリコン膜203
を得る(図3(C)参照)。
The film forming conditions at this time are as follows. Si 2 H 6 100 to 500 SCCM He 500 SCCM Reaction pressure 0.1 to 1 Torr Film formation temperature 430 to 500 ° C. Next, after patterning this α-Si film 203 ′ into a predetermined island shape, a temperature of about 600 ° C. And heat treatment in a nitrogen atmosphere for about 40 hours to crystallize the active silicon film 203.
Is obtained (see FIG. 3 (C)).

【0021】次にゲート絶縁膜を形成するために、ドラ
イ酸化により、500〜2000Åの膜厚の酸化シリコ
ン膜204’を形成する(図3(D)参照)。ゲート絶
縁膜の形成条件は以下の通りである。
Next, in order to form a gate insulating film, a silicon oxide film 204 'having a film thickness of 500 to 2000 Å is formed by dry oxidation (see FIG. 3D). The conditions for forming the gate insulating film are as follows.

【0022】 O2 2.5 SLM 反応温度 850〜1100℃ 次にこの上にゲート電極となるP又はBをドープしたシ
リコン膜205’を減圧CVD法により、1000〜4
000Åの膜厚で形成する(図3(E)参照)。
O 2 2.5 SLM Reaction temperature 850 to 1100 ° C. Next, a P or B-doped silicon film 205 ′ serving as a gate electrode is formed on this by a low pressure CVD method to 1000 to 4
It is formed with a film thickness of 000Å (see FIG. 3 (E)).

【0023】この後、所定のパターンに従って、エッチ
ング工程を行い、ゲート絶縁膜204、ゲート電極20
5を形成する(図3(F)参照)。このゲート電極20
5をマスクとして、ソース・ドレイン領域となるべき部
分にイオンドーピング法により、例えばPをドープして
n型のソース・ドレイン領域206、207を形成する
(図4(A)参照)。
After that, an etching process is performed according to a predetermined pattern to form the gate insulating film 204 and the gate electrode 20.
5 is formed (see FIG. 3 (F)). This gate electrode 20
Using the mask 5 as a mask, the portions to be the source / drain regions are doped with, for example, P by ion doping to form n-type source / drain regions 206 and 207 (see FIG. 4A).

【0024】この時、セラミック基板101の表面が酸
化シリコンを主成分とするガラス層102により平坦化
されているため、活性シリコン層203もその表面が平
坦なものが得られる。これに形成されるTFTのチャネ
ル長Lも10μm以下に制御することが出来る。従っ
て、周波数特性の良い素子を得ることが出来るので、集
積回路を設計する場合に回路の応用範囲の広いものを得
ることが出来る。
At this time, since the surface of the ceramic substrate 101 is flattened by the glass layer 102 containing silicon oxide as a main component, the active silicon layer 203 also has a flat surface. The channel length L of the TFT formed in this can also be controlled to 10 μm or less. Therefore, it is possible to obtain an element having good frequency characteristics, so that a wide range of circuit applications can be obtained when designing an integrated circuit.

【0025】次にこれらの基板全体を窒素雰囲気で60
0℃12時間加熱しドーパントの活性化を行う。この
後、常圧CVD法で層間絶縁膜としてPSG膜208を
4000〜8000Åの膜厚で形成し、電極形成のため
の必要なパターンに従ってPSG膜208のパターニン
グを行い、開孔を形成する(図4(B)参照)。
Next, the whole of these substrates is subjected to 60 in a nitrogen atmosphere.
The dopant is activated by heating at 0 ° C. for 12 hours. After that, a PSG film 208 is formed as an interlayer insulating film with a film thickness of 4000 to 8000Å by an atmospheric pressure CVD method, and the PSG film 208 is patterned according to a necessary pattern for forming an electrode to form an opening (see FIG. 4 (B)).

【0026】次に電極用の第二のドープドシリコン電極
層209を形成して、図2のようなTFTを得る。薄膜
集積回路として構成する場合には、この後に保護膜を兼
ねた図1のPSG膜の如き層間絶縁膜105をチップオ
ンガラス法でスピンコートし、この後電極用のスルーホ
ールを形成し、これに接続用の電極をパターニングし
て、同様に形成した他の回路素子と接続する。
Next, a second doped silicon electrode layer 209 for electrodes is formed to obtain a TFT as shown in FIG. In the case of forming a thin film integrated circuit, an interlayer insulating film 105 such as the PSG film of FIG. 1 which also serves as a protective film is spin-coated by a chip-on-glass method after this, through holes for electrodes are formed, and Then, the connection electrode is patterned to be connected to another circuit element similarly formed.

【0027】なおこの層間絶縁膜105は、シリコンア
ルコキシド、リンアルコキシドを適宜の厚さに形成しこ
れを焼成して得ることもできる。他の手法例えばCVD
法により形成することもできる。
The interlayer insulating film 105 can also be obtained by forming silicon alkoxide or phosphorus alkoxide in an appropriate thickness and firing it. Other techniques such as CVD
It can also be formed by a method.

【0028】また、薄膜集積回路を構成する上で、さら
に別の配線が必要な場合には、同様に層間絶縁膜とドー
プドシリコン膜を積層して多層配線を形成する。次にこ
の薄膜集積回路が形成された基板101上に印刷法を使
用して受動素子を構成する積層体を設ける。積層体とし
て、積層型インダクタを形成する場合の概略工程図を図
5に示す。
Further, when another wiring is required in constructing the thin film integrated circuit, an interlayer insulating film and a doped silicon film are similarly laminated to form a multilayer wiring. Next, a laminated body that constitutes a passive element is provided by using a printing method on the substrate 101 on which the thin film integrated circuit is formed. FIG. 5 shows a schematic process diagram in the case of forming a laminated inductor as a laminated body.

【0029】使用する磁性材料としては、Ni−Cu−
Znフェライトを使用し、この材料と有機合成樹脂バイ
ンダーとを混合し、印刷用の素地材料ペーストを準備す
る。また、必要とする特性に合わせて他の材料との混合
も可能である。
The magnetic material used is Ni-Cu-
Zn ferrite is used, and this material is mixed with an organic synthetic resin binder to prepare a base material paste for printing. It is also possible to mix with other materials according to the required properties.

【0030】このペーストを保護膜として層間絶縁膜1
05を形成した、前記の薄膜集積回路が形成された基板
上に印刷法で所定のパターンに磁性材料層211として
印刷する(図5(A)参照)。
Interlayer insulating film 1 using this paste as a protective film
The magnetic material layer 211 is printed in a predetermined pattern by a printing method on the substrate on which the thin film integrated circuit is formed, on which No. 05 is formed (see FIG. 5A).

【0031】次にインダクタの導体材料として、Ag−
Pd粉末を使用し、合成樹脂バインダーと混合し、印刷
用ペーストとし、これを所定のパターンに前記磁性材料
211が印刷された上に導体材料層212を印刷する
(図5(B)参照)。
Next, as the conductor material of the inductor, Ag-
Pd powder is used and mixed with a synthetic resin binder to form a printing paste, and the conductor material layer 212 is printed on the magnetic material 211 in a predetermined pattern (see FIG. 5B).

【0032】この時、薄膜集積回路の取り出し電極10
4と導体材料層212が電気的な接続を行えるようにパ
ターンを設計し、磁性材料層211の印刷時に接続のた
めのスルーホールを設けてある。
At this time, the extraction electrode 10 of the thin film integrated circuit
4 and the conductor material layer 212 are designed in a pattern so that they can be electrically connected to each other, and through holes for connection are provided when the magnetic material layer 211 is printed.

【0033】このようにして磁性材料を含む素地材料層
と導体材料層とを交互に積層して印刷し、この積層体が
インダクタを構成するように設計されたパターンに従っ
て、複数回印刷される。
In this way, the base material layers containing the magnetic material and the conductor material layers are alternately laminated and printed, and this laminated body is printed a plurality of times in accordance with the pattern designed to form the inductor.

【0034】またこの時、必要に応じて、パターンの一
部を利用して、このインダクタ内部に、薄膜集積回路の
取り出し電極につながった導通部を形成して行くことが
出来る。
At this time, if necessary, a part of the pattern can be utilized to form a conducting portion connected to the extraction electrode of the thin film integrated circuit inside the inductor.

【0035】次に混成集積回路部品の取り出し電極21
3を導電材料で印刷した後、これらの積層体を含む基板
のすべてを、所定の温度、例えば800〜1000℃、
本実施例では850℃で焼成し、積層体中の有機バイン
ダーの除去とインダクタの焼成を行う。
Next, the extraction electrode 21 of the hybrid integrated circuit component
After printing 3 with a conductive material, all of the substrates, including these laminates, are subjected to a predetermined temperature, for example 800-1000 ° C.,
In this embodiment, firing is performed at 850 ° C. to remove the organic binder in the laminated body and fire the inductor.

【0036】最後に、積層体を含む基板全体を、水素雰
囲気中で400℃1時間熱処理し、水素化処理を行い、
セラミック基板101上に形成した活性シリコン膜10
3中の欠陥準位密度の減少をはかり、本実施例の複合薄
膜集積回路部品を完成する。
Finally, the entire substrate including the laminated body is heat-treated in a hydrogen atmosphere at 400 ° C. for 1 hour to be hydrogenated,
Active silicon film 10 formed on ceramic substrate 101
By reducing the defect level density in 3, the composite thin film integrated circuit component of this example is completed.

【0037】前記の実施例では、薄膜集積回路を形成す
るセラミック基板101上に直接リフロー膜としてPS
G膜により構成された酸化シリコンを主成分とするガラ
ス層102を形成する例について述べたが、本発明で
は、セラミック基板とリフロー膜の間に熱伝導性の良好
な高融点金属又はそのシリサイドを形成することができ
る。
In the above embodiment, the PS film is directly used as the reflow film on the ceramic substrate 101 forming the thin film integrated circuit.
Although the example of forming the glass layer 102 containing silicon oxide as a main component and formed of the G film has been described, in the present invention, a refractory metal having good thermal conductivity or a silicide thereof is provided between the ceramic substrate and the reflow film. Can be formed.

【0038】熱伝導性の良好な高融点金属として、モリ
ブデンMo、タングステンW、タンタルTa、ジルコニ
ウムZr、コバルトCo、ハフニウムHf等を用いるこ
とが出来、またそのシリサイドも使用することが出来
る。
As the refractory metal having good thermal conductivity, molybdenum Mo, tungsten W, tantalum Ta, zirconium Zr, cobalt Co, hafnium Hf, etc. can be used, and its silicide can also be used.

【0039】これは、アルミナ等のセラミック基板上
に、例えばMo膜をスパッタリング法により形成するこ
とにより成膜することができる。この時の成膜条件は次
の通りである。
This can be formed by forming, for example, a Mo film on a ceramic substrate such as alumina by a sputtering method. The film forming conditions at this time are as follows.

【0040】 アルゴン圧 0.5〜10 mTorr 反応温度 300〜500℃ パワー 1 KW 次にMo膜を形成した基板上にPSG膜をスピンコート
しリフロー膜を形成する。以下の工程は前記実施例と同
様である。
Argon pressure 0.5 to 10 mTorr Reaction temperature 300 to 500 ° C. Power 1 KW Next, a PSG film is spin-coated on the substrate on which the Mo film is formed to form a reflow film. The subsequent steps are the same as in the above embodiment.

【0041】これにより、その後、半導体プロセス等の
熱処理工程を行っても、基板の放熱が十分に行われ、素
子の特性に悪影響を与えない。また、前記実施例では、
薄膜集積回路を形成した基板上の積層体として、積層型
インダクタを形成した例について説明したが、本発明は
これに限定されるものではなく、他の受動回路素子、例
えば抵抗、積層型コンデンサあるいはそれらを組合わせ
たものも用いることができる。
As a result, even if a heat treatment process such as a semiconductor process is performed thereafter, the heat is sufficiently radiated from the substrate and the characteristics of the element are not adversely affected. Further, in the above embodiment,
Although an example in which a laminated inductor is formed as a laminated body on a substrate on which a thin film integrated circuit is formed has been described, the present invention is not limited to this, and other passive circuit elements such as resistors, laminated capacitors or A combination of them can also be used.

【0042】さらに、これらの積層体の形成法は、前記
実施例で説明した印刷法のみに限定されず、スパッタリ
ング法、蒸着法等を用いたり、これらを組合わせること
もできる。
Further, the method of forming these laminated bodies is not limited to the printing method described in the above embodiment, but a sputtering method, a vapor deposition method or the like can be used, or a combination thereof can be used.

【0043】積層体を形成する導電材料としては、銀A
g、金Au、銅Cu、パラジウムPdあるいはこれらの
合金等、磁性体材料としてはその他亜鉛フェライト、M
n−Znフェライト、酸化鉄フェライト等、誘電体材料
としてはアルミナ、チタン酸バリウムや酸化チタン等を
使用できる。
Silver A is used as a conductive material for forming the laminate.
g, gold Au, copper Cu, palladium Pd, or alloys of these, other magnetic materials include zinc ferrite, M
Alumina, barium titanate, titanium oxide or the like can be used as the dielectric material such as n-Zn ferrite or iron oxide ferrite.

【0044】なお、前記実施例では本発明のリフロー膜
を設けた基板上に薄膜集積回路を形成後、積層体を形成
した例について説明したが、本発明は、別の工程で形成
した積層体を前記の基板上に取り付けることもできる。
In the above embodiment, an example was described in which a laminated body was formed after forming a thin film integrated circuit on a substrate provided with the reflow film of the present invention, but the present invention is a laminated body formed in another step. Can also be mounted on said substrate.

【0045】さらに前記実施例では半導体プロセスとし
て800℃以上の高温プロセスで行う例について説明し
たが、低温プロセスの場合にも、リフロー膜を設けるこ
とによって、特性のよい薄膜集積回路を得ることができ
る。
Further, in the above-described embodiment, an example in which a high temperature process of 800 ° C. or higher is performed as a semiconductor process has been described. However, even in the case of a low temperature process, a thin film integrated circuit having excellent characteristics can be obtained by providing the reflow film. .

【0046】なお前記実施例では、酸化シリコンを主成
分とするガラス層102としてPSG膜を使用した場合
について説明したが本発明は勿論これに限定されるもの
ではなく、例えばBSG(ボロシリケートグラス)、B
−PSG(ボロ−フォスフォシリケートグラス)、NS
G−PSG(ノンドープシリケートグラス−フォスフォ
シリケートグラス)等を使用することもできる。
In the above embodiment, the case where the PSG film is used as the glass layer 102 containing silicon oxide as a main component has been described, but the present invention is not limited to this, for example, BSG (borosilicate glass). , B
-PSG (boro-phosphosilicate glass), NS
G-PSG (non-doped silicate glass-phosphosilicate glass) or the like can also be used.

【0047】同様に層間絶縁膜105としても、PSG
に限定されるものではなく、BSG、B−PSG、NS
G−PSG等を使用することもできる。
Similarly, as the interlayer insulating film 105, PSG
It is not limited to BSG, B-PSG, NS
G-PSG or the like can also be used.

【0048】[0048]

【発明の効果】本発明の構成にすることにより、受動素
子から成る積層体と、所望の特性を有する薄膜集積回路
を形成したセラミック基板とを一体化することが出来、
複合薄膜集積回路部品の小型化、高密度化さらに低コス
ト化が達成できる。
With the structure of the present invention, it is possible to integrate a laminated body including passive elements and a ceramic substrate on which a thin film integrated circuit having desired characteristics is formed.
It is possible to reduce the size, density and cost of the composite thin film integrated circuit component.

【0049】また、本発明により安価なセラミック基板
上に、特性のよい薄膜集積回路を形成することが出来
る。特にセラミック基板を用いて、比較的高い温度の半
導体プロセスを施すことが出来るので、形成する回路の
応用範囲の広い集積回路素子を形成することが可能とな
った。
Further, according to the present invention, a thin film integrated circuit having excellent characteristics can be formed on an inexpensive ceramic substrate. In particular, since a semiconductor substrate can be subjected to a semiconductor process at a relatively high temperature by using a ceramic substrate, it is possible to form an integrated circuit element having a wide range of applications of a circuit to be formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の概略説明図である。FIG. 1 is a schematic explanatory diagram of an embodiment of the present invention.

【図2】本発明の一実施例で用いられる薄膜トランジス
タ(TFT)の概略説明図である。
FIG. 2 is a schematic explanatory diagram of a thin film transistor (TFT) used in an embodiment of the present invention.

【図3】本発明の一実施例で用いられるTFTの製造工
程説明図の一部である。
FIG. 3 is a part of a manufacturing process explanatory view of a TFT used in an embodiment of the present invention.

【図4】本発明の一実施例で用いられるTFTの製造工
程説明図の続きである。
FIG. 4 is a continuation of the manufacturing process explanatory view of the TFT used in one embodiment of the present invention.

【図5】本発明の一実施例の製造工程の概略説明図であ
る。
FIG. 5 is a schematic explanatory view of a manufacturing process according to an embodiment of the present invention.

【図6】従来の複合集積回路部品の概略説明図である。FIG. 6 is a schematic explanatory view of a conventional composite integrated circuit component.

【符号の説明】[Explanation of symbols]

101 セラミック基板 102 酸化シリコンを主成分とするガラス層 103 薄膜集積回路 104 パット電極 105 層間絶縁膜 106 積層型コンデンサ 107 積層型インダクタ 108 導体層 109 取り出し電極 101 Ceramic Substrate 102 Glass Layer Containing Silicon Oxide as Main Component 103 Thin Film Integrated Circuit 104 Pat Electrode 105 Interlayer Insulating Film 106 Multilayer Capacitor 107 Multilayer Inductor 108 Conductor Layer 109 Extraction Electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/38 A 7011−4E 3/46 Q 6921−4E (72)発明者 山内 幸夫 神奈川県厚木市長谷398番地 株式会社半 導体エネルギー研究所内 (72)発明者 坂本 直哉 神奈川県厚木市長谷398番地 株式会社半 導体エネルギー研究所内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location H05K 3/38 A 7011-4E 3/46 Q 6921-4E (72) Inventor Yukio Yamauchi Atsugi Kanagawa 398, Hase Hachi, Ltd. Inside the Semiconductor Energy Laboratory Co., Ltd. (72) Inventor, Naoya Sakamoto 398, Hase, Atsugi City, Kanagawa Prefecture

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 薄膜集積回路を形成したセラミック基板
上に、積層型コンデンサ、積層型インダクタ、抵抗ある
いはこれらを複合した積層体を設けた複合集積回路部品
において、該セラミック基板と薄膜集積回路との間に酸
化シリコンを主成分とするガラス層を形成し、セラミッ
ク基板表面の凹凸を平坦化することを特徴とする複合集
積回路部品。
1. A composite integrated circuit component comprising a ceramic substrate on which a thin film integrated circuit is formed, and a multilayer capacitor, a multilayer inductor, a resistor, or a laminated body in which these are composited, wherein the ceramic substrate and the thin film integrated circuit are provided. A composite integrated circuit component, characterized in that a glass layer containing silicon oxide as a main component is formed therebetween to flatten the irregularities on the surface of the ceramic substrate.
【請求項2】 前記セラミック基板と、前記酸化シリコ
ンを主成分とするガラス層の間に、熱伝導性のよい高融
点金属層又はそのシリサイド層を形成することを特徴と
する請求項1記載の複合集積回路部品。
2. A refractory metal layer having good thermal conductivity or a silicide layer thereof is formed between the ceramic substrate and the glass layer containing silicon oxide as a main component. Composite integrated circuit parts.
【請求項3】 前記薄膜集積回路に用いられる薄膜トラ
ンジスタのチャネル長は10μm以下であることを特徴
とする請求項1又は請求項2記載の複合集積回路部品。
3. The composite integrated circuit component according to claim 1, wherein the thin film transistor used in the thin film integrated circuit has a channel length of 10 μm or less.
JP5191299A 1993-05-21 1993-08-02 Composite integrated circuit parts Pending JPH0745786A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP5191299A JPH0745786A (en) 1993-08-02 1993-08-02 Composite integrated circuit parts
US08/242,813 US5643804A (en) 1993-05-21 1994-05-16 Method of manufacturing a hybrid integrated circuit component having a laminated body
KR1019940011146A KR100273826B1 (en) 1993-05-21 1994-05-21 Method of manufacturing a hybrid integrated circuit component having a laminated body and hybrid integrated circuit component
US08/812,453 US5877533A (en) 1993-05-21 1997-03-06 Hybrid integrated circuit component
US09/226,215 US6410960B1 (en) 1993-05-21 1999-01-07 Hybrid integrated circuit component
KR1019990046276A KR100311675B1 (en) 1993-05-21 1999-10-25 A composite integrated circuit componenet and a hybrid integrated circuit member
KR1020010009793A KR100351399B1 (en) 1993-05-21 2001-02-26 A method of manufacturing a composite integrated circuit component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5191299A JPH0745786A (en) 1993-08-02 1993-08-02 Composite integrated circuit parts

Publications (1)

Publication Number Publication Date
JPH0745786A true JPH0745786A (en) 1995-02-14

Family

ID=16272257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5191299A Pending JPH0745786A (en) 1993-05-21 1993-08-02 Composite integrated circuit parts

Country Status (1)

Country Link
JP (1) JPH0745786A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745335A (en) * 1996-06-27 1998-04-28 Gennum Corporation Multi-layer film capacitor structures and method
JP2004221570A (en) * 2002-12-27 2004-08-05 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
JP2006041135A (en) * 2004-07-26 2006-02-09 Sumitomo Bakelite Co Ltd Electronic device and manufacturing method thereof
JP2006324076A (en) * 2005-05-18 2006-11-30 Japan Pionics Co Ltd Glass panel, its manufacturing method, and plasma display panel using it
US8026152B2 (en) 2002-12-27 2011-09-27 Semiconductor Energy Laboratory Co., Ltd. Separation method of semiconductor device
JP2022521511A (en) * 2019-02-21 2022-04-08 ケメット エレクトロニクス コーポレーション Power module package with integrated passive components

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745335A (en) * 1996-06-27 1998-04-28 Gennum Corporation Multi-layer film capacitor structures and method
JP2004221570A (en) * 2002-12-27 2004-08-05 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
US8026152B2 (en) 2002-12-27 2011-09-27 Semiconductor Energy Laboratory Co., Ltd. Separation method of semiconductor device
US8441102B2 (en) 2002-12-27 2013-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a capacitor
JP2006041135A (en) * 2004-07-26 2006-02-09 Sumitomo Bakelite Co Ltd Electronic device and manufacturing method thereof
JP2006324076A (en) * 2005-05-18 2006-11-30 Japan Pionics Co Ltd Glass panel, its manufacturing method, and plasma display panel using it
JP2022521511A (en) * 2019-02-21 2022-04-08 ケメット エレクトロニクス コーポレーション Power module package with integrated passive components

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