JPH0745787A - Thin-film composite integrated circuit parts and its menufacture - Google Patents
Thin-film composite integrated circuit parts and its menufactureInfo
- Publication number
- JPH0745787A JPH0745787A JP5191300A JP19130093A JPH0745787A JP H0745787 A JPH0745787 A JP H0745787A JP 5191300 A JP5191300 A JP 5191300A JP 19130093 A JP19130093 A JP 19130093A JP H0745787 A JPH0745787 A JP H0745787A
- Authority
- JP
- Japan
- Prior art keywords
- film
- integrated circuit
- thin
- thin film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄膜複合集積回路部品に
係り、特に安価に製造できチップサイズの小さな薄膜複
合集積回路部品に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film composite integrated circuit component, and more particularly to a thin film composite integrated circuit component which can be manufactured at low cost and has a small chip size.
【０００２】[0002]
【従来の技術】能動回路素子から構成される薄膜集積回
路を形成した基板と、積層型コンデンサ、積層型インダ
クタ、抵抗回路あるいはこれらを組合わせたものから形
成される積層体を一体化させた複合集積回路部品は、従
来から知られている。2. Description of the Related Art A substrate in which a thin film integrated circuit composed of active circuit elements is formed and a laminated body formed of a laminated capacitor, a laminated inductor, a resistor circuit or a combination thereof are integrated. Integrated circuit components have been known for some time.
【０００３】一例として図５に示す如き構造の複合集積
回路部品について説明する。この複合集積回路部品は積
層型コンデンサ５１と、積層型インダクタ５２から成る
積層体と薄膜集積回路チップ５４とから構成される。積
層型コンデンサ５１を形成するためには、仮支持基板上
にＢａＴｉＯ3 系セラミックス等の誘電体材料ペースト
をシート状に印刷し、この上に電極用導体材料ペースト
を印刷し、さらにこの上に誘電体材料ペーストと電極用
導体材料ペーストを交互に複数層印刷して積層する。As an example, a composite integrated circuit component having a structure as shown in FIG. 5 will be described. This composite integrated circuit component comprises a multilayer capacitor 51, a multilayer body including a multilayer inductor 52, and a thin film integrated circuit chip 54. In order to form the multilayer capacitor 51, a dielectric material paste such as BaTiO 3 -based ceramics is printed in a sheet shape on a temporary support substrate, a conductor material paste for electrodes is printed thereon, and a dielectric material is further formed thereon. A plurality of layers of the body material paste and the electrode conductor material paste are alternately printed and laminated.
【０００４】この積層体の上に、同様にして磁性材料と
導体材料ペーストを積層印刷してインダクタンス部分を
積層する。積層型インダクタ５２は、例えば、Ｎｉ−Ｃ
ｕ−Ｚｎ系フェライト等の磁性体材料ペーストをシート
状に印刷し、その上にコイルパターンを印刷し、さらに
この上にこれらを交互に印刷する。それからこの積層体
を乾燥させたのち、仮支持板から剥離し、例えば８００
℃〜９００℃で焼成し、複合積層体を得る。A magnetic material and a conductor material paste are similarly laminated and printed on the laminated body to laminate the inductance portion. The multilayer inductor 52 is, for example, Ni-C.
A magnetic material paste such as u-Zn ferrite is printed in a sheet shape, a coil pattern is printed on the sheet, and these are alternately printed. Then, after drying this laminated body, it is peeled off from the temporary support plate, for example, 800
Firing at ℃ to 900 ℃, to obtain a composite laminate.
【０００５】このように形成した積層体上にベアの薄膜
集積回路チップ５４を搭載し、この薄膜集積回路チップ
５４の取り出し端子５５と積層体に設けられた電極パッ
ト５６とを金属線５７によりワイヤボンディングして電
気接続する。A bare thin film integrated circuit chip 54 is mounted on the laminated body formed in this way, and a takeout terminal 55 of this thin film integrated circuit chip 54 and an electrode pad 56 provided on the laminated body are wired by a metal wire 57. Bonding and electrical connection.
【０００６】最後にこの薄膜集積回路チップ５４を覆っ
てプラスチックあるいはセラミックのパッケージ５８を
形成し、複合集積回路部品５０を完成する。また、前記
の構成では、積層体を形成するために仮支持基板を用い
て受動素子材料ペーストと導電材料ペーストを印刷し、
その後これを剥離するという煩雑な工程が必要である。
これをなくすために、薄膜集積回路を形成した基板上に
直接積層体を形成する構造のものもある。Finally, a plastic or ceramic package 58 is formed covering the thin film integrated circuit chip 54 to complete the composite integrated circuit component 50. Further, in the above configuration, the passive element material paste and the conductive material paste are printed using the temporary support substrate to form the laminated body,
After that, a complicated process of peeling it off is required.
In order to eliminate this, there is also a structure in which a laminated body is directly formed on a substrate on which a thin film integrated circuit is formed.
【０００７】さらに薄膜集積回路チップと受動素子から
なる積層体を別々の工程で形成するのでなく、ＬＳＩの
Ｓｉ基板内に、大容量のコンデンサを薄膜プロセスで内
蔵させて形成する試みも提案されている（ＮＩＫＫＥＩ
ＥＬＥＣＴＲＯＮＩＣＳ１９９３年５月２４日号ｐ８
２〜８７参照）。Further, an attempt has also been proposed to form a large-capacity capacitor in a Si substrate of an LSI by a thin film process, instead of forming a laminated body including a thin film integrated circuit chip and a passive element in separate steps. (NIKKEI
ELECTRONICS May 24, 1993 issue p8
2-87).
【０００８】[0008]
【発明が解決しようとする課題】従来の複合集積回路部
品では、その受動素子部分を構成する積層体は積層印
刷、焼成による厚膜プロセスで形成する。従って積層体
として誘電体材料層や磁性体材料層を多層に積層する場
合でも非常に生産性良く、安価に製造することができ
る。またインダクタやコンデンサの数が少くなれば、複
合集積回路部品の大きさは小さく出来る。In the conventional composite integrated circuit component, the laminated body constituting the passive element portion is formed by a thick film process by laminated printing and firing. Therefore, even when a dielectric material layer or a magnetic material layer is laminated in multiple layers as a laminated body, it can be manufactured with extremely high productivity and at low cost. In addition, the size of the composite integrated circuit component can be reduced by reducing the number of inductors and capacitors.
【０００９】ところが、薄膜集積回路を搭載して複合集
積回路部品を構成する場合には、薄膜集積回路チップを
搭載するための一定の大きさが積層体としては必要とな
り、積層体の大きさを十分に小さく出来ないという問題
点がある。However, when a thin film integrated circuit is mounted to form a composite integrated circuit component, a certain size for mounting the thin film integrated circuit chip is required for the laminated body, and the size of the laminated body is reduced. There is a problem that it cannot be made small enough.
【００１０】また、薄膜集積回路を形成した基板上に直
接厚膜プロセスで積層体を形成するものでは、積層体の
形成のための焼成温度が高いため、予め形成した薄膜集
積回路の素子特性に悪影響を与えることや、焼成による
積層体の縮みが、前記薄膜集積回路に悪影響を与えるな
どの問題点がある。Further, in the case where the laminated body is formed directly on the substrate on which the thin film integrated circuit is formed by the thick film process, the firing temperature for forming the laminated body is high, so that the device characteristics of the thin film integrated circuit formed in advance are There are problems such that the thin film integrated circuit is adversely affected and the shrinkage of the laminate due to firing adversely affects the thin film integrated circuit.
【００１１】さらに、ＬＳＩに大容量のコンデンサを内
蔵させたものは、その製法上、薄膜集積回路を形成した
基板上に、薄膜集積回路の横にこれを形成することにな
り、このため、全体の部品の大ききさが大型化するなど
の問題点がある。Further, in the LSI in which a large-capacity capacitor is built in, the thin film integrated circuit is formed on the substrate on which the thin film integrated circuit is formed due to its manufacturing method. However, there is a problem in that the size of the parts is large.
【００１２】従って本発明の目的は、安価に製造出来る
上にチップサイズの小さな複合集積回路部品を提供する
ものである。Therefore, an object of the present invention is to provide a composite integrated circuit component which can be manufactured at low cost and has a small chip size.
【００１３】[0013]
【課題を解決するための手段】本発明は前記問題点を解
決するため、薄膜集積回路を形成した基板上に、積層型
コンデンサ、積層型インダクタあるいはこれらを組合わ
せた受動回路を構成する積層部を形成した複合集積回路
部品において、積層部として、前記薄膜集積回路にＳｉ
Ｏ2 を主成分とするガラス層からなる層間膜を介在し
て、薄膜プロセスで形成した薄膜積層体を形成するもの
である。SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a multilayer capacitor, a multilayer inductor, or a multilayer portion which constitutes a passive circuit combining these on a substrate on which a thin film integrated circuit is formed. In the composite integrated circuit component formed with, a Si layer is formed on the thin film integrated circuit as a laminated part.
A thin film laminate formed by a thin film process is formed with an interlayer film made of a glass layer containing O 2 as a main component interposed.
【００１４】なお、薄膜プロセスで形成する膜は１０層
以内であることが望ましい。The film formed by the thin film process is preferably 10 layers or less.
【００１５】[0015]
【作用】これにより薄膜集積回路を形成した基板上に垂
直方向に薄膜積層体を形成することができるので、薄膜
複合集積回路部品を非常に小型に提供できる。As a result, the thin film laminated body can be formed in the vertical direction on the substrate on which the thin film integrated circuit is formed, so that the thin film composite integrated circuit component can be provided in a very small size.
【００１６】[0016]
【実施例】本発明の一実施例を図１〜図４によって説明
する。図１は本発明の一実施例である薄膜複合集積回路
部品１０の概略説明図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic explanatory view of a thin film composite integrated circuit component 10 which is an embodiment of the present invention.
【００１７】図１において、１１は基板、１２は薄膜集
積回路チップ、１３は取り出し電極、１４はフォスフォ
シリケートグラス（ＰＳＧ）膜、１５はＴｉＯ2 層、１
６はＡｌ層、１７は薄膜積層型コンデンサ、１８は薄膜
積層型インダクタ、１９は薄膜磁性材料層、２０は取り
出し電極を示す。In FIG. 1, 11 is a substrate, 12 is a thin film integrated circuit chip, 13 is a take-out electrode, 14 is a phosphosilicate glass (PSG) film, 15 is a TiO 2 layer, 1
6 is an Al layer, 17 is a thin film laminated capacitor, 18 is a thin film laminated inductor, 19 is a thin film magnetic material layer, and 20 is a take-out electrode.
【００１８】本実施例においては薄膜集積回路チップ１
２を形成した基板１１上に常圧ＣＶＤ法によって形成し
たＰＳＧ膜１４を介在させて、誘電体材料層、例えばＴ
ｉＯ 2 層１５と導体材料層、例えばＡｌ層１６とを交互
にマスク蒸着やマスクスパッタ法を用いた薄膜プロセス
を用いて形成し、薄膜積層型コンデンサ１７と、磁性材
料層１９とＡｌ層１６からなる薄膜積層型インダクタ１
８を形成する。In the present embodiment, the thin film integrated circuit chip 1
2 is formed by the atmospheric pressure CVD method on the substrate 11 on which
With the PSG film 14 interposed, a dielectric material layer such as T
iO 2Alternating layers 15 and conductor material layers, eg Al layers 16
Film process using mask evaporation and mask sputtering method
Thin film multilayer capacitor 17 and magnetic material
Thin-film laminated inductor 1 including material layer 19 and Al layer 16
8 is formed.
【００１９】また、薄膜集積回路チップ１２と薄膜積層
型コンデンサ１７との間の層間膜１４はフォスフォシリ
ケートグラス（ＰＳＧ）膜、ノンドープシリケートグラ
ス（ＮＳＧ）膜、ボロシリケートグラス（ＢＳＧ）膜、
このＢＳＧと、フォスフォシリケートグラス（ＰＳＧ）
との混合体であるボロフォスフォシリケートグラス（Ｂ
・ＰＳＧ）膜の如きＳｉＯ2 を主成分とするガラス膜の
少なくとも一種以上から成る膜であって、その膜厚は
０．１〜５μｍ、好ましくは８０００Å以上あるとよ
い。これらのガラス膜は常圧ＣＶＤ法により形成するこ
とができる。The interlayer film 14 between the thin film integrated circuit chip 12 and the thin film multilayer capacitor 17 is a phosphosilicate glass (PSG) film, a non-doped silicate glass (NSG) film, a borosilicate glass (BSG) film,
This BSG and phosphosilicate glass (PSG)
Borophosphosilicate glass (B
A film made of at least one kind of glass film containing SiO 2 as a main component, such as a PSG) film, and the film thickness is 0.1 to 5 μm, preferably 8000 Å or more. These glass films can be formed by the atmospheric pressure CVD method.
【００２０】なお、薄膜集積回路チップ１２と薄膜積層
型コンデンサ１７、薄膜積層型インダクタ１８とは薄膜
集積回路の取り出し電極１３と導体材料層であるＡｌ層
１６によって電気的に接続される。The thin film integrated circuit chip 12, the thin film multilayer capacitor 17, and the thin film multilayer inductor 18 are electrically connected to each other by the lead electrode 13 of the thin film integrated circuit and the Al layer 16 which is a conductor material layer.
【００２１】次に本実施例の薄膜複合集積回路部品に用
いる、薄膜集積回路チップ１２における薄膜トランジス
タの製造工程を、図２〜図３によって説明する。先ず、
基板１１として多結晶シリコン基板を用い、この基板１
１上にスパッタ法により、酸化シリコン膜２２を１００
０〜５０００Åの厚さに形成する（図２（Ａ）参照）。Next, the manufacturing process of the thin film transistor in the thin film integrated circuit chip 12 used in the thin film composite integrated circuit component of this embodiment will be described with reference to FIGS. First,
A polycrystalline silicon substrate is used as the substrate 11, and this substrate 1
1 by sputtering the silicon oxide film 22 to 100
It is formed to a thickness of 0 to 5000Å (see FIG. 2 (A)).
【００２２】次にこの上にアモルファス・シリコン（α
−Ｓｉ）膜２３’を減圧ＣＶＤ法により、５００〜６０
００Åの厚さに形成する（図２（Ｂ）参照）。この時の
成膜条件は次の通りである。Next, an amorphous silicon (α
-Si) film 23 'is formed by a low pressure CVD method to 500-60
It is formed to a thickness of 00Å (see FIG. 2 (B)). The film forming conditions at this time are as follows.
【００２３】 Ｓｉ2 Ｈ6 １００〜５００ ＳＣＣＭ Ｈｅ ５００ ＳＣＣＭ 反応圧力 ０．１〜１ Ｔｏｒｒ 成膜温度 ４３０〜５００℃ このα−Ｓｉ膜２３’を所定のアイランド状にパターニ
ングした後、約６００℃で約４０時間、窒素雰囲気中で
熱処理して結晶化し活性シリコン膜２３とする（図２
（Ｃ）参照）。Si 2 H 6 100 to 500 SCCM He 500 SCCM Reaction pressure 0.1 to 1 Torr Film formation temperature 430 to 500 ° C. After patterning the α-Si film 23 ′ into a predetermined island shape, the temperature is about 600 ° C. It is heat-treated in a nitrogen atmosphere for about 40 hours to be crystallized to form an active silicon film 23 (FIG. 2).
(See (C)).
【００２４】次にゲート絶縁膜を形成するために、ドラ
イ酸化により、５００〜２０００Åの膜厚の酸化シリコ
ン膜２４’を形成する（図２（Ｄ）参照）。この時の成
膜条件は次の通りである。Next, in order to form a gate insulating film, a silicon oxide film 24 'having a film thickness of 500 to 2000 Å is formed by dry oxidation (see FIG. 2D). The film forming conditions at this time are as follows.
【００２５】 Ｏ2 ２．５ ＳＬＭ 反応温度 ８５０〜１１００℃ 次にこの上にゲート電極となるＰ又はＢをドープしたシ
リコン層２５’を減圧ＣＶＤ法により、１０００〜４０
００Åの膜厚で形成する（図２（Ｅ）参照）。O 2 2.5 SLM Reaction temperature 850 to 1100 ° C. Next, a P or B-doped silicon layer 25 ′ serving as a gate electrode is formed on this layer by a low pressure CVD method at 1000 to 40 ° C.
It is formed with a film thickness of 00Å (see FIG. 2E).
【００２６】この後、所定のパターンに従ってエッチン
グ工程によりゲート絶縁膜２４、ゲート電極２５を形成
する（図２（Ｆ）参照）。さらにこのゲート電極２５を
マスクとして、活性シリコン膜２３のソース・ドレイン
領域となるべき部分に、イオンドーピング法により、例
えばＰをドープしてソース・ドレイン領域２６、２７を
形成する（図３（Ａ）参照）。After that, a gate insulating film 24 and a gate electrode 25 are formed by an etching process according to a predetermined pattern (see FIG. 2F). Further, using the gate electrode 25 as a mask, source / drain regions 26 and 27 are formed in the portion of the active silicon film 23 to be the source / drain regions by ion doping, for example, by doping P (FIG. 3A). )reference).
【００２７】これらの素子を含む基板を窒素雰囲気中で
６００℃で１２時間加熱しドーパントの活性化を行い、
さらに水素雰囲気中で４００℃１時間熱処理し、水素化
処理を行い活性シリコン膜２３の欠陥準位密度を減少さ
せる。A substrate including these elements is heated at 600 ° C. for 12 hours in a nitrogen atmosphere to activate the dopant,
Further, heat treatment is performed in a hydrogen atmosphere at 400 ° C. for 1 hour to perform hydrogenation treatment to reduce the defect level density of the active silicon film 23.
【００２８】次にこの基板全体に常圧ＣＶＤ法でＰＳＧ
膜２８を４０００〜８０００Åの膜厚で形成した後、各
電極配線のために、必要とするパターンに従ってパター
ニングを行う（図３（Ｂ）参照）。Next, PSG is formed on the entire substrate by the atmospheric pressure CVD method.
After forming the film 28 with a film thickness of 4000 to 8000Å, patterning is performed according to a required pattern for each electrode wiring (see FIG. 3B).
【００２９】この後電極配線用のＡｌをスパッタ法によ
り成膜し、配線パターンに従ってパターニングし、配線
層２９を形成して、図３（Ｃ）の如き薄膜トランジスタ
を完成する。After that, Al for the electrode wiring is formed by the sputtering method, patterned according to the wiring pattern, and the wiring layer 29 is formed to complete the thin film transistor as shown in FIG. 3C.
【００３０】この後に保護膜を兼ねたＰＳＧ膜を層間絶
縁膜として形成し、電極用スルーホールを形成後電極配
線層を形成して薄膜集積回路チップ１２を構成する。本
発明では、次にこの薄膜集積回路チップ１２が形成され
た基板１１上にＰＳＧ膜１４を介して薄膜プロセスを用
いて図１に示す如く、薄膜状の受動素子の薄膜積層型コ
ンデンサ１７、薄膜積層型インダクタ１８等を形成す
る。After that, a PSG film also serving as a protective film is formed as an interlayer insulating film, an electrode through hole is formed, and then an electrode wiring layer is formed to form the thin film integrated circuit chip 12. In the present invention, next, as shown in FIG. 1, using a thin film process through the PSG film 14 on the substrate 11 on which the thin film integrated circuit chip 12 is formed, as shown in FIG. The laminated inductor 18 and the like are formed.
【００３１】薄膜積層部として積層インダクタ１８を形
成する場合を図４によって説明する。使用する磁性材料
としてはＮｉ−Ｃｕ−Ｚｎフェライトを使用し、次の条
件でマスクスパッタリングを行い、Ｎｉ−Ｃｕ−Ｚｎフ
ェライト膜１９を形成する（図４（Ａ）参照）。The case of forming the laminated inductor 18 as the thin film laminated portion will be described with reference to FIG. Ni—Cu—Zn ferrite is used as the magnetic material to be used, and mask sputtering is performed under the following conditions to form the Ni—Cu—Zn ferrite film 19 (see FIG. 4A).
【００３２】スパッタリングの条件は以下の通りであ
る。 ターゲット Ｎｉ−Ｃｕ−Ｚｎ アルゴン圧 １０〜１００ ｍＴｏｒｒ 反応温度 １５０℃ ＲＦパワー １ ＫＷ なお、フェライト膜１９には薄膜集積回路チップ１２の
取り出し電極１３に対応するスルーホールを形成する。The sputtering conditions are as follows. Target Ni-Cu-Zn Argon pressure 10 to 100 mTorr Reaction temperature 150 ° C. RF power 1 KW In addition, a through hole corresponding to the extraction electrode 13 of the thin film integrated circuit chip 12 is formed in the ferrite film 19.
【００３３】次にインダクタの導体材料層として、Ａｌ
をマスクスパッタリングにより蒸着しＡｌ層１６を形成
するとともに、薄膜集積回路の取り出し電極１３と導体
層１６との接続も行う（図４（Ｂ）参照）。Next, as a conductor material layer of the inductor, Al
Is vapor-deposited by mask sputtering to form the Al layer 16, and the extraction electrode 13 of the thin film integrated circuit and the conductor layer 16 are also connected (see FIG. 4B).
【００３４】同様に薄膜プロセスを用いて交互にＮｉ−
Ｃｕ−Ｚｎフェライト膜１９’と導体層１６’を形成し
て積層型の薄膜インダクタ１８を形成する（図４（Ｃ）
参照）。Similarly, a thin film process is used to alternate the Ni--
A Cu-Zn ferrite film 19 'and a conductor layer 16' are formed to form a laminated thin film inductor 18 (FIG. 4C).
reference).
【００３５】その後、必要に応じてこの上に積層型薄膜
コンデンサを形成することもできる。例えば、誘電体材
料としてＴｉＯ2 を用いてマスクスパッタリングを行う
ときの成膜の条件は次の通りである。After that, a laminated thin film capacitor can be formed on this, if necessary. For example, the conditions of film formation when mask sputtering is performed using TiO 2 as a dielectric material are as follows.
【００３６】 真空度 ０．０１ Ｔｏｒｒ 基板の温度 ２００℃ ソース温度 １５００℃ この条件でＴｉＯ2 膜を形成後、Ａｌをマスクスパッタ
リングして導体膜として積層化して、例えば、図１に示
す如く薄膜積層型コンデンサ１７を形成する。Degree of vacuum 0.01 Torr Substrate temperature 200 ° C. Source temperature 1500 ° C. Under these conditions, a TiO 2 film is formed, and then Al is mask-sputtered to be laminated as a conductor film. For example, thin film lamination as shown in FIG. The mold capacitor 17 is formed.
【００３７】本発明では、薄膜集積回路を形成した基板
上に形成する積層部として各受動素子をマスクスパッタ
リングなどの薄膜プロセスで行うため、反応条件を変え
るだけでよいので製造が容易であるが、多層にするには
スパッタリング工程時に加熱処理が介在するので、その
影響を小さくするために全体で１０層以内にすることが
望ましい。In the present invention, since each passive element is formed by a thin film process such as mask sputtering as a laminated portion formed on a substrate on which a thin film integrated circuit is formed, it is easy to manufacture because only reaction conditions need to be changed. Since heat treatment is involved during the sputtering process to form a multilayer, it is desirable that the total number be within 10 layers in order to reduce the effect.
【００３８】[0038]
【発明の効果】本発明の構成にすることにより、薄膜集
積回路チップを形成した基板上に形成する積層部も全部
薄膜プロセスで行うため、従来の厚膜法のように高温に
よる焼成処理など、基板に対して高温熱処理を行うこと
がない。According to the structure of the present invention, since the laminated portion formed on the substrate on which the thin film integrated circuit chip is formed is also entirely formed by the thin film process, a baking treatment at a high temperature as in the conventional thick film method, etc. No high temperature heat treatment is applied to the substrate.
【００３９】これにより焼成による積層体の縮みと薄膜
集積回路を形成した基板との熱膨張係数の違いによる悪
影響もない。さらに薄膜集積回路形成後の高温熱処理が
ないので、水素化がし易い上、熱による素子特性への悪
影響もない。As a result, there is no adverse effect due to the shrinkage of the laminate due to firing and the difference in the coefficient of thermal expansion between the substrate on which the thin film integrated circuit is formed. Furthermore, since there is no high-temperature heat treatment after the thin film integrated circuit is formed, hydrogenation is easy and there is no adverse effect on the device characteristics due to heat.
【００４０】また、薄膜法により、従来の圧膜法より積
層部が薄くなり部品の小型化、コンパクト化が実現す
る。ＩＣのチップサイズは樹脂モールドの大きさにより
決まるため、この樹脂モールドを全体で一体化できるた
め小型化できる。Further, the thin film method allows the laminated portion to be thinner than that of the conventional pressure film method, so that the parts can be made smaller and more compact. Since the chip size of the IC is determined by the size of the resin mold, this resin mold can be integrated as a whole, so that the size can be reduced.
【００４１】その上、積層部の導体材料として高価なＰ
ｄの代わりに安価なＡｌが使用でき、その点からも薄膜
集積回路部品の低コスト化がはかれる。In addition, P which is expensive as a conductor material for the laminated portion
Inexpensive Al can be used instead of d, and also from this point, the cost of the thin film integrated circuit component can be reduced.
【図１】本発明の一実施例の薄膜複合集積回路部品の概
略構成説明図である。FIG. 1 is a schematic configuration explanatory view of a thin film composite integrated circuit component of one embodiment of the present invention.
【図２】本発明の一実施例で用いる薄膜トランジスタの
製造工程説明図の一部である。FIG. 2 is a part of a manufacturing process explanatory view of a thin film transistor used in one embodiment of the present invention.
【図３】本発明の一実施例で用いる薄膜トランジスタの
製造工程説明図の続きである。FIG. 3 is a continuation of the manufacturing process explanatory diagram of the thin film transistor used in the embodiment of the present invention.
【図４】本発明の一実施例の薄膜複合集積回路部品の薄
膜積層部の製造工程説明図である。FIG. 4 is an explanatory view of the manufacturing process of the thin film laminated portion of the thin film composite integrated circuit component of one embodiment of the present invention.
【図５】従来の複合集積回路部品の概略構成説明図であ
る。FIG. 5 is a schematic configuration explanatory view of a conventional composite integrated circuit component.
１１ 基板 １２ 薄膜集積回路チップ １４ ＰＳＧ膜 １５ 薄膜誘電体材料層 １６ Ａｌ層 １７ 薄膜積層型コンデンサ １８ 薄膜積層型インダクタ １９ 薄膜磁性体材料層 11 Substrate 12 Thin Film Integrated Circuit Chip 14 PSG Film 15 Thin Film Dielectric Material Layer 16 Al Layer 17 Thin Film Multilayer Capacitor 18 Thin Film Multilayer Inductor 19 Thin Film Magnetic Material Layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/46 Ｑ 6921−4Ｅ (72)発明者 坂本 直哉 神奈川県厚木市長谷398番地 株式会社半 導体エネルギー研究所内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location H05K 3/46 Q 6921-4E (72) Inventor Naoya Sakamoto 398 Hase, Atsugi-shi, Kanagawa Co., Ltd. Conductor Energy Laboratory
Claims (5)
コンデンサ、積層型インダクタあるいはこれらを組合わ
せた受動素子を構成する積層部を形成した複合集積回路
部品において、薄膜集積回路を形成した基板上にＳｉＯ
2 を主成分とするガラス層からなる層間膜を介在して、
薄膜プロセスで形成した薄膜積層型受動素子を形成する
ことを特徴とする薄膜複合集積回路部品。1. A composite integrated circuit component having a thin film integrated circuit formed on a substrate on which a thin film integrated circuit is formed, in which a multilayer capacitor, a laminated inductor, or a laminated portion forming a passive element combining these is formed. SiO on top
With an inter-layer film consisting of a glass layer whose main component is 2 ,
A thin film composite integrated circuit component characterized by forming a thin film laminated passive device formed by a thin film process.
ラス膜、ノンドープシリケートグラス膜、ボロシリケー
トグラス膜、ボロフォスフォシリケートグラス膜のうち
の少なくとも１層からなることを特徴とする請求項１記
載の薄膜複合集積回路部品。2. The interlayer film is made of at least one layer selected from a phosphosilicate glass film, a non-doped silicate glass film, a borosilicate glass film, and a borophosphosilicate glass film. Thin film composite integrated circuit component.
ることを特徴とする請求項１記載の薄膜複合集積回路部
品。3. The thin film composite integrated circuit component according to claim 1, wherein the thickness of the interlayer film is 0.1 to 5 μm.
１０層以内とすることを特徴とする請求項１記載の薄膜
複合集積回路部品。4. The thin film composite integrated circuit component according to claim 1, wherein the thin film laminated body of the thin film laminated passive element is within 10 layers.
法によりＳｉＯ2 を主成分とするガラス層からなる層間
膜を形成する工程と、該層間膜上に４５０℃以下の薄膜
プロセスで薄膜積層型受動素子を形成する工程とを有す
る薄膜複合集積回路部品の製造方法。5. A CVD method on a substrate on which a thin film integrated circuit is formed.
Thin film composite integrated circuit component including a step of forming an interlayer film made of a glass layer containing SiO 2 as a main component by a method and a step of forming a thin film laminated passive element on the interlayer film by a thin film process at 450 ° C. or lower Manufacturing method.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5191300A JPH0745787A (en) | 1993-08-02 | 1993-08-02 | Thin-film composite integrated circuit parts and its menufacture |
| US08/242,813 US5643804A (en) | 1993-05-21 | 1994-05-16 | Method of manufacturing a hybrid integrated circuit component having a laminated body |
| KR1019940011146A KR100273826B1 (en) | 1993-05-21 | 1994-05-21 | Method of manufacturing a hybrid integrated circuit component having a laminated body and hybrid integrated circuit component |
| US08/812,453 US5877533A (en) | 1993-05-21 | 1997-03-06 | Hybrid integrated circuit component |
| US09/226,215 US6410960B1 (en) | 1993-05-21 | 1999-01-07 | Hybrid integrated circuit component |
| KR1019990046276A KR100311675B1 (en) | 1993-05-21 | 1999-10-25 | A composite integrated circuit componenet and a hybrid integrated circuit member |
| KR1020010009793A KR100351399B1 (en) | 1993-05-21 | 2001-02-26 | A method of manufacturing a composite integrated circuit component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5191300A JPH0745787A (en) | 1993-08-02 | 1993-08-02 | Thin-film composite integrated circuit parts and its menufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0745787A true JPH0745787A (en) | 1995-02-14 |
Family
ID=16272274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5191300A Pending JPH0745787A (en) | 1993-05-21 | 1993-08-02 | Thin-film composite integrated circuit parts and its menufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0745787A (en) |
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