JPH0745701A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease the parasitic capacitance between wirings by providing vacant space between the wirings on the same layer. CONSTITUTION:After wirings 2 have been formed on the same layer, a solid film 3 is formed while it is being cooled by the use of a liquid. The solid film is removed as for as the wiring part is exposed. After a roughly insulating film 5 having a large film shrinkage factor has been formed on the solid film, the solid film is evaporated through the insulating film 5 by heating etc., and a dense insulating film 7 having the film shrinkage factor smaller than that of the insulating film 5 is formed. Space 6 is obtained between wirings.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a space between wirings in the same layer and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, multi-layer wiring and miniaturization have been advanced for higher performance. For a semiconductor device having a minimum feature size of 0.3 μm or less, an increase in wiring parasitic capacitance is a serious problem for speeding up. There is a serious problem that the inter-wiring capacitance in the same layer increases with miniaturization.

Therefore, in order to reduce the parasitic capacitance between the wirings, a semiconductor device having a space between the wirings has been proposed, for example, as disclosed in Japanese Patent Laid-Open No. 2-240947. A conventional semiconductor device having a space between wirings and a method for manufacturing the same will be described with reference to FIG.

First, as shown in FIG. 6A, CV is formed on the surface of a silicon substrate on which transistors and the like (not shown) are formed.
A semiconductor substrate on which the silicon oxide film 1 is formed by the D method or the like is prepared. A contact hole (not shown) is formed in the silicon oxide film by using a normal photolithography technique. Next, an Al film is formed by a sputtering method or the like, and the Al film is patterned by using a normal photolithography technique to form the Al film wiring 2 of the first layer. Next, the silicon oxide film 11 is formed by the CVD method.

Then, using the spin coating method, as shown in FIG.
As shown in (b), the SOG film 13 is formed. Next, a silicon oxide film 14 is formed by using a plasma CVD method or the like, a photoresist film is formed, and then etching back is performed to planarize the film. Then, the silicon oxide film 15 is formed by the plasma CVD method or the like.

Next, the contact hole 16 is formed by using the photolithography technique. Then, the Al film 8A is formed by the sputtering method or the like, and the second Al film wiring 8 is formed by using the photolithography technique as shown in FIG. 6C. Then, the silicon oxide films 14 and 15 and the SOG film 13 are etched by the plasma etching method using the second Al film wiring 8 as a mask to form a space between the wirings of the first layer and the second layer.

Finally, as shown in FIG. 6D, the silicon oxide film 17 and the silicon nitride film 18 are formed by plasma CV.
It is formed by the D method. As described above, the space insulating structure can be realized not only between the uppermost wirings but also between the lower wirings.

[0008]

In this conventional semiconductor device, a space can be formed not only between the wirings in the uppermost layer but also in a portion between the wirings in the lower layer, but the uppermost layer and the lower layer overlap each other. The part has the drawback that no space can be formed. Therefore, in order to improve the performance of semiconductor devices, multi-layer wiring has been advanced,
In the case of a semiconductor device having a multi-layered wiring of three or more layers, there is an increase in the number of overlapping portions of the wiring layers, and the ratio of spaces that can be formed decreases as the number of layers increases, which reduces the effect of reducing the parasitic capacitance between the wirings. There is. As described above, the conventional method has a problem in that it is used in a future semiconductor device having a minimum processing dimension of 0.3 μm or less, and the speed-up effect is small.

[0009]

The semiconductor device of the present invention comprises:
A plurality of wirings in the same layer formed by selectively covering the surface of a predetermined first insulating film of a semiconductor substrate, a sparse second insulating film covering the surface of the wiring, and the second insulating film It has a dense third insulating film covering the surface of the film and has a space between the wirings.

Also, the method of manufacturing a semiconductor device of the present invention comprises the step of selectively covering the surface of the first insulating film covering the surface of the semiconductor substrate to form a plurality of wirings in the same layer and the semiconductor substrate. Forming a solid film on the surface of the first insulating film selectively covered with the wiring by supplying and solidifying a predetermined liquid while cooling the surface of the wiring, and thinning the solid film. Of the wiring, a step of depositing a sparse second insulating film on the entire surface, a step of evaporating the solid film under heating or reduced pressure, and a step of depositing a dense third insulating film. A space is provided between them. In this case, a solid film is formed after forming a protective film covering the surface and side surfaces of the wiring, and then the solid film is thinned to expose the protective film on the surface of the wiring and then a sparse second film is formed. An insulating film may be deposited on the entire surface.

[0011]

The present invention will be described below with reference to the drawings. 1A to 1E are cross-sectional views in order of the processes, for illustrating the first embodiment of the present invention along with the manufacturing process.

First, as shown in FIG. 1A, after forming various parts necessary for forming a semiconductor device on a silicon substrate (not shown), such as a transistor, by using an ordinary technique, A semiconductor substrate on which the silicon oxide film 1 (first insulating film) is formed to have a thickness of about 200 to 800 nm by using the CVD method or the like is prepared. Next, a contact hole (not shown) is formed by using a normal photolithography technique or the like. Then, the Al film wiring 2 of the first layer is formed by using the sputtering technique.

Next, while cooling the semiconductor substrate to 0 ° C. or lower, for example, by using a spin coater, for example, water is dropped to form an ice film 3 on the surface of the semiconductor substrate as shown in FIG. 1B.
Is formed to have a thickness of about 0.5 to 2 μm. Next, using a chemical mechanical polishing (CMP) device, for example, while flowing alcohol and rotating at several tens to several hundred rpm, several tens to 2000 g / c.
Polishing is performed until the Al wiring 2 is exposed by applying a pressure of m ² to the semiconductor substrate.

Although the CMP method is used in this embodiment, it may be carried out by an etch-back method such as a plasma etching method, or the moisture may be removed at a temperature of 0 to -10.degree.

Subsequently, a sparse silicon oxide film (second insulating film) 5 having a large film shrinkage ratio at a low temperature of 0 ° C. or less is formed on the surface of the thin film 200.
A film is formed up to 500 nm. As a forming method, for example, hydrogen-diluted SiH ₄ + O ₂ -based cooling plasma CVD method is used, and glow discharge decomposition of hydrogen-diluted silane 100 sccm oxygen 10 sccm mixed gas is performed at a reaction pressure of 0.2 Torr, a discharge power of 50 W, and a silicon substrate temperature of −110 ° C. A film is formed.
This cooled plasma CVD method is based on the proceedings No. 38 of the 38th Joint Lecture on Applied Physics. 2, p. 633, 29p-
V-11.

A silicon oxide type insulating film may be formed at around 0 ° C. by using triethoxyfluorosilane and water. In this case, since water is supplied as water vapor from above the ice film 3, only triethoxyfluorosilane may be allowed to flow at atmospheric pressure, or plasma CVD using TEOS and water.
Law is okay.

Regarding such a CVD method, 1991
International Electron Device Meading Technical Digest Magazine (1991 Inte
national Electron Device
s Meeting TECHNICAL DIGES
T), pages 289-292.

The silicon oxide type insulating film formed by such a method is a sparse film which exhibits a volume shrinkage of at least 3% when treated in a nitrogen atmosphere at 900 ° C.

After that, heat to 100 to 300 ° C.,
Alternatively, the pressure may be reduced to several Torr, as shown in FIG.
As shown in FIG. 3, the ice film 3 between the wirings is converted to water vapor 4 and evaporated through the sparse silicon oxide insulating film 5.

A dense silicon oxide insulating film 7 (third insulating film) having a volume shrinkage less than that of the silicon oxide insulating film 5 due to heat treatment, for example, a shrinkage ratio of 3% or less is shown in FIG.
As shown in (e), a film having a thickness of 200 to 1000 nm is formed.
As a film forming method, there is a plasma CVD method using silane and nitrous oxide or tetraethoxysilane and oxygen. Next, an Al film is formed in a thickness of 0.3 to 1 μm using a sputtering method.
The film is formed, and the Al film wiring 8 of the second layer is formed by using the ordinary photolithography technique and the plasma etching technique.

As described above, according to the present invention, the space 6 can be formed between the wirings by evaporating the ice film 3 as water through the sparse silicon oxide insulating film 5. Since there is no solid in the space, the relative dielectric constant is about 1, which is reduced to about 1/4 as compared with about 4 of the silicon oxide film. Therefore, in the conventional example, the portion where the wiring of the first layer and the wiring of the second layer overlap is
Although a silicon oxide film was present instead of a space, by using the present invention, a space can be formed between the wirings of each layer even in the wiring of the second or higher layer, and the wiring between the wirings of the same layer can be compared with the conventional one. The parasitic capacitance can be reduced. In addition, the second
Since the insulating film is included, the parasitic capacitance between wirings of different layers can be reduced. Therefore, it is effective for high-speed operation of the semiconductor device.

As described above, according to the present invention, it is possible to reduce the parasitic capacitance between wirings even if the wiring is multilayered, and it is possible to cope with finer wiring and multilayer wiring than ever before.

Next, a second embodiment will be described. FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention. In this embodiment, the Al film wirings 2 and 8 are surrounded by aluminum nitride films 10a and 10b, respectively. By enclosing the Al film wiring with an aluminum nitride film (protective film), the resistance against electromigration etc. when a large current is applied to the Al film wiring is increased, and the reliability of the wiring is further improved as compared with the first embodiment. Is.

In the present embodiment, A of the first layer and the second layer
After forming the film wirings 2 and 8, using a lamp annealer or the like, in a nitrogen or ammonia atmosphere, 300 to 450 ° C.
The surface of the Al film wirings 2 and 8 is nitrided by heating to
This is the same as the first embodiment except that the aluminum nitride films 10a and 10b are formed to have a thickness of 1 to 50 nm. As the protective film, an aluminum oxide film may be formed by heating in an oxygen atmosphere instead of the above-mentioned aluminum nitride film.

Next, a third embodiment will be described. FIG. 3 is a sectional view of a semiconductor chip showing a third embodiment of the present invention. In this embodiment, the Al film wirings 2 and 8 are surrounded by silicon oxide insulating films 11a and 11b (protective films), respectively. 5 silicon oxide insulating films 11a and 11b are formed by plasma CVD using silane and nitrous oxide or tetraethoxysilane and oxygen.
By forming a thickness of 0 to 200 nm, the reliability of the Al film wirings 2 and 8 can be improved. Both the structures of the second and third embodiments are effective in improving the reliability of the Al film wiring. However, when the distance between the Al film wirings becomes small, the space 6 between the wirings in the third embodiment becomes silicon oxide based. Since it is filled with the insulating film, the effect of reducing the parasitic capacitance between the wirings decreases. Whether to use the second or third embodiment may be freely determined depending on the semiconductor device.

The type of the protective film surrounding the Al film wiring may be changed for each layer, that is, the first layer is an aluminum nitride film and the second layer is a silicon oxide insulating film.

Next, a fourth embodiment will be described with reference to the drawings. FIG. 4 is a sectional view of a semiconductor chip showing a fourth embodiment of the present invention. In the present embodiment, when the distance between the Al film wirings is large, for example, 5 μm or more, the Al film wiring is used to support the sparse second insulating film (5) and the dense third insulating film (7). This is a structure using a dummy wiring 12 between them. If, for example, an Al film is used as the dummy wiring and the dummy wiring 12 is formed when the first-layer Al film wiring 2 is formed, the structure of this embodiment can be easily realized. By using the dummy wiring between the wirings of the predetermined layer as in this embodiment,
Even if there is a space, a semiconductor device having sufficient strength can be manufactured. It goes without saying that the dummy wiring can be formed at any position.

Next, a fifth embodiment will be described with reference to the drawings. FIG. 5 is a schematic diagram of a semiconductor manufacturing apparatus used for manufacturing of the present invention. In this semiconductor manufacturing apparatus, for example, the steps from the step of forming the ice film 3 on the Al film wiring 2 to the step of forming a dense insulating film in the first embodiment can be performed in the same apparatus. .

This apparatus comprises an interlock chamber 20 for loading / unloading wafers, an ice film forming chamber 22, a purge chamber 24 for evaporating an ice film, a CVD chamber 23 for forming a sparse insulating film and a dense film. And a transfer chamber 21 having a transfer robot for transferring wafers and valves 19-1 to 19-5, and the transfer chamber 21, the CVD chamber 23, and the purge chamber 24.
Etc. are designed to have a low temperature of 0 ° C. or lower.

A method for carrying out the present invention using this apparatus will be described below. First, after forming the Al film wiring 2 of the first layer, the wafer is put into the interlock chamber 20 and then put into the ice film forming chamber 22 via the transfer chamber 21. As described in the first embodiment, the wafer is rotated at a low temperature of 0 ° C. or lower while dripping water to form an ice film on the surface of the wafer.
The wafer is put into the purge chamber 24 via the transfer chamber 21 while being cooled to, for example, −10 to −20 ° C. By adjusting the temperature to 0 to -10 ° C. and reducing the pressure to several Torr, water vapor is removed from the ice film surface as water vapor, and the ice film is removed until the surface of the Al film wiring of the first layer is exposed. .

Next, the wafer is cooled to −10 to −20 ° C. and transferred to the CVD chamber 23 via the transfer chamber 21. By heat treatment, a sparse silicon oxide insulating film having a volume contraction of 3% or more is formed. Next, while cooling the wafer, it is put into the purge chamber 24 via the transfer chamber 21. Temperature 20
By raising the temperature to 200 ° C. or reducing the pressure, the ice film is evaporated as water vapor to form a space between the Al film wirings. Then, the wafer is transferred to the CVD chamber 23 via the transfer chamber 21. Therefore, a dense silicon oxide insulating film is formed.

As described above, by performing a series of steps in the same manufacturing apparatus, the ice film is not melted during the steps, and a semiconductor device having good reproducibility and high reliability can be realized.

In this embodiment, the CVD chamber for forming the sparse insulating film and the dense insulating film is described as the same chamber, but they may be provided in different chambers. Similarly, although the step of removing the ice film until the Al film wiring is exposed and the step of removing it as water vapor are performed in the purge chamber, they may be performed in separate chambers.

Although the embodiments of the present invention have been described above, it goes without saying that Al-Cu-Si is used as the wiring material in addition to Al, but metals such as W, Mo, Cu, etc., or silicides, etc. The effect of the present invention does not change even if the above material is used.

In the embodiment, water is used as the liquid and an ice film is used as the solid film, but other liquids such as alcohol may be used. Further, the sparse insulating film and the dense insulating film are described as the silicon oxide insulating film, but other insulating films may be used.

Although the embodiment of the present invention has been described with a two-layer wiring structure, the present invention may be applied to a one-layer structure or a structure having two or more layers.

[0037]

As described above, according to the present invention, by forming a space between the wirings in the same layer, there is no space in the portion where the layers of the wirings overlap each other as in the case of the multilayer wiring. This also solves the problem, further reduces the parasitic capacitance between the wirings, and has the effect of further increasing the speed of the semiconductor device.

[Brief description of drawings]

FIG. 1A is a view for explaining a first embodiment of the present invention.
It is a process sectional view divided and shown in (e).

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a third embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor chip for explaining a fourth embodiment of the present invention.

FIG. 5 is a schematic diagram of a semiconductor manufacturing apparatus for explaining a fifth embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor chip for explaining a conventional technique.

[Explanation of symbols] 1 silicon oxide film 2 first layer Al film wiring 3 ice film 4 water vapor 5 sparse silicon oxide insulating film 6 space 7, 7a, 7b dense silicon oxide insulating film 8 second layer Al Film wiring 9 Cover film 10, 10a, 10b Aluminum nitride film 11, 11a, 11b Silicon oxide type insulating film 12 Dummy wiring 13 SOG film 14, 15 Silicon oxide film 16 Contact 17 Silicon oxide film 18 Silicon nitride film 19-1 to 19 -5 valve 20 interlock chamber 21 transfer chamber 22 ice film forming chamber 23 CVD chamber 24 purge chamber

Claims (6)

[Claims] 1. A plurality of wirings in the same layer formed by selectively covering the surface of a predetermined first insulating film of a semiconductor substrate, and a sparse second insulating film covering the surface of the wiring. A dense third insulating film covering the surface of the second insulating film, and a space between the wirings. 2. The semiconductor device according to claim 1, wherein a surface and a side surface of the wiring are covered with a protective film. 3. The semiconductor device according to claim 1, wherein a dummy wiring on the same layer as the wiring is provided. 4. A step of selectively covering the surface of a first insulating film which covers the surface of a semiconductor substrate to form a plurality of wirings in the same layer, and a predetermined liquid is supplied while cooling the semiconductor substrate. Forming a solid film on the surface of the first insulating film selectively covered with the wiring by solidifying the solid film, and thinning the solid film to expose the surface of the wiring.
A space is provided between the wirings by a step of depositing a sparse second insulating film on the entire surface, a step of evaporating the solid film under heating or reduced pressure, and a step of depositing a dense third insulating film. A method of manufacturing a semiconductor device, comprising: 5. A step of selectively covering the surface of a first insulating film that covers the surface of a semiconductor substrate to form a plurality of wirings in the same layer, and a protective film that covers at least the surface and side surfaces of the wirings. And a step of forming a solid film on the surface of the first insulating film at least selectively covered with the protective film by supplying and solidifying a predetermined liquid while cooling the semiconductor substrate, Thinning the film to expose the surface of the protective film on the surface of the wiring, depositing a sparse second insulating film over the entire surface, and evaporating the solid film under heating or reduced pressure, A method of manufacturing a semiconductor device, characterized in that a space is provided between the wirings by a step of depositing a dense third insulating film. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the solid film to the step of depositing the third insulating film are performed in the same manufacturing apparatus.