JPH0744520B2 - Line monitoring device - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is used in digital communications. In particular, the present invention relates to an active backup switching technology for communication lines.

[0002]

2. Description of the Related Art In digital communication, during maintenance of a working line or when the working line deteriorates due to fading, etc., it is switched to a protection line, and when the working line is restored, the protection line is switched to the working line again. The line is maintained and maintained.
Since no interruption should occur in the information bit transmitted at the time of such switching, a non-interruptive synchronization switching method for performing non-interruptive synchronous switching is adopted. Further, a parity monitoring method is used in which a parity bit calculated by the transmitting side is compared with a result of parity calculation performed by the receiving side for each frame in order to monitor the line state.

A frame structure of a data signal sequence used for digital communication will be described with reference to FIG. FIG. 2 is a diagram showing a frame structure of a data signal sequence. In FIG. 2, the information bit DATA to be transmitted has a frame synchronization bit F and an auxiliary signal transmission bit S multiplexed at the working transmission end, and a parity operation for accumulating the multiplexed data signal sequence for each frame. The parity bit P is multiplexed and then transmitted on the working line. Similarly, also at the spare transmission end, the frame synchronization bit F and the auxiliary signal transmission bit S are multiplexed with the same information bit DATA as the working line, and parity calculation is performed on the multiplexed data signal sequence. , And the parity bit P is transmitted on the protection line after being multiplexed. At this time, the information bits P transmitted on the working line and the protection line are the same signal, but the auxiliary signal transmission bits S multiplexed at the working transmission line and the protection transmission line are on the working line or the protection line. Since the independent control information is inserted, it becomes the symmetry of the parity operation.
The data signal sequence of the frame does not always match at the working sending end and the backup sending end. Therefore, the data signal sequences transmitted on the working line and the protection line do not necessarily match except for information bits.

A conventional device will be described with reference to FIG. FIG. 3 is a block diagram of a conventional device. In FIG. 3, the data signal sequence 101 transmitted on the working line is transmitted via the working line input terminal 13 to the working line frame synchronization circuit 11
To the data signal sequence 20 after the frame synchronization has been established.
1 and the frame pulse 301 are output. Similarly, the data signal sequence 102 transmitted on the protection line is transmitted via the protection line input terminal 14 to the protection line frame synchronization circuit 12
To the data signal sequence 20 after the frame synchronization has been established.
2 and the frame pulse 302. In the non-instantaneous-interruption synchronization switching circuit 2, the working line frame synchronization circuit 11
Is a circuit for switching the data signal sequence 201 and the frame pulse 301 output from the backup line frame synchronization circuit 12 and the data signal sequence 202 and the frame pulse 302 output from the protection line frame synchronization circuit 12 without interruption.
1 and the frame pulse 501 are output. The parity calculation circuit 3 is a circuit that calculates the data signal sequence 401 output from the hitless synchronization switching circuit 2 for each frame based on the frame pulse 501 and outputs a calculation result 601. The parity bit extraction circuit 4 extracts, from the data signal sequence 401, the parity bit inserted at the sending end based on the frame pulse 501 output from the hitless synchronization switching circuit 2.
The parity bit 701 is output. The comparison circuit 5 outputs the parity bit 7 output from the parity bit extraction circuit 4.
01 and the operation result 60 output from the parity operation circuit 3
1 is compared, and if they do not match, an error pulse 801 is output to monitor the quality of the line selected by the hitless synchronous switching circuit 2.

[0005]

In such a line monitoring apparatus, when the auxiliary signal transmission bit transmitted on the working line and the protection line is different, the working line or the protection line is switched by the hitless synchronous switching circuit. Although the information bits can be switched without error, the target data to be integrated in each frame by the parity operation circuit may be switched in the middle of the frame, so the correct parity operation result cannot be obtained, and there is no interruption synchronization switching. An erroneous error pulse is output every time the circuit is switched.

The present invention has been made against such a background, and the line quality monitoring parity calculation result is inserted into the frame synchronization bit position after the frame synchronization is established and transferred, and the non-instantaneous synchronization switching is performed. It is an object of the present invention to provide a line monitoring device which eliminates the generation of an erroneous parity error pulse at the time of switching by extracting the result later.

[0007]

DISCLOSURE OF THE INVENTION The present invention provides a working line input terminal to which a working line for digital communication is connected, a protection line input terminal to which a protection line is connected, and a working line input terminal and a protection line input terminal. From the active line frame synchronization circuit and the standby line frame synchronization circuit, which establish the frame synchronization of the data signal sequence input from, respectively, and the output signals of the active line frame synchronization circuit or the standby line frame synchronization circuit are momentarily interrupted according to the switching control signal. The line monitoring device includes a non-instantaneous-interruption-synchronization switching circuit that switches without a switch and an error detection unit that detects an error from the output signal and outputs error information.

Here, a feature of the present invention is that the error detecting section is provided for each of the working spares on the input side of the hitless synchronization switching circuit, and the error information of the error detecting section is output to the output. It is provided with means for inserting into each signal, and further with means for extracting the error information from the selection output signal of the hitless synchronization switching circuit.

It is preferable that the inserting means includes a means for inserting the error information into a frame synchronization bit position of the data signal sequence.

The extracting means preferably includes means for deleting the error information from the frame synchronization bit position.

It is preferable that the arithmetic logic means of the error detecting section includes means for accumulating error detection information for a large number of frames arriving in time series.

[0012]

The parity of the signal on the working line is checked, for example, by the error detecting section dedicated to the working line. The parity of the signal of the protection line is checked by the error detection unit dedicated to the protection line.

As a result of the check, if an error is detected, the error detecting section outputs an error pulse. Upon receiving this error pulse, the comparison result insertion circuit inserts error information into the frame synchronization bit position of the signal on the working line or the signal on the protection line in which frame synchronization has been established.

The signal on the working line or the signal on the protection line is switched and output by the non-instantaneous-interruption synchronous switching circuit, and the inserted error information is extracted from the frame synchronization bit position of the output signal after this switching. To monitor the signal quality.

As a result, it is possible to prevent the parity information to be accumulated for each frame from being accumulated due to line switching and causing an error in the error detection result.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the device of the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

In the present invention, a working line input terminal 13 to which a working line for digital communication is connected, a protection line input terminal 14 to which a protection line is connected, and this working line input terminal 13
And a working line frame synchronization circuit 11 and a protection line frame synchronization circuit 12 for respectively establishing frame synchronization of the data signal sequence input from the protection line input terminal 14.
A non-instantaneous-interruption synchronization switching circuit 2 that switches the output signal of the working line frame synchronization circuit 11 or the protection line frame synchronization circuit 12 without interruption according to a switching control signal, and outputs an error information by detecting an error from the output signal. The line monitoring device includes error detection units 63 and 64.

Here, the feature of the present invention is that the error detecting sections 63 and 64 are provided for each of the working spares on the input side of the hitless synchronous switching circuit 2, and the error detecting sections 63 and 64 are provided. Comparison result insertion circuits 61 and 62 are provided as means for inserting the error information into the output signal, respectively, and further, the operation result extraction circuit 7 is provided as means for extracting the error information from the selected output signal of the hitless synchronization switching circuit 2. And the comparison result deleting circuit 10 is provided.

The comparison result insertion circuits 61 and 62 insert the error information into the frame synchronization bit positions of the data signal sequence. Further, the comparison result deletion circuit 10 deletes the error information from the frame synchronization bit position.

The arithmetic logic means of the error detectors 63 and 64 integrates the error detection information for a large number of frames that arrive in time series.

Next, the operation of the apparatus of the present invention will be described. In FIG. 1, a data signal sequence 101 transmitted on a working line is input to a working line frame synchronizing circuit 11 via a working line input terminal 13, and a frame synchronizing bit inserted at a working line sending end (not shown) is detected. After the frame synchronization is established, the data signal sequence 201 and the frame pulse 301 are output. Parity bit extraction circuit 4
Reference numeral 1 is a circuit for extracting the parity bit inserted at the active transmission end from the data signal sequence 201 based on the frame pulse 301 output from the active line frame synchronization circuit 11, and outputs the parity bit 701. The parity calculation circuit 31 performs a parity calculation by integrating the data signal sequence 201 for each frame based on the frame pulse 301 output from the working line frame synchronization circuit 11, and outputs a calculation result 601. The comparison circuit 51 compares the parity bit 701 output from the parity bit extraction circuit 41 with the operation result 601 output from the parity operation circuit 31, and outputs the comparison result 801 as an error pulse when they do not match. The comparison result insertion circuit 61 is a circuit for inserting the error information corresponding to the comparison result 801 output from the comparison circuit 51 into the frame synchronization bit position of the data signal sequence 201 after the frame synchronization is established. The data signal sequence 121 and the frame pulse 131 in which the error information corresponding to the comparison result 801 output from the comparison circuit 51 is inserted are output.

Similarly, the data signal string 102 transmitted on the protection line is also input to the protection line frame synchronization circuit 12 of the protection line receiving end 9 through the protection line input terminal 14, and after the frame synchronization is established, the data signal string is established. It is output as 202 and frame pulse 302. After that, the calculation result 602 output from the parity calculation circuit 32 that accumulates the data for each frame and performs the parity calculation and the parity bit extraction circuit 42 that extracts the parity bit inserted at the spare sending end (not shown) are output. Parity bit 70
2 is input to the comparison circuit 52, and the obtained comparison result 80
The error information corresponding to 2 is inserted by the comparison result insertion circuit 62 at the frame synchronization bit position of the data signal sequence 202 and the frame pulse 302 after the frame synchronization is established. The comparison result insertion circuit 62 outputs the data signal sequence 122 and the frame pulse 132 in which the error information is inserted.

The non-instantaneous-interruption synchronization switching circuit 2 includes the data signal sequence 121 and the frame pulse 131 output from the comparison result inserting circuit 61 of the working line receiving end 8 and the comparison result inserting circuit 62 of the protection line receiving end 9. The circuit that switches the output data signal sequence 122 and the frame pulse 132 of
The data signal sequence 151 and the frame pulse 161 in which the error information corresponding to the comparison result 801 or 802 output from the comparison circuit 51 or 52 is inserted in the bit position for frame synchronization are output. The calculation result extraction circuit 7 uses the frame pulse 16 output from the hitless synchronization switching circuit 2.
On the basis of 1, the error information corresponding to the comparison result 801 or 802 inserted by the comparison result insertion circuit 61 or 62 of the line selected by the hitless synchronous switching circuit 2 is extracted from the data signal sequence 151 as the error pulse 141. Output. The comparison result deleting circuit 10 detects the comparison result inserting circuits 61 and 6 from the data signal sequence 151 output to the subsequent device.
In 2, the error information inserted in the frame bit position is deleted.

[0024]

As described above, according to the present invention, since the result of independently detecting the quality states of the working line and the protection line is used, the auxiliary signal transmission bits transmitted on the working line and the protection line are different. Even in this case, an error pulse is not output at the time of switching, and the line selected by the non-instantaneous-interruption synchronous switching circuit can be monitored.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a frame configuration of a data signal sequence.

FIG. 3 is a block diagram of a conventional device.

[Explanation of Codes] 2 Non-interruption synchronization switching circuit 3, 31, 32 Parity operation circuit 4, 41, 42 Parity bit extraction circuit 5, 51, 52 Comparison circuit 61, 62 Comparison result insertion circuit 6, 63, 64 Error detection Part 7 Calculation result extraction circuit 8 Working line receiving end 9 Backup line receiving end 10 Comparison result deleting circuit 11 Working line frame synchronizing circuit 12 Working line frame synchronizing circuit 13 Working line input terminal 14 Working line input terminal 101, 102, 201 , 202, 401, 121,
122, 151 data signal sequence 141 error pulse 131, 132, 161, 301, 302, 501 frame pulse 601 operation result 701, P parity bit 801, 802 comparison result DATA information bit F frame synchronization bit S auxiliary signal transmission bit

Claims (4)

[Claims] 1. A working line input terminal to which a working line for digital communication is connected, a protection line input terminal to which a protection line is connected, and a data signal sequence input from the working line input terminal and the protection line input terminal. A working line frame synchronization circuit and a protection line frame synchronization circuit that respectively establish frame synchronization, and a non-instantaneous sync switching circuit that switches the output signal of the working line frame synchronization circuit or the protection line frame synchronization circuit according to a switching control signal without interruption. When,
In a line monitoring device including an error detection unit that detects an error from the output signal and outputs error information, the error detection unit is provided for each of the working spares on the input side of the hitless synchronization switching circuit. A circuit provided with means for inserting the error information of the error detection unit into the output signal, and means for extracting the error information from the selected output signal of the hitless synchronous switching circuit. Monitoring equipment. 2. The line monitoring device according to claim 1, wherein the inserting means includes means for inserting the error information into a frame synchronization bit position of the data signal sequence. 3. The line monitoring device according to claim 1, wherein the extracting means includes means for deleting the error information from a frame synchronization bit position. 4. The line monitoring apparatus according to claim 1, wherein the arithmetic logic means of the error detection unit includes means for accumulating error detection information for a large number of frames that arrive in time series.