JPH0743950B2 - Read circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit, and more particularly to a read circuit in a nonvolatile semiconductor memory device having a floating gate and capable of electrically writing and erasing.

[Conventional technology]

Conventionally, a circuit for reading an insulated gate field effect memory transistor (hereinafter referred to as a memory transistor), which is a nonvolatile semiconductor memory element having a floating gate and capable of electrically writing and erasing, has been used in other circuits such as a mask ROM and an EPROM. Similar to the memory, the information "1" or "0" is read by comparing with the reference voltage or the reference current generated by the reference voltage generating circuit.

[Problems to be solved by the invention]

The above-described conventional read circuit has a drawback in that there is no circuit compensation for variations in memory transistors at the time of manufacture and fluctuations at the time of use, and it is not stable for mass production such as occurrence of read defects. Such drawbacks are
In the future, it will become a big problem as the capacity and miniaturization of LSI further increase.

For this reason, a method of using a pseudo memory transistor in the reference voltage generation circuit has been considered, but the potential (initial value) of the floating gate at the time of manufacturing greatly changes depending on the degree of the electric field applied in the manufacturing process such as plasma etching. Since it is unstable, it has been abandoned because it is not suitable for use in a circuit that generates a reference voltage.

An object of the present invention is to provide a stable read circuit having a circuit-like compensating means against variations and fluctuations.

[Means for solving problems]

The circuit of the present invention is a read circuit in a non-volatile semiconductor memory device having an insulated gate field effect memory transistor having a floating gate and capable of electrically writing and erasing, as a memory element, and a minimum required for the memory element. Read / write circuit of the same configuration and a pseudo read / write circuit that supplies the read voltage of the pseudo memory element as a reference voltage for the read voltage of the memory element, and a set voltage in response to an external control signal. A reference voltage setting unit that outputs and a comparison unit that compares the reference voltage with the set voltage are provided in the same integrated circuit, and when setting the reference voltage, writing to the pseudo memory element is performed until they match in the above comparison. To operate the pseudo read / write circuit It

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a memory unit 1, a reference voltage generating unit 2, a reference voltage setting unit 3, two comparators 4 and 5 and a gate (NOR circuit) 6 are provided. It is housed in one semiconductor integrated circuit.

The memory unit 1 is composed of a memory element group, an address selection circuit, a read circuit, a write circuit, and other circuits that perform memory operations, and generates a read voltage V _A during a read operation. Comparator 4
Compares the read voltage V _A with the reference voltage V _R generated by the reference voltage generator 2 during the read operation, and outputs the output voltage V _O according to the result.

The reference voltage setting unit 3 functions only when setting the reference voltage V _R after manufacturing the semiconductor integrated circuit, and generates the setting voltage V _ION in response to the value of the control voltage V _G given from the outside. . The set voltage V _ION is compared with the reference voltage V _R by the comparator 5, and the result is fed back to the reference voltage generator 2 via the gate 6. The effect of the feedback is to set the value of the reference voltage V _{R to} the same value as the set voltage V _ION . Once set, the reference voltage V _R retains its value even when the control voltage V _G is removed, and is used for comparison with the read voltage V _R from the memory unit 1 as described above.

As shown in FIG. 2 (A), the memory unit 1 is a memory element M1 which is an insulated gate field effect transistor (hereinafter, field effect transistor is referred to as transistor) having a floating gate and capable of being electrically written and erased. And the transistor M2
And a memory drive circuit section consisting of M3 and a transistor M
Read voltage V _A consisting of 4, M5 and 2-input NOR circuit N1
And a transistor M6 that uses the write signal V _WR as the gate and the write voltage V _PP as the drain
And a write circuit section. Second
The figure shows only one memory element in order to avoid complication of the drawing. However, in reality, a large number of memory element groups and an address selection circuit for selecting a designated memory element from them are provided. Have.

As shown in FIG. 2 (B), the reference voltage generator 2 has the same configuration as the memory unit 1 for one memory element,
Each transistor in FIG. 2 (B) corresponds to that in FIG. 2 (A).
In FIG. 2A, each corresponding transistor is a pseudo transistor of the transistor marked with "D". The reference voltage generator 2 is shared by many memory devices.

Next, the operation of FIGS. 2 (A) and 2 (B) will be described.
Since both are basically the same, only FIG. 2 (A) will be described. In writing operation, the drive signals X and write signal V _WR is set to +25 volts, and the former only +25 volts during erase operation and the write enable signal W / E is set to both cases are both "H" level.

When writing "0", the write voltage V _{CG is set} to +25 V, +25 V is applied to the control gate formed on the floating gate of the transistor M1 via the transistor M3, and the write voltage V _{PP is set} to 0 V. As a result, the drain of the transistor M1 is set to 0 volt via the transistor M6. As a result, a high electric field is generated between the control gate and the drain, and electrons are injected from the drain to the floating gate by the FN tunnel current through the thin (100 angstrom) oxide film formed on the drain. In this way, electrons are injected into the floating gate, and even if the erase operation is completed, the floating gate maintains the state in which electrons are accumulated. The negative potential on the floating gate increases the threshold voltage seen by the control gate to +6 volts.

Next, write "1" as follows. The write voltage V _CG is 0 volt, the control gate of the transistor M1 is 0 volt via the transistor M3, and the write voltage V _CG is 0 volt.
_{With PP} at +25 volts, +25 volts is applied to the drain of transistor M1 via transistor M6. As a result,
Electrons are emitted from the floating gate to the drain, and the potential of the floating gate becomes positive. This causes the threshold voltage seen by the control gate to be -3 volts.

The erasing operation is the same as the above-described case of writing "0", and even if "1" is written, the "0" write state is forcibly entered. Further, the read operation is performed by setting the potential of the control gate to 0 volt and turning on / off the transistor M1 according to the threshold voltage value set by "0" writing and "1" writing as described above. To do.

When the transistor M1 is off, there is no current path between the transistors M5, M4, M2 and M1, so the read voltage V _A is the power supply voltage V _CC level, and when the transistor M1 is on, the read voltage V _A Becomes V _CC −α · I _ON . Here, α is a circuit constant determined by the conductance g _{m of the} transistor M4 and the gain of the NOR circuit N1.

The reference voltage generator 2 operates in conjunction with the memory unit 1 during the memory read operation, and the reference voltage V _R is applied to the transistor M1.
Determined by D ON current I _ON, but the operation stability on, the read voltage V _A of the transistor M1 is at the read voltage V _A and on the time of OFF
Most preferably, it is set to an intermediate voltage value of. For example, when operating with the power supply voltage V _DD = 5 V, the read voltage V _A is 5 V when the transistor M1 is off and 3 V when the transistor M1 is on, and the on-current of the transistor M1D is set so that the reference voltage V _R is 4 V. Control. In this case, if the on-current of the transistor M1 is 40 microamps, that of M1D is 20 microamps. As described above, the details of the above control are described in the memory unit 1 (FIG. 2 (A)).
Since the operation of the reference voltage generator and the operation of the reference voltage generator (FIG. 2 (B)) are the same, it can be understood from the above description of the operation of FIG. 2 (A). The control signal V _W2 is the output of the gate 6 in FIG.

The reference voltage V _R is set during initialization. To do so, first, the transistor M1D is erased in the same manner as for the memory section 1. Next, the reference voltage setting unit 3 is used.

As shown in FIG. 2 (C), the reference voltage setting unit 3 is composed of transistors MN1, MN2, MN3 and a NOR circuit NN3, among which a circuit composed of transistors NM2, NM3 and a NOR circuit NN3 and a NOR circuit NN3. The circuit NN3 has the same configuration as the read circuit in the memory unit 1 and the reference voltage generation unit 2.

After erasing the transistor M1D described above, in the reference voltage setting unit 3, for example, in the above example, the control signal V _G that turns on current of the transistor MN1 to 20 microamperes.
Is set to the read operation mode, and the set voltage V _ION and the reference voltage V _R are compared by the comparator 5. Since the transistor M1D is off, the reference voltage V _R is the power supply voltage V _CC level and V _R >> V _ION , and the output of the comparator 5 is set to the “L” level.

Next, write voltage V _E is 0 volt, and write voltage V _W1 is +25.
By setting the control signal V _W3 to the “L” level, the control signal V _W2 goes to the “H” level, so that the transistor M6D turns on and a high voltage is applied to the drain of the transistor M1D to start writing. The threshold voltage gradually decreases and the ON current I _ON of the reference voltage generator 2 increases. In setting the reference voltage V _R in this way, the control signal V _W3 causes the feedback route consisting of the reference voltage generator 2, the comparator 5 and the gate 6 in FIG. 1 to function, and the reference voltage V _W3 . After setting _R , it has a role to retain it.

When such writing and reading are repeated and the on-current I _ON in the reference voltage generating section exceeds 20 microamps for a bit, the output of the comparator 5 becomes “H” level, and the control signal V _W2 becomes “L” level, Therefore, the transistor M6D is turned off, the drain of the transistor M1D becomes 0 volt, and the writing is completed. In this way, the transistor M1D stops writing with the same on-current I _ON as the transistor MN1.

As a result, the setting operation of the reference voltage V _R is completed, so that the control signal V _W3 is returned to the “H” level and the memory unit 1
In reading, the binary information is detected by comparing the read voltage V _A with the reference voltage V _R.

In this embodiment, by adopting the reference voltage setting circuit 3 and the above-mentioned feedback circuit, the voltage of the floating gate, which was conventionally unstable depending on the degree of the electric field applied in the manufacturing process such as plasma etching, is circuitally compensated. However, as a result, since it changes in the same direction with respect to manufacturing variations and fluctuations during use, it is possible to use a pseudo memory that is originally suitable for generating a reference voltage.

If a depletion type transistor is provided in place of the transistor MN1 in the first embodiment, a constant on power supply I _ON can be obtained by setting the gate voltage to 0 volt.
Can be set to the transistor M1D.
Since the control signal V _G in the diagram (C) becomes unnecessary, there are advantages that the number of output pins can be reduced and the efficiency such as shortening the test time can be improved.

〔The invention's effect〕

As described above, according to the present invention, by using the pseudo memory transistor and providing the write / erase circuit capable of setting the on-current of the memory transistor, the on-current, that is, the reference voltage can be easily adjusted after manufacturing and stable reading can be performed. There is an effect that the operation can be realized.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows the details of the essential parts of this embodiment. 1 ... Memory section, 2 ... Reference voltage generating section, 3 ...
… Reference voltage setting unit, 4,5 …… Comparator, 6 …… Gate, M1 to M6, M1D to M6D, MN1 to MN3 …… Transistor, N
1, N1D, NN3 …… Noah circuit.

Claims (1)

[Claims] 1. A read circuit in a non-volatile semiconductor memory device having an insulated gate field effect memory transistor, which has a floating gate and is electrically writable and erasable, as a memory element, wherein the memory element and the minimum required for the memory element. A read / write circuit having the same configuration as that of the read / write circuit and a pseudo read / write circuit, which supplies a read voltage of the pseudo memory element as a reference voltage to the read voltage of the memory element, and responds to an external control signal. A reference voltage setting unit that outputs a set voltage and a comparison unit that compares the reference voltage with the set voltage are provided in the same integrated circuit, and when setting the reference voltage, the pseudo The pseudo read and write so as to write to the memory device A read circuit characterized in that the read circuit is operated.