JPH0743126A - Pattern inspection device - Google Patents

Abstract

PURPOSE:To make a comparison between the shapes of each pattern on a reference substrate and an inspected substrate, and between the coordinate positions of each pattern, and make judgement about the existence of a wiring pattern defect, based upon the results of both measurements. CONSTITUTION:A pattern inspection device has an X-Y stage 1, a CCD sensor 2, an image processing circuit 3, a frame memory 4, an adder 5, a matrix formation circuit 6, a shape storage memory 7, a shape register memory 8, a coordinate detecting circuit 8, a position storage memory 10, and a defect detecting circuit 11. In this device, the image of a reference substrate is picked up at a learning process, and the shape data of a specified pattern is stored in the memory 8. Also, the coordinate position of the data is stored in the memory 10. At an inspection process, the image of an inspected substrate is picked up, and the circuit 11 makes a comparison between the shape data of the reference substrate and the inspected substrate, as well as between the pattern coordinate positions of the reference substrate and the inspected substrate. When both measurement results agree to each other, the inspected substrate is judged to have no defect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a visual inspection of a wiring pattern on a printed circuit board, a photomask or the like.

[0002]

2. Description of the Related Art Conventionally, various pattern inspection apparatuses have been proposed for the purpose of inspecting the appearance of a wiring pattern on a printed circuit board or a photomask (see, for example, JP-A-60-501429). In this type of conventional pattern inspection apparatus, first, in a learning process, the shape of the wiring pattern of the reference board is coded and stored in a memory,
Next, in the inspection process, the shape of the wiring pattern of the inspected substrate is coded, the coded pattern is compared with the pattern stored in the memory in the learning process, and the inspected substrate has a defect only when the two do not match. The shape comparison method that determines A conventional pattern inspection apparatus using the shape comparison method will be described below with reference to FIGS.

First, the reference substrate K1 to be learned is optically imaged from the upper left corner to the lower right corner using an image pickup device such as a CCD to create two-dimensional image data. At this time, for example, as shown in FIG. 2, M × M (M = 5 in the figure) pixels Px, which are the minimum units of image data, are collected to form an element E.
And the element E is collected by N × N to form the processor Ps. Further, the gradation of the pixel Px located on the pattern Pn of the printed board is "1", and the gradation of the pixel Px located on the base material of the printed board is "0",
The value of the element E (hereinafter referred to as element data) when the sum of the gradations of all the pixels in the element E is larger than a predetermined threshold value is "1", and the element data when it is less than the threshold value is "0". To do. Then, for example, element data is sequentially output from the upper left element E of the processor Ps to the processor Ps.
The distribution of the element data is encoded (hereinafter, the encoded distribution of the element data is referred to as shape data). This shape data is stored in the shape storage memory 7. For example, in FIG. 5, at a position a1 where the processor Ps exists in the pad part of the pattern Pn, a position b1 where the processor exists in the part without the pattern, and a position c1 where the processor Ps exists in the line part of the pattern Pn,
The element E overlapping the pattern Pn is "1", and the other elements E are "0", and the illustrated element patterns a2, b2, c2 are extracted, and these are coded and stored in the shape memory memory 7. .

Next, in the inspection process, the CCD sensor 2 sequentially images the substrate K2 to be inspected from the upper left corner to the lower right corner, and the shape data of the substrate K2 to be inspected is created as in the learning process. Then, the shape data is compared with the shape data of the reference substrate K1 stored in the shape storage memory 7. For example,
Since the element pattern d2 when the processor Ps is located at the position d1 in FIG. 5B is equal to the element pattern a2 at the position a1 in FIG. 5A, it is determined that there is no defect at this position. Since there is a pattern defect e11 at the position e1 and the element pattern e2 including this defect is not stored in the shape memory memory 7 in the learning process, it is determined that the position e1 has a defect.

[0005]

In the conventional pattern inspection apparatus using the above-described shape comparison method, when the pattern which should exist in the dotted line portion f11 at the position f1 in FIG. 5 disappears, the element in this portion disappears. The pattern is f2. In this case, the position b where no pattern exists in the learning process
Since the same element pattern b2 is extracted in 1 and the pattern data corresponding to this is stored, the position f
It is determined that 1 has no defect, and the defect is overlooked.

An object of the present invention is to provide a pattern inspection apparatus capable of preventing a defect from being overlooked when the defect data is detected by comparing the respective shape data of the reference substrate and the inspection target substrate.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIG. 1 showing an embodiment. According to the present invention, a plurality of types of references are sequentially output by imaging a wiring pattern formed on a reference substrate. The shape data of the pattern is stored, the wiring pattern formed on the substrate to be inspected is imaged, the shape data of the inspection pattern that is sequentially output and the shape data of the stored reference pattern are sequentially compared, and the inspection target is inspected. A position detecting unit 9 which is applied to a pattern inspection apparatus for determining the presence or absence of a defect in a wiring pattern on a substrate and detects the position of each inspected pattern on the inspected substrate, and shape data of a plurality of types of reference patterns. The shape registration means 8 for registering the shape data of at least one kind of the specific pattern and comparing the shape data of the registered specific pattern with the shape data of the pattern to be inspected. Stores the position on the reference substrate specific pattern, position storage means for comparing the said stored position and a detected position by the position detecting means 9 10
The above-mentioned object can be achieved by including a determination means 11 for determining the presence or absence of a defect in the wiring pattern on the inspected substrate based on the comparison result of the shape registration means 8 and the comparison result of the position storage means 10. .

[0008]

The position of the specific pattern registered on the shape registration means 8 on the reference substrate is stored by the position storage means 10, and the stored position and the inspection pattern of each inspection pattern detected by the position detection means 9 are inspected. The position on the substrate is compared by the position storage means 10. Further, the shape registration means 8 compares the shape data of the pattern to be inspected with the shape data of the specific pattern registered in the shape registration means 8. The determination means 11 determines the presence or absence of a defect in the wiring pattern on the inspected substrate based on the comparison result of the position storage means 10 and the comparison result of the shape registration means 8.

Incidentally, in the section of means and action for solving the above-mentioned problems for explaining the constitution of the present invention, the drawings of the embodiments are used to make the present invention easy to understand. It is not limited to.

[0010]

FIG. 1 is a block diagram of an embodiment of the present invention. Reference numeral 1 is an XY stage for moving the reference substrate K1 or the inspected substrate K2 in a plane parallel to these surfaces.
Reference numeral 2 denotes a CCD sensor arranged above the XY stage, which picks up an image of a specific range of the substrate according to the movement of the substrate and outputs image data according to the brightness distribution thereof. The minimum unit of the image captured by the CCD sensor 2 is called a pixel. An image processing circuit 3 inputs image data output from the CCD sensor 2, and when the pixel is on the pattern Pn (copper foil) part, it is "1", and when it is on the substrate of the substrate, "0". It is converted into binary data and stored in the frame memory 4. In this way, the frame memory 4 stores the image data converted into “0” and “1” in pixel units (each is referred to as pixel information).
The contents of the frame memory 4 are updated every time a new image is taken by the CCD sensor 2.

Reference numeral 5 denotes an adder circuit, which collects M × M pieces of pixel information stored in the frame memory 4 in order to form an element E. The number of pieces of pixel information included in each element E is "1". When the number exceeds the predetermined threshold value, the value of the element E (element data) is set to "1", and if it is less than that, it is set to "0" and the data is output. For example, in FIG. 2, the element E is composed of 5 × 5 pieces of pixel information, and assuming that the threshold value is 12, if there are 13 or more pieces of pixel information “1” in the element E, the element data “1” is displayed. "" Is output, and if less than that, "0" is output. As the M × M pieces of pixel information forming the element E, M pieces of pixel information are used in the X-axis direction and the Y-axis direction at adjacent coordinate positions.

Reference numeral 6 denotes a matrix forming circuit, which collects N × N elements E located at adjacent coordinate positions to form a processor Ps, and N × N included in each processor Ps.
The value of each element E is output in parallel. For example, in the case of FIG. 2, if the X-axis and the Y-axis are set as shown in the figure, the matrix forming circuit 6 determines that the upper left corner of FIG.
The element data of is the most significant bit, and the lower right corner (X,
Each element data is output in parallel, with the element data at the position having a large Y coordinate) as the least significant bit. When the pixel Px in the shaded area in FIG. 2 is on the wiring pattern P on the substrate, the data output from the matrix forming circuit 6 is
It will be {0000000000000000011000110}. The output from the matrix forming circuit 6 is input to each address terminal of the shape memory 7 and the shape registration memory 8. The shape memory memory 7 is a 2 ^{N · N} bit RAM that can be written and read.
Composed of. When the output from the matrix forming circuit 6 is input to the address terminal of the shape memory 7 while the reference substrate K1 shown in FIG. 3 is being imaged, "1" is input to the data terminal as the data of the address. As a result, all the shape data of the reference substrate K1 is stored in the shape storage memory 7.

Reference numeral 8 denotes a shape registration memory in which shape data of a specific shape on the reference substrate K1 is stored in advance, and is composed of a read-only 2 ^{N · N-} bit ROM. In the shape registration memory 8, a value obtained by converting an element pattern of a specific shape to be a defect inspection target into shape data by the matrix forming circuit 6 is input to an address terminal, and "1" is stored as data of the address. It The storage in the shape registration memory 8 is performed prior to the learning process. For example, when the element pattern of FIG. 2 is the target of the defect inspection, the data "1" is stored at the address {0000000000000000011000110}. Reference numeral 9 is a coordinate detection circuit, which is X-
The coordinate values of the reference substrate K1 or the inspected substrate K2 output from the Y stage 1 are input, coded and output. As a method of this coding, for example, the coordinate values of X and Y of the coordinate (X, Y) are represented by L bits, and a 2 ^L·L bit code is used.

Reference numeral 10 is a position storage memory for storing the coordinate position of the shape data stored in the shape registration memory 8. The output from the coordinate detection circuit 9 is input to its address terminal, and the shape registration is made to the data terminal. The output from the memory 8 is input. In this position storage memory 10, a signal coded according to the coordinate value sequentially output from the coordinate detection circuit 9 is used as an address, and as the data of this address,
Data output from the shape registration memory 8 "0" or "
1 ”is stored. 11 is a defect determination circuit, which is based on the shape comparison result output from the shape registration memory 8 and the position comparison result output from the position storage memory 10.
It is determined whether the pattern Pn has a defect. Specifically, the output from the shape registration memory 8 and the position storage memory 10
The exclusive OR with the output from is calculated, and when the calculation result is "1", it is determined as a defect.

Next, defect inspection by the apparatus of this embodiment will be described with reference to FIGS. 3 and 4. First, the learning process will be described with reference to FIG. FIG. 3 shows an example of imaging the pad portion of the pattern Pn. The 5 × 5 squares shown in FIG. 3 represent one unit of the processor Ps, and in this example, the processor Ps is composed of 5 × 5 elements E. In FIG. 3, the processor Ps scans the reference substrate K1 and takes in the shape data of the reference pattern. For example, focusing on the positions A, B, and C, the matrix forming circuit 6
From these, the same shape data {0000000000011100111001110} of the element pattern ADR1 is output to the shape memory memory 7 and the shape registration memory 8. Figure 3
In the example, since the shape data at positions A, B, and C are all the same, the shape memory memory 7 stores the address {0000000000011
The data “1” is stored in 100111001110}.

On the other hand, the shape registration memory 8 shown in FIG.
Address prior to the learning process {00000000000111001110011
If the data "1" is stored only in 10}, the element pattern A is added to the address terminal of the shape registration memory 8.
When the shape data of DR1 is input, the shape registration memory 8
Outputs data "1". That is, whether the processor Ps is at any of the positions A, B, and C, the shape registration memory 8
Outputs data "1". The output "1" from the shape registration memory 8 is input to the data terminal of the position storage memory 10, and at the address terminal thereof, when the processor Ps is at the position A, the value obtained by coding the coordinates (X1, Y1), Coordinates (X3, Y1) when the processor Ps is at the position B
When the processor Ps is located at the position C, the coded values of the coordinates (X2, Y2) are input. Thus, in the example of FIG. 3, the positions A, B, C
Each coordinate position of is encoded and stored in the position storage memory 10.

Next, the operation of the inspection process will be described with reference to FIG. The inspected substrate K2 which is the inspection target shown in FIG.
In comparison with the reference substrate K1 of No. 3, the pad disappears at the position C, and a part of the pad is missing at the position D. First, when the processor Ps is at the position A, the matrix forming circuit 6 causes the positions A, B, and
The same data {0000000000011100111001110} as the shape data of the element pattern ADR1 in C is output.
Since "1" is registered in the shape registration memory 8 as the data of the address corresponding to the element pattern ADR1, the shape registration memory 8 is located at the position A of the inspected substrate K2.
The data "1" is output to the position storage memory 10 and the defect determination circuit 11. At this time, a value obtained by coding the coordinates (X1, Y1) of the position A is input to the address terminal of the position storage memory 10. Since the data "1" has been stored in the address of the position storage memory 10 in the previous learning step, the position storage memory 10 outputs the data "1" to the defect determination circuit 11. Since the data “1” is input to the defect judgment circuit 11 from both the shape registration memory 8 and the position storage memory 10, their exclusive OR is “1”.
It becomes 0 ″, and as a result, it is determined that the position A has no defect in the pattern Pn.

When the processor Ps is at the position C, since there is no pattern Pn at this position, the shape data {0 of the element pattern ADR2 is sent from the matrix forming circuit 6.
000000000000000000000000} is output. However, since the data "1" is not stored in that address of the shape registration memory 8, the data "1" is not stored in the shape registration memory 8.
0 "is output. Further, a coded value of the coordinates (X2, Y2) of the position C is input to the address terminal of the position storage memory 10. Since "1" is stored in the learning process, data "1" is output from the position storage memory 10. Therefore, in the defect determination circuit 11, the exclusive OR is "1".
1 ″, and it is determined that the position C has a defect in the pattern Pn.

When the processor Ps is at the position D where the Y coordinate is slightly larger than the position B (see FIG. 3), the reference substrate K1.
The shape data {0000000000011100111001110} of the same element pattern ADR1 as the position B of
Since it is input to the shape registration memory 8, “1” is output from the shape registration memory 8. Further, the address terminal of the position storage memory 10 is input with a value obtained by coding the coordinates (X3, Yd) of the position D. Since "1" is not stored at that address of the position storage memory 10 when the reference substrate K1 is imaged, "0" is output from the position storage memory 10. Therefore, in the defect judgment circuit 11, the exclusive OR is "
1 ", which determines that the position D has a defect in the pattern Pn.

As described above, in the above embodiment, the shape registration memory 8 compares the shape data of a specific pattern, and the position storage memory 10 compares the coordinate position of the pattern. If the values do not match, it is determined that the inspected substrate K2 has a defect. Therefore, at the coordinate position where the shape data of the reference substrate K1 is created, the pattern disappears on the inspected substrate K2 and there is no corresponding pattern,
Defects can be detected even when the pattern of the registered shape is present on the inspected substrate K2 at a position other than the coordinate position where the shape data of the reference substrate K1 is created, and it is possible to detect defects that cannot be detected by the shape comparison method. The accuracy of defect detection of the pattern Pn is improved by using the conventional shape comparison method together. The specific pattern to be inspected is registered in the shape registration memory 8. For example, only the shape data of a specific portion such as the pad portion of the pattern Pn or the branch portion of the pattern Pn is stored.

In the above embodiment, the shape of the pad portion of the pattern Pn is registered in the shape registration memory 8 as a specific pattern and the coordinate positions thereof are stored in the position storage memory 10, respectively. A plurality of registration memories for storing patterns may be prepared, and these registration memories may be operated in parallel. Also,
In the above embodiment, the number of pixels forming the element E and the number of elements E forming the processor Ps are both 5 × 5.
The unit of s is not limited to this. In the above embodiment, the addition circuit 5 determines whether each element E is "0" or "1", and the matrix formation circuit 6 outputs N × N element data in parallel. May be performed by hardware using a logic IC or the like, or may be performed by software.

[0022]

As described above in detail, according to the present invention, the shape data of the specific pattern on the reference board is registered, and the registered shape data and the shape data of the pattern to be inspected on the board to be inspected. To compare the position of the shape data of the specific pattern with the position of the pattern to be inspected on the board to be inspected, and to detect the presence or absence of a defect in the wiring pattern based on the comparison result of both, simply When only these are compared, it is possible to detect a defect that was missed by comparing the positions of the shape data, and the accuracy of defect detection of the wiring pattern is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a pattern inspection apparatus according to the present invention.

FIG. 2 is a diagram illustrating pixels, elements, and a processor.

FIG. 3 is a diagram illustrating an operation in a learning process of the pattern inspection apparatus of FIG.

FIG. 4 is a diagram illustrating an operation in an inspection process of the pattern inspection apparatus of FIG.

FIG. 5 is a diagram illustrating an operation of a conventional pattern inspection device.

[Explanation of symbols]

 1 XY Stage 2 CCD Sensor 3 Image Processing Circuit 4 Frame Memory 5 Addition Circuit 6 Matrix Forming Circuit 7 Shape Storage Memory 8 Shape Registration Memory 9 Coordinate Detection Circuit 10 Position Storage Memory 11 Defect Judgment Circuit

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Claims (1)

[Claims] 1. A wiring pattern formed on a reference substrate is imaged and the shape data of a plurality of types of reference patterns that are sequentially output are stored, and the wiring pattern formed on the inspected substrate is imaged and sequentially output. In the pattern inspection apparatus for sequentially comparing the shape data of the inspected pattern and the stored shape data of the reference pattern to determine the presence or absence of a defect in the wiring pattern on the inspected substrate, each of the inspected patterns Of position detection means for detecting a position on the substrate to be inspected, and shape data of at least one type of specific pattern among the shape data of the plurality of types of reference patterns, and the registered specific pattern. Shape registering means for comparing the shape data of the target pattern with the shape data of the pattern to be inspected, and the position of the specific pattern on the reference substrate is stored. At the same time, based on the comparison result of the shape registration means and the comparison result of the position storage means, a position storage means for comparing the stored position with the position detected by the position detection means, A pattern inspecting device, comprising: a determining unit that determines whether or not there is a defect in a wiring pattern on a substrate.