JPH0740211B2 - Constant current circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a constant current circuit, for example, a MOSF circuit.
The present invention relates to a technique effectively used for a constant current circuit which is composed of an ET (insulated gate type field effect transistor) and forms a positive and a negative constant current whose current values are equal in absolute value.

[Background technology]

When using MOSFETs to form positive and negative constant currents that are equal in absolute value, the constants of the N-channel MOSFET and P-channel MOSFET that flow the constant current are designed from circuit operation simulation, and based on the measured results of the prototype, The ratio of MOSFET constants (channel width W / channel length L) was adjusted. However, it is extremely difficult to obtain the same positive and negative constant currents under the influence of process fluctuations and temperature fluctuations. The constant current circuit as described above is required, for example, in an automatic equalizer for digital telephones and a loop filter of a PLL (phase locked loop) circuit.

Therefore, the inventor of the present application considered making the current values of the positive and negative polarities equal by using a negative feedback circuit using a differential amplifier circuit.

As an example of a constant current circuit using a differential amplifier circuit,
There is JP-A-55-59515.

[Object of the Invention]

An object of the present invention is to provide a constant current circuit capable of obtaining a positive and negative polar constant currents whose current values are equalized with high accuracy.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the first conductive first M having a drain connected to the resistance means.
The drain of the first MOSFET is connected to the OSFET and the non-inverting input terminal, the constant voltage is supplied to the inverting input terminal, and the differential output voltage is connected to the gate of the MOSFET. And a first differential amplifier circuit for converting the current flowing through the resistance means into a constant current with the constant voltage as a reference, and a first conductive circuit having a gate and a source respectively connected to the gate and the source of the first MOSFET. Type second MOSFET, a second conductivity type third MOSFET having a drain connected to the drain of the second MOSFET, a non-inverting input terminal to which the drain of the third MOSFET is connected, and an inverting input terminal to the second, The midpoint voltage of the power supply voltage supplied between the sources of the third MOSFET is supplied, and the differential output voltage is
A second differential amplifier circuit coupled to be supplied to the gate of the 3MOSFET, and a gate and a source connected to the gate and the source of the second MOSFET, respectively, for forming a first constant current from the drain. First conductivity type fourth MOSFET
And a second conductivity type fifth MOSFET having a gate and a source respectively connected to the gate and the source of the third MOSFET and forming a second constant current from the drain.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a constant current circuit according to the present invention. Although not particularly limited, each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N-channel MOSFET
Is a gate electrode made of polysilicon formed through a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region and between the source region and the drain region. Composed of. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of N channel MOs formed thereon.
Configure a common substrate gate for SFETs. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the N-channel MOSFET, that is, the semiconductor substrate is set to the ground potential of the circuit, and the P-channel MO
The substrate gate of the SFET, that is, the N-type well region, is coupled to the power supply terminal Vcc in FIG.

The N-channel MOSFET Q1 forms a reference constant current I1. That is, the fixed resistance R is provided between the drain of the MOSFET Q1 and the power supply voltage Vcc, although not particularly limited thereto.
The drain voltage of the MOSFET Q1 is supplied to the non-inverting input terminal (+) of the differential amplifier circuit (operational amplifier circuit) OP1. A constant voltage Vcc-Vref, for example, is supplied to the inverting input terminal (-) of the differential amplifier circuit OP1. The output voltage of the differential amplifier circuit OP1 is supplied to the gate of the MOSFET Q1. In the operational amplifier circuit OP1, the drain voltage of MOSFET Q1 is
Supply MOSFET with output voltage equal to cc-Vref
Controls the conductance of Q1. For example, when the voltage drop (I1 × R) in the resistor R is higher than the constant voltage Vref, the output voltage of the differential amplifier circuit OP1 becomes low and the MOSFET Q1 is biased shallowly to reduce the current I1 and reduce the voltage drop in the resistor R. When (I1 × R) is lower than the constant voltage Vref, the output voltage of the differential amplifier circuit OP1 becomes high and the MOSFET Q1 is deeply biased to increase the current I1. Such a differential amplifier circuit
Due to the loop of the negative feedback by OP1, a constant current I1 as shown in the following equation (1) flows through the MOSFET Q1.

I1 = Vref / R (1) As described above, when the constant voltage Vref (Vcc-Vref) based on the power supply voltage Vcc is used for the inverting input terminal (-) of the differential amplifier circuit OP1, The constant current I1 can be made independent of the fluctuation of the power supply voltage Vcc.

The same voltage as that of the MOSFET Q1 is supplied to the gate of the N-channel MOSFET Q2, so that, for example, if the size (W / L) is the same as that of the MOSFET Q1, the same constant current I1 is caused to flow, or the equal ratio of both MOSFETs Q1 and Q2. According to the above, a constant current will flow. A P-channel MOSFET Q3 is connected in series to the drain of the MOSFET Q2. In order to make the current I2 flowing through this MOSFET Q3 equal to the constant current I1 flowing through the above MOSFET Q2, the drain of MOSFET Q3 (connection point between MOSFET QT3 and Q2)
The voltage is supplied to the non-inverting input terminal (+) of the differential amplifier circuit OP2 similar to the above. The midpoint voltage (Vcc / 2) of the operating voltage Vcc supplied between the sources of the MOSFETs Q2 and Q3 is supplied to the inverting input terminal (-) of the differential amplifier circuit OP2.

Due to the negative feedback effect of the differential amplifier circuit OP2 provided in the MOSFET Q3, the current I2 of the MOSFET Q3 is the constant current of the MOSFET Q2.
Balance to be equal to I1. For example, both currents
In the relation of I2> I1, the drain voltage of the MOSFET Q3 is made higher than the midpoint voltage Vcc / 2, so that the output voltage of the differential amplifier circuit OP2 is made higher. As a result, P-channel MOSFET Q3
Is shallowly biased, which reduces its drain current I2. On the other hand, if both currents have a relation of I1> I2, the above MOSF
Since the drain voltage of ETQ3 is made lower than the midpoint voltage Vcc / 2, the output voltage of the differential amplifier circuit OP2 is made low. As a result, the P-channel MOSFET Q3 is deeply biased, so that its drain current I2 is increased. Due to the negative feedback operation of the differential amplifier circuit OP2, MOSFETs Q3 and Q3
The potential at the connection point of 2 (drain potential of MOSFETs Q2 and Q3) is always equal to the midpoint potential Vcc / 2 as the above reference. In other words, the current I2 flowing through the P-channel MOSFET Q3 flows through the N-channel MOSFET Q2. Control so that it becomes equal to the constant current I1.

Constant current formed by the above current balance circuit
I1 (= I2) is output via the N-channel output MOSFET Q4 and the P-channel MOSFET Q5, respectively. That is,
The N-channel output MOSFET Q4 has its gate commonly connected to MOSFETs Q1 and Q2, thereby
, And the output voltage of the differential amplifier circuit OP1 equal to the gate voltage of Q2 is supplied. The gate of the P-channel output MOSFET Q5 is commonly connected to the MOSFET Q3, so that the output voltage of the differential amplifier circuit OP2 equal to the gate voltage of the MOSFET Q3 is supplied. And MOSFETs Q2 and Q4
And the size ratio of MOSFETs Q3 and Q5 are set equal, the sink current (negative current) I1 ′ obtained from the drain of the MOSFET Q4 and the push current (positive current) I2 obtained from the drain of the MOSFET Q5 are set. ′ Can be set to the same current value as the MOSFETs Q2 and Q3 of the balance circuit.

[Embodiment 2] FIG. 2 shows a circuit diagram of an embodiment in which the present invention is applied to a minute voltage generating circuit.

In this example, to form positive and negative minute currents,
Compared to the N-channel MOSFET Q4 shown in FIG. 1, the N-channel MOSFETs Q4 ′ and Q4 ″ have a size of ΔW /
It is formed so that only L is different. That is, the size of the MOSFET Q4 'that forms the positive minute current + ΔI has the above-mentioned MO.
Compared to SFETQ4, it is smaller by ΔW / L, and a negative minute current −ΔI
MOSFET Q4 ″ for forming the
It is formed larger than ETQ4 by ΔW / L.

Further, in order to form these minute signals at required timing, the source of the P-channel MOSFET Q5 has a low level such as the ground potential of the circuit formed by the CMOS inverter circuit N3 which receives the timing signal ▲ ▼ and the power supply voltage Vcc. Such a high level is supplied. Further, the timing signal UP is received by the source of the MOSFET Q4 ′.
The same high level and low level of the CMOS inverter circuit N1 are supplied, and the same high level and low level of the CMOS inverter circuit N2 receiving the timing signal DW are supplied to the source of the MOSFET Q4 ″.

For example, when the timing signal (up signal) UP is set to the high level, the output signal of the inverter circuit N1 is set to the low level and the output signal of the inverter circuit N3 is set to the high level during that time, so that the currents in the MOSFETs Q5 and Q4 'are increased. I2 and I1 ′
(Note that MOSFETs Q3 and Q5 have the same size, MOSFET Q2
And the virtual MOSFET Q4 is the same size). Above MOSFET
Since the size of Q4 'is smaller by ΔW / L, the current I2 of the MOSFET Q5 (the virtual MOSFET Q4
Current I1) is less than. As a result, ΔI charges the capacitor C and raises its voltage Vc. On the other hand, when the timing signal (down signal) DW is set to high level,
During that time, the output signal of the inverter circuit N2 goes low,
Since the output signal of the inverter circuit N3 is set to the high level, the currents I2 and I1 ″ flow through the MOSFETs Q5 and Q4 ″, respectively.
Since the size of the MOSFET Q4 ″ is large by ΔW / L, it is larger than the current I2 of the MOSFET Q5 (current I1 of the virtual MOSFET Q4) by ΔI according to the size.
Discharges the capacitor C and reduces its voltage Vc.

If the timing signals UP and DW are generated according to the reference time, the voltage Vc controlled stepwise can be formed. Such a voltage can be used as a voltage signal for canceling the echo component of the line in an A / D or D / A conversion circuit or an automatic equalizer for digital telephones, for example.

[Third Embodiment] FIG. 3 shows a circuit diagram of an embodiment in which the present invention is applied to a loop filter (low-pass filter) LPP in a PLL circuit.

In this embodiment, the sizes of the N-channel output MOSFET Q4 and the P-channel output MOSFET Q5 in the constant current circuit are set so that the same current flows.
N-channel output MOSFET Q4 source has a phase comparison circuit PD
The output signal of the CMOS inverter circuit N1 which receives the down signal DW formed by
The source of Q5 is supplied with the output signal of the CMOS inverter circuit N3 that receives the up signal ▲ formed by the phase comparison circuit PD.

A capacitor C is provided between the connection point of the MOSFETs Q4 and Q5 and the ground potential of the circuit. The voltage VC held in the capacitor C is used as a control signal for the voltage controlled oscillator circuit VCO.

This voltage-controlled oscillator circuit VCO is set to a desired frequency, and its oscillation signal φo is 1 /
Divided to N. The phase comparison circuit PD is the frequency division circuit COUN
Phase difference between the output signal φo ′ and the reference frequency signal φr, in other words, an up-up and down signal DW having a pulse width according to the frequency difference is formed.

For example, if the phase of the divided output φo 'is delayed with respect to the reference frequency φr, in other words, the divided output φo'.
If the frequency of is decreased, the phase comparison circuit PD sets the up signal ▲ ▼ to low level. As a result, the P-channel MOSFET Q5 is activated during that time, and the constant current I as described above is supplied to the capacitor C, so that the control voltage VC is increased. As a result, the oscillation frequency φo of the voltage controlled oscillator circuit VCO is increased. On the other hand, if the phase of the frequency-divided output φo ′ advances with respect to the reference frequency φr, in other words, if the frequency of the frequency-divided output φo ′ is increased, the phase comparison circuit PD sets the down signal DW to the high level. To do. As a result, the N-channel MOSFET Q4 is activated during that time and the capacitor C is discharged by the constant current I as described above, so that the control voltage VC is lowered. As a result, the oscillation frequency φo of the voltage controlled oscillator circuit VCO is lowered. With the above operation, the transmission frequency φo can be set to a frequency N times the reference frequency φr. In this embodiment, the MOSF that forms the discharge current of the capacitor C is
MOSF that forms the current of ETQ4 and the charging current of capacitor C
Because the ETQ5 currents can be equal, there is no offset in the loop filter. This enables highly accurate PLL operation.

[Effect]

(1) Using a differential amplifier circuit, a first conductivity type constant current MOSF
By controlling the gate voltage of the second conductivity type MOSFET so that the drain voltage of the second MOSFET directly connected to ET becomes equal to the midpoint potential of the operating voltage, the current flowing through both MOSFETs is controlled. Can be equal by this,
Both positive and negative polarities are set to the same current value from the drain of the output MOSFET, which has the same size ratio as both MOSFETs and has a common gate, and is not affected by process variations and temperature fluctuations. It is possible to obtain the output current of

(2) As the first conductivity type constant current MOSFET, a differential amplifier circuit is used to control the gate voltage so that the drain voltage becomes a constant constant voltage to form a reference constant current. The effect that the negative constant current itself can be set with high precision is obtained.

(3) By making the drain voltage of the constant current MOSFET equal to the constant voltage with reference to the power supply voltage, it is possible to form a reference constant current irrelevant to fluctuations in the power supply voltage. .

(4) By forming the size of the one output MOSFET with a small difference from the size of the MOSFET for obtaining the same current, it is possible to obtain a small constant current according to the small difference. The effect is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in FIG. 1, the voltage supplied to the resistor R for forming the reference constant current may be a predetermined constant voltage other than the power supply voltage Vcc. The resistor R may be an external component of the semiconductor integrated circuit device. Further, the P-channel MOSFET and the N-channel MOSFET may be reversed. In this case, the polarity of the operating voltage may be reversed.

Further, the circuit for forming the reference constant current may be any circuit other than the circuit using the feedback circuit by the differential amplifier circuit.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention can be widely used as a circuit that forms a current having the same positive and negative polarities.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a constant current circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention applied to a voltage generating circuit, and FIG. FIG. 9 is a circuit diagram showing an example in which the present invention is applied to a PLL circuit. OP1, OP2 …… Differential amplifier circuit (arithmetic amplifier circuit), VCO …… Voltage control type oscillator circuit, COUN …… Dividing circuit, PD …… Phase comparator circuit, LPF / loop filter (low-pass filter)

Claims (1)

[Claims] 1. A first conductivity type first MOSFET (Q1) having a drain connected to a resistance means, a drain of the first MOSFET (Q1) connected to a non-inverting input terminal, and a constant voltage ( Vref) is supplied so that the differential output voltage is supplied to the gate of the MOSFET (Q1), and the constant voltage (Vr
ef) as a reference, a first differential amplifier circuit for making the current flowing through the resistance means a constant current, and a first conductive circuit having a gate and a source connected to the gate and the source of the first MOSFET (Q1), respectively. Second MOS of type
The FET (Q2), the second MOSFET of the second conductivity type having the drain connected to the drain of the second MOSFET (Q2) (Q3), the drain of the third MOSFET (Q3) is connected to the non-inverting input terminal, Connect the second and third MOSFETs (Q2 and Q2) to the inverting input terminal.
A second differential amplifier circuit coupled so that the midpoint voltage of the power supply voltage supplied between the sources of 3) is supplied and the differential output voltage is supplied to the gate of the third MOSFET (Q3); A fourth MOSFET (Q4) of the first conductivity type having a gate and a source respectively connected to the gate and the source of the second MOSFET (Q2) and for forming a first constant current from the drain.
And a second conductivity type fifth MOSFET (Q5) having a gate and a source respectively connected to the gate and the source of the third MOSFET (Q3) and forming a second constant current from the drain. Characteristic constant current circuit.