JPH0739250Y2 - Semiconductor structure - Google Patents

Semiconductor structure

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Publication number
JPH0739250Y2
JPH0739250Y2 JP1986132974U JP13297486U JPH0739250Y2 JP H0739250 Y2 JPH0739250 Y2 JP H0739250Y2 JP 1986132974 U JP1986132974 U JP 1986132974U JP 13297486 U JP13297486 U JP 13297486U JP H0739250 Y2 JPH0739250 Y2 JP H0739250Y2
Authority
JP
Japan
Prior art keywords
film
znse
zns
substrate
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1986132974U
Other languages
Japanese (ja)
Other versions
JPS6339961U (en
Inventor
有二 菱田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1986132974U priority Critical patent/JPH0739250Y2/en
Publication of JPS6339961U publication Critical patent/JPS6339961U/ja
Application granted granted Critical
Publication of JPH0739250Y2 publication Critical patent/JPH0739250Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【考案の詳細な説明】 (イ)産業上の利用分野 本考案は格子の不整合が原因となる転位の発生を抑制し
たGaAs上の無転位結晶薄膜を得ることができる半導体構
造を提供しようとするものである。
Detailed Description of the Invention (a) Field of Industrial Application The present invention intends to provide a semiconductor structure capable of obtaining a dislocation-free crystal thin film on GaAs in which generation of dislocations caused by lattice mismatch is suppressed. To do.

(ロ)従来の技術 現在、光を利用した情報の伝達、処理及び記録、再生技
術が重要な研究開発の題目となりつつあるのは周知の通
りであり、半導体レーザ、発光ダイオード及び固体又は
液体の発光素子等の研究が進められ、既に実用化の域に
達したものもある。
(B) Conventional technology It is well known that information transmission, processing and recording / reproducing technology using light is becoming an important research and development subject at present, and it is well known that semiconductor lasers, light emitting diodes and solid or liquid Research on light-emitting devices has been advanced, and some have already reached the stage of practical application.

これらの中で、早急に実用化が望まれるものに、青色発
光ダイオード(青色LED)がある。青色LED材料には、窒
化ガリウム(GaN)、炭化ケイ素(SiC)、セレン化亜鉛
(ZnSe)及び硫化亜鉛(ZnS)がある。これらの材料の
中で、GaN及びZnSは室温で2.7eV以上のバンド幅を有す
る直接遷移型バンド構造を持つため青色LEDだけでなく
紫外線まで発振可能な半導体レーザ材料として期待され
ている。
Among these, a blue light emitting diode (blue LED) is one that is urgently desired to be put into practical use. Blue LED materials include gallium nitride (GaN), silicon carbide (SiC), zinc selenide (ZnSe) and zinc sulfide (ZnS). Among these materials, GaN and ZnS are expected to be semiconductor laser materials capable of oscillating not only blue LEDs but also ultraviolet rays because they have a direct transition type band structure having a bandwidth of 2.7 eV or more at room temperature.

ところで、GaAs基板上にZnSe単結晶膜を成長する場合、
成長膜厚が150nmを越えるとGaAsとZnSeの格子不整合に
起因する転位がZnSe膜に発生する。
By the way, when growing a ZnSe single crystal film on a GaAs substrate,
When the grown film thickness exceeds 150 nm, dislocations occur in the ZnSe film due to the lattice mismatch between GaAs and ZnSe.

そこで、このような転位の発生を抑制するためにZnSeに
5%程度のSを添加して三元混晶ZnSe1−χSχ(χ
0.05)とすることによりGaAs基板と格子整合させる方
法、またはInを添加することによりZnSeと格子整合した
三元混晶InGaAsを基板として用いる方法等がある(例え
ば信学技報、SSD85-162、P59〜67参照)。
Therefore, in order to suppress the occurrence of such dislocations, about 5% of S is added to ZnSe to form a ternary mixed crystal ZnSe 1-χ Sχ (χ
0.05) to make a lattice match with a GaAs substrate, or a method of using a ternary mixed crystal InGaAs lattice-matched to ZnSe by adding In as a substrate (for example, IEICE Technical Report, SSD85-162, See P59-67).

(ハ)考案が解決しようとする問題点 上述の従来技術では成長膜と基板の結晶格子を整合させ
るために混晶を用いて行っていたが、 このような混晶を形成する上で組成比を正確に制御する
ことは困難である。
(C) Problems to be solved by the invention In the above-mentioned conventional technique, a mixed crystal was used to match the crystal lattices of the growth film and the substrate. However, in forming such a mixed crystal, the composition ratio Is difficult to control accurately.

本考案は上記欠点に鑑み為されたもので組成比の制御が
困難である格子整合した混晶を形成せずに、格子の不整
合が原因となる転位の発生を抑制したGaAs上のZnSe膜を
得ることができる半導体構造を提供しようとするもので
ある。
The present invention has been made in view of the above-mentioned drawbacks, and it is difficult to control the composition ratio.It does not form a lattice-matched mixed crystal and suppresses the generation of dislocations caused by lattice mismatch. It is intended to provide a semiconductor structure capable of obtaining

(ニ)問題点を解決するための手段 本考案はGaAs基板上に厚さ150nm以下のZnSe単結晶膜と
数原子層のZnSまたはZnSeS混晶を交互に積層してなる半
導体構造である。
(D) Means for solving the problem The present invention is a semiconductor structure in which a ZnSe single crystal film having a thickness of 150 nm or less and several atomic layers of ZnS or ZnSeS mixed crystal are alternately laminated on a GaAs substrate.

(ホ)作用 GaAs基板上に成長したZnSe膜は膜厚が150nm以下であれ
ば弾性限界内であり転位は発生しない。またZnSe膜はGa
Asより格子定数が大きく、ZnSe膜はGaAs基板より圧縮応
力を受けるがZnS、ZnSeSはZnSeより格子定数が小さいの
でZnS層またはZnSeS層をZnSe層中に挿入することによ
り、転位発生の原因となる圧縮応力を緩和することがで
き。
(E) Action The ZnSe film grown on the GaAs substrate is within the elastic limit and the dislocation does not occur if the film thickness is 150 nm or less. The ZnSe film is Ga
The lattice constant is larger than As, and the ZnSe film receives compressive stress from the GaAs substrate, but ZnS and ZnSeS have smaller lattice constants than ZnSe, so inserting a ZnS layer or ZnSeS layer into the ZnSe layer causes dislocations. Can relieve compressive stress.

(ヘ)実施例 第1図は本考案実施例の半導体構造の断面図であり、分
子線エピタキシー(MBE、Molecular Beam Epitaxy)を
用いて面方位(100)のGaAs基板上に成長させることに
より形成される。
(F) Example FIG. 1 is a cross-sectional view of a semiconductor structure of an example of the present invention, which is formed by growing on a GaAs substrate having a plane orientation (100) by using molecular beam epitaxy (MBE). To be done.

ここで、MEB法について以下に説明する。Here, the MEB method will be described below.

MEB法は10-10Torr以上の超高真空系内での取扱のため分
子の持つ平均自由行程は長く、噴出セルより発生した気
体分子は分子流となって基板に飛来する。基板に到達し
た分子は表面拡散ののち、他の分子と会合・結合し、基
板表面に捕捉され、堆積・成長する。会合・結合に寄与
しない分子は基板表面から脱離・再蒸発する。基板表面
に到達する分子の個数は分子線強度に等しく、分子線強
度は蒸発源の温度により一義的に決定される。また結晶
の成長速度、不純物濃度、多元化合物の組成比は分子線
強度により制御できる。
Since the MEB method is handled in an ultra-high vacuum system of 10 -10 Torr or more, the molecules have a long mean free path, and the gas molecules generated from the ejection cell fly to the substrate as a molecular flow. After reaching the substrate, the molecules diffuse on the surface and then associate and bond with other molecules to be trapped on the surface of the substrate for deposition and growth. Molecules that do not contribute to association / bonding are desorbed and re-evaporated from the substrate surface. The number of molecules reaching the surface of the substrate is equal to the molecular beam intensity, and the molecular beam intensity is uniquely determined by the temperature of the evaporation source. The crystal growth rate, the impurity concentration, and the composition ratio of the multi-component compound can be controlled by the molecular beam intensity.

第2図は一般的な分子線エピタキシャル成長装置の模式
図を示し、(4)はチャンバであって排気部(5)から
の超高真空排気によりその内は約10-10Torrに調整され
る。(1)はチャンバ(4)内に配置されたGaAs基板を
示し、抵抗加熱器(図示せず)によりその加熱量が調整
される。(6)(7)(8)は夫々Zn、Se及びZnSが入
れられた第1、第2、第3のセルを示し、夫々の温度が
可変設定されるようになっている。
FIG. 2 shows a schematic diagram of a general molecular beam epitaxial growth apparatus, in which (4) is a chamber, the inside of which is adjusted to about 10 −10 Torr by ultra-high vacuum exhaust from the exhaust part (5). Reference numeral (1) shows a GaAs substrate arranged in the chamber (4), and its heating amount is adjusted by a resistance heater (not shown). (6), (7), and (8) show the first, second, and third cells in which Zn, Se, and ZnS are placed, respectively, and the respective temperatures are variably set.

こうした分子線エピタキシャル成長装置を用いて、第1
図に示す無転位結晶薄膜を形成するためにはまず、GaAs
基板(1)として面方位〈100〉のものを用い、成長前
に温度620℃で15分の熱エッチによる表面処理を行な
う。そして、基板(1)の温度を320℃に設定して、第
1、第2のセル(6)(7)の温度を夫々約300℃及び
約220℃に加熱してZnSe膜(2)を100nm成長させる(成
膜速度は1μm/hである)。次いで、ZnSe膜(2)上にZ
nS膜(3)を2nm成長させる(成膜速度は0.3μm/h、第
3のセル(8)の温度は950℃)。さらに前述と同様にZ
nS膜(3)上にZnSe膜(2)とZnS膜(3)を繰り返し
成長することによりZnSe膜(2)とZnS膜(3)の積層
構造の薄膜が形成される。
Using such a molecular beam epitaxial growth system,
In order to form the dislocation-free crystal thin film shown in the figure, first, GaAs
A substrate (1) having a plane orientation of <100> is used, and surface treatment is performed by thermal etching at a temperature of 620 ° C. for 15 minutes before growth. Then, the temperature of the substrate (1) is set to 320 ° C., and the temperatures of the first and second cells (6) and (7) are heated to about 300 ° C. and about 220 ° C. to form the ZnSe film (2). Grow 100 nm (deposition rate is 1 μm / h). Then, Z on the ZnSe film (2)
The nS film (3) is grown to a thickness of 2 nm (film formation rate is 0.3 μm / h, temperature of the third cell (8) is 950 ° C.). Furthermore, as in the above, Z
By repeatedly growing the ZnSe film (2) and the ZnS film (3) on the nS film (3), a thin film having a laminated structure of the ZnSe film (2) and the ZnS film (3) is formed.

ZnSe膜(2)はGaAs基板(1)より格子定数が大きいた
めGaAs基板(1)より圧縮応力を受けるが、ZnS膜
(3)はZnSe膜(2)より格子定数が小さいのでZnS膜
(3)をZnSe膜(2)間に挿入することにより転位発生
の原因となる圧縮応力を緩和することができる。
Since the ZnSe film (2) has a larger lattice constant than the GaAs substrate (1), it receives compressive stress from the GaAs substrate (1), but since the ZnS film (3) has a smaller lattice constant than the ZnSe film (2), the ZnS film (3) ) Is inserted between the ZnSe films (2), the compressive stress that causes dislocation generation can be relaxed.

また、転位は透過電子顕微鏡で格子像を調べることによ
って確認できる。
The dislocations can be confirmed by examining the lattice image with a transmission electron microscope.

なお、本実施例ではZnS膜を用いたがZnSeSでもよい。Although the ZnS film is used in this embodiment, ZnSeS may be used.

(ト)考案の効果 本考案は以上の説明から明らかなように、GaAs基板上に
厚さ150nm以下のZnSe単結晶層と数原子層のZnSまたはZn
SeS混晶を交互に積層することにより転位の発生が抑制
されたGaAs基板上の無転位結晶薄膜を得ることができ
る。
(G) Effect of the Invention As is clear from the above description, the present invention is a ZnSe single crystal layer with a thickness of 150 nm or less and a few atomic layers of ZnS or Zn on a GaAs substrate.
By disposing SeS mixed crystals alternately, it is possible to obtain a dislocation-free crystal thin film on a GaAs substrate in which dislocation generation is suppressed.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案実施例の半導体構造の断面図、第2図は
分子線エピタキシャル装置の断面図である。 (1)……GaAs基板、(2)……ZnSe膜、(3)……Zn
S膜、(4)……チャンバ、(5)……排気部、(6)
(7)(8)……セル。
FIG. 1 is a sectional view of a semiconductor structure of an embodiment of the present invention, and FIG. 2 is a sectional view of a molecular beam epitaxial device. (1) …… GaAs substrate, (2) …… ZnSe film, (3) …… Zn
S film, (4) ... Chamber, (5) ... Exhaust part, (6)
(7) (8) …… Cell.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】GaAs基板上に厚さ150nm以下のZnSe単結晶
層と数原子層のZnSまたはZnSeS混晶を交互に積層してな
ることを特徴とする半導体構造。
1. A semiconductor structure characterized in that a ZnSe single crystal layer having a thickness of 150 nm or less and several atomic layers of ZnS or ZnSeS mixed crystal are alternately laminated on a GaAs substrate.
JP1986132974U 1986-08-29 1986-08-29 Semiconductor structure Expired - Lifetime JPH0739250Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986132974U JPH0739250Y2 (en) 1986-08-29 1986-08-29 Semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986132974U JPH0739250Y2 (en) 1986-08-29 1986-08-29 Semiconductor structure

Publications (2)

Publication Number Publication Date
JPS6339961U JPS6339961U (en) 1988-03-15
JPH0739250Y2 true JPH0739250Y2 (en) 1995-09-06

Family

ID=31032858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986132974U Expired - Lifetime JPH0739250Y2 (en) 1986-08-29 1986-08-29 Semiconductor structure

Country Status (1)

Country Link
JP (1) JPH0739250Y2 (en)

Also Published As

Publication number Publication date
JPS6339961U (en) 1988-03-15

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