JPH0739234Y2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0739234Y2
JPH0739234Y2 JP1986032787U JP3278786U JPH0739234Y2 JP H0739234 Y2 JPH0739234 Y2 JP H0739234Y2 JP 1986032787 U JP1986032787 U JP 1986032787U JP 3278786 U JP3278786 U JP 3278786U JP H0739234 Y2 JPH0739234 Y2 JP H0739234Y2
Authority
JP
Japan
Prior art keywords
electrically insulating
hole
recess
insulating substrate
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1986032787U
Other languages
Japanese (ja)
Other versions
JPS62145337U (en
Inventor
英二 萩本
次郎 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1986032787U priority Critical patent/JPH0739234Y2/en
Publication of JPS62145337U publication Critical patent/JPS62145337U/ja
Application granted granted Critical
Publication of JPH0739234Y2 publication Critical patent/JPH0739234Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Die Bonding (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、電気絶縁性基板に半導体ペレットを取りつけ
る構造の半導体装置におけるマウント部の構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a structure of a mount portion in a semiconductor device having a structure in which a semiconductor pellet is mounted on an electrically insulating substrate.

〔従来の技術〕[Conventional technology]

電気絶縁性基板に半導体ペレットを取りつける構造の半
導体装置における通常の組み立て方法は次の通りであ
る。A general method of assembling a semiconductor device having a structure in which a semiconductor pellet is attached to an electrically insulating substrate is as follows.

半導体ペレットを電気絶縁性基板のマウント部に搭載
し、Au,Alなどの金属細線を用いて半導体ペレットのボ
ンディングバッド部と相対する電気絶縁性基板のパッド
部とを電気的に接続する。その後、樹脂や封止用キャッ
プを用いて封止する。これらの一連の組み立て工程にお
いて、マウント部に半導体ペレットを搭載する際、半導
体ペレットと電気絶縁性基板との接着は、Agペーストの
ごとき熱硬化性樹脂材料は勿論マウント部としての凹部
の表面がメタライズされていればAu-Sn,Au-Si等の低融
点ロー材を使用することができる。The semiconductor pellet is mounted on the mount portion of the electrically insulating substrate, and the bonding pad portion of the semiconductor pellet and the pad portion of the electrically insulating substrate opposite thereto are electrically connected by using a metal thin wire such as Au or Al. After that, sealing is performed using a resin or a sealing cap. When mounting the semiconductor pellets on the mount portion in these series of assembly steps, the semiconductor pellets and the electrically insulating substrate are adhered to each other not only by thermosetting resin material such as Ag paste but also on the surface of the recess portion as the mount portion. If so, a low melting point brazing material such as Au-Sn or Au-Si can be used.

〔考案が解決しようとする問題点〕 いずれにしても接着には加熱することが必要であるが電
気絶縁性基板としてガラスエポキシ、ガラスフェノー
ル、ガラスポリイミド等の有機材料系の基板を用いる場
合、マウント部にメタライズを施してあると有機材料と
メタライズ層との間で剥離することがある。これらは有
機材料に対するメタライズ層の密度強度が不足している
場合ばかりでなく、これらの材料間に製造工程で含まれ
てしまった異物がガス化したり、空間部分の気体が膨張
したために発生することがあるからである。このことは
大きな半導体ペレットを搭載するマウント部になればな
るほど発生しやすい傾向がある。剥離が生じると半導体
ペレットが浮き上がり、後工程であるボンディング作業
におけるボンディングに不具合を生じる。また、半導体
ペレットの放熱に留意しなければならない場合には、半
導体装置としての機能に支障を生じることになる。[Problems to be solved by the invention] In any case, it is necessary to heat for bonding, but when using an organic material type substrate such as glass epoxy, glass phenol, glass polyimide as an electrically insulating substrate, mount If the portion is metallized, the organic material and the metallized layer may be separated from each other. These occur not only when the density strength of the metallized layer with respect to the organic material is insufficient, but also because foreign matter contained in the manufacturing process between these materials is gasified or the gas in the space expands. Because there is. This tends to occur more easily in the mount part where a large semiconductor pellet is mounted. When the peeling occurs, the semiconductor pellet floats up, which causes a problem in bonding in a bonding process which is a post process. Further, if attention must be paid to the heat radiation of the semiconductor pellet, the function as a semiconductor device will be hindered.

さらに、マウント部のメタライズ上にNiやAuの電気めっ
きを施す場合には、導電路が必要だがそのためのパター
ンが用意できない場合には作業用ラックを工夫して導電
路を解保しなければならない。多くの場合、作業の安定
性にかけているのが現状である。この点は電気絶縁性基
板としてアルミナ等のセラミクス基板を用いた場合に顕
著である。本考案は、上述の欠点を除去した構造を提供
するものである。Furthermore, when electroplating Ni or Au on the metallization of the mount, a conductive path is required, but if a pattern for that is not available, a work rack must be devised to release the conductive path. . In many cases, the current situation is that the work is not stable. This point is remarkable when a ceramic substrate such as alumina is used as the electrically insulating substrate. The present invention provides a structure that eliminates the above-mentioned drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本考案の半導体装置は、有機材料系の電気絶縁性基板で
あって、ペレットをマウントするための凹部を有し、前
記凹部には表面・裏面間を貫通する貫通孔が形成された
電気絶縁性基板と、前記凹部の側面および底面と前記貫
通孔の表面と前記基板の裏面とを連続的に覆うメタライ
ズ層であって、前記貫通孔内に新たな空隙を形成するメ
タライズ層と、前記貫通孔上に位置するように前記ペレ
ットマウント部の前記メタライズ層に接着剤で固定され
た半導体ペレットを有することを特徴とする。The semiconductor device of the present invention is an electrically insulating substrate of an organic material type, which has a recess for mounting pellets, and the recess has a through hole penetrating between the front surface and the back surface. A metallization layer that continuously covers the substrate, the side and bottom surfaces of the recess, the front surface of the through hole, and the back surface of the substrate, the metallization layer forming a new void in the through hole; It is characterized in that it has a semiconductor pellet fixed to the metallized layer of the pellet mount portion with an adhesive so as to be located above.

半導体ペレットを接着するマウント部に設けた貫通孔の
周囲又は内部の金属部によってメタライズ層が基板に固
定されるので実質的にメタライズ層の密着強度を上げる
ことができる。Since the metallized layer is fixed to the substrate by the metal part around or inside the through hole provided in the mount part to which the semiconductor pellet is bonded, the adhesion strength of the metallized layer can be substantially increased.

また、発生する熱を効率よく逃がしたり、電気的導通が
とれるので、半導体ペレットの特性を生かすことができ
る。Further, since the generated heat can be efficiently dissipated and electrical conduction can be established, the characteristics of the semiconductor pellet can be utilized.

〔実施例〕〔Example〕

以下に本考案の実施例について詳細に説明する。第１図
は本考案の実施例を示す縦断面図であって、半導体装置
の一部分を表示している。電気絶縁性基板１はガラスエ
ポキシ、ガラスフェノール、ガラスポリイミド等の有機
材料系のものである。半導体ペレット２は電気絶縁性基
板１にマウント部として凹部を設けて搭載されている。
凹部の表面はメタライズされており半導体ペレット２と
電気絶縁性基板１との接着は、Agペーストのごとき熱硬
化性樹脂材料は勿論Au-Sn,Au-Si等の低融点ロー材を使
用することもできる。熱硬化性樹脂材料を接着剤として
用いる場合には十分加熱しておかないと後工程であるボ
ンディング作業においてガスが発生しボンディング時の
雰囲気を損じ不良を生じる。半導体ペレットの放熱に留
意しなければならない場合には、熱伝導率の良い金属系
ロー材が有利である。Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a vertical sectional view showing an embodiment of the present invention, showing a part of a semiconductor device. The electrically insulating substrate 1 is made of an organic material such as glass epoxy, glass phenol and glass polyimide. The semiconductor pellet 2 is mounted on the electrically insulating substrate 1 with a recess provided as a mount portion.
The surface of the recess is metallized and the semiconductor pellet 2 and the electrically insulating substrate 1 are bonded to each other by using a low melting point brazing material such as Au-Sn, Au-Si as well as a thermosetting resin material such as Ag paste. You can also When a thermosetting resin material is used as an adhesive, if it is not sufficiently heated, gas will be generated in the bonding process which is a post-process, and the atmosphere during bonding will be damaged and defects will occur. When attention must be paid to the heat dissipation of the semiconductor pellet, a metal-based brazing material having a good thermal conductivity is advantageous.

マウント部に一ケ所又は数ケ所貫通孔を設ける。貫通孔
にはいわゆるスルーホールめっきしておく。めっきの方
法は通常のめっき方法が利用できる。例えば、樹脂基板
であればCuの無電解めっき、アルミナ等のセラミクスで
あればＷのメタライズ上にNiめっきを施す。この貫通孔
周囲の金属部分が電気絶縁性基板に固着して加熱による
フクレを抑制することになる。電気絶縁性基板への固定
は前記の貫通孔だけでも可能だがマウント部である凹部
の裏面側にも金属部を設けておいたほうが効果が確実と
なる。貫通孔の空洞部は、後工程で熱硬化性樹脂や半田
など金属で詰めておくことで耐湿性及び強度が向上す
る。Provide one or several through holes on the mount. The through holes are so-called through-hole plated. As a plating method, an ordinary plating method can be used. For example, electroless plating of Cu is applied to a resin substrate, and Ni plating is applied to metallization of W for ceramics such as alumina. The metal portion around the through hole is fixed to the electrically insulating substrate to suppress blistering due to heating. The fixing to the electrically insulating substrate can be performed only by the through hole, but the effect is more reliable if the metal portion is provided also on the back surface side of the recess which is the mount portion. The cavity portion of the through hole is filled with a metal such as a thermosetting resin or solder in a later process to improve the moisture resistance and strength.

電気絶縁性基板が一層形式のものでボンディングパッド
パターンが密にパターンニングされている場合にはスル
ーホールからの結線８によってマウント部の電気的導通
をとることができる。When the electrically insulating substrate is of a single layer type and the bonding pad pattern is densely patterned, the electrical connection of the mount portion can be established by the connection 8 from the through hole.

第１図ではスルーホールは一ケ所であるがマウント部の
大きさにあわせて数ケ所設けてもよい。Although there is only one through hole in FIG. 1, it may be provided at several places depending on the size of the mount portion.

〔考案の効果〕[Effect of device]

本考案は、構造が簡単でマウント作業の歩留まりを向上
させる。パッケージ形態としてフェイスダウンタイプに
すれば放熱の効果をより一層期待することができる。The present invention has a simple structure and improves the yield of mounting work. If a face-down type is used as the package form, the heat dissipation effect can be further expected.

【図面の簡単な説明】[Brief description of drawings]

第１図は、本考案の実施例を示す縦断面図である。 ここに、１……電気絶縁性基板、２……半導体ペレッ
ト、３……電気絶縁性フレーム、４……金属細線、５…
…メタライズ層、６……接着材、７……貫通孔、８……
結線。FIG. 1 is a vertical sectional view showing an embodiment of the present invention. Here, 1 ... electrically insulating substrate, 2 ... semiconductor pellet, 3 ... electrically insulating frame, 4 ... metal fine wire, 5 ...
… Metallization layer, 6 …… Adhesive, 7 …… Through hole, 8 ……
Connection.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項１】有機材料系の電気絶縁性基板であって、ペ
レットをマウントするための凹部を有し、前記凹部には
表面・裏面間を貫通する貫通孔が形成された電気絶縁性
基板と、前記凹部の側面および底面と前記貫通孔の表面
と前記基板の裏面とを連続的に覆うメタライズ層であっ
て、前記貫通孔内に新たな空隙を形成するメタライズ層
と、前記貫通孔上に位置するように前記ペレットマウン
ト部の前記メタライズ層に接着剤で固定された半導体ペ
レットを有する半導体装置。1. An electrically insulating substrate made of an organic material, comprising: a recess for mounting a pellet, wherein the recess has a through hole penetrating between a front surface and a back surface thereof. A metallization layer that continuously covers the side and bottom surfaces of the recess, the front surface of the through hole, and the back surface of the substrate, and a metallization layer that forms a new void in the through hole; A semiconductor device having a semiconductor pellet fixed to the metallized layer of the pellet mount portion with an adhesive so as to be positioned.
JP1986032787U 1986-03-07 1986-03-07 Semiconductor device Expired - Lifetime JPH0739234Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986032787U JPH0739234Y2 (en) 1986-03-07 1986-03-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986032787U JPH0739234Y2 (en) 1986-03-07 1986-03-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS62145337U JPS62145337U (en) 1987-09-12
JPH0739234Y2 true JPH0739234Y2 (en) 1995-09-06

Family

ID=30839797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986032787U Expired - Lifetime JPH0739234Y2 (en) 1986-03-07 1986-03-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0739234Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0746709B2 (en) * 1986-08-11 1995-05-17 イビデン株式会社 Electronic component mounting board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5836500A (en) * 1981-08-28 1983-03-03 マックス株式会社 Disk mounting device for encoding drawing head
JPS6218084A (en) * 1985-07-16 1987-01-27 新藤電子工業株式会社 Manufacture of printed wiring board for mounting semiconductor element
JPS6239032A (en) * 1985-08-14 1987-02-20 Matsushita Electric Works Ltd Chip carrier for electronic element

Also Published As

Publication number Publication date
JPS62145337U (en) 1987-09-12

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