JPH0738696A - Image forming device and system - Google Patents

Abstract

PURPOSE:To obtain an image forming device by correcting a picture signal based on a color test picture with equipment identification information added thereto so as to arrange the density when a picture of the same source from plural devices is outputted. CONSTITUTION:When plural image forming devices are operated nearly simultaneously by a same picture signal for printing, a control section 1165 provided to a picture processing section of each image forming device prints out a color test picture added with equipment identification information representing the image forming device outputted from a pattern generator 1161. Then the correction value of gradation correction devices 1164-1167 is set based on the printed color test picture. Thus, the equipment information is added to the color test picture and the user allows the image forming device to read the color test picture without notifying from which image forming device outputs the color test picture and corrects the image forming device outputting the color test signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus and an image forming system in which, for example, a plurality of image forming apparatuses are connected to output the same full-color image from each apparatus substantially at the same time.

[0002]

2. Description of the Related Art A system for connecting a plurality of image forming apparatuses and forming images from the same supply source by these image forming apparatuses is disclosed in Japanese Patent Laid-Open Publication No. 59-189769. It has been known.

[0003]

However, the above-mentioned conventional example has the following problems. That is, since all the images output by the respective image forming apparatuses are not controlled to have the same density, the images output depending on the respective states of the image forming apparatuses, regardless of the same image source. There was a drawback that each concentration was different.

Further, in the case of a system in which a plurality of color image forming apparatuses are connected, there arises a problem that not only the densities of the output images are different but also the tints thereof are different.

[0005]

SUMMARY OF THE INVENTION The present invention is intended to solve the above problems, and has the following structure as one means for solving the above problems. That is, it is characterized in that information for specifying the image forming apparatus is formed with the image signal representing the given color test image.

Further, common reading means for reading an image of an original and outputting an image signal, color test means for outputting an image signal representing a color test image, and an image output from the reading means or the color test means A correction means for correcting the signal; and a plurality of forming means for forming an image corresponding to the image signal representing the color test image on a recording medium, wherein the correcting means uses the test image formed by the forming means for the test image. It is characterized in that the correction value of the image signal is set based on the image signal read by the common reading means.

[0007]

With the above configuration, it is possible to provide an image forming system that sets a correction value of an image signal based on an image signal obtained by reading a test image. For example, when images of the same source are output by a plurality of image forming apparatuses, The density and color can be made uniform.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image forming apparatus and system according to an embodiment of the present invention will be described in detail below with reference to the drawings. In the following description, a system of a full-color copying machine will be described as a preferred embodiment, but the present invention is not limited to this, and within the scope not departing from the gist of the present invention,
Of course, it can be implemented in various modes.

[Description of Device Outline] FIG. 2 is a diagram showing an example of a system configuration of the present embodiment. In the figure, 1 to 4 are full-color copying machines (hereinafter simply referred to as "copying machines"), and 5 to 7 are interface cables for connecting the copying machines to each other.

Each of these copying machines is composed of an image scanner and a color image output section, and operates as a single copying machine (hereinafter referred to as "stand-alone"). In addition, an image signal of an original read by a copying machine is used. By transmitting the image to another copying machine, the images of the document can be output substantially simultaneously by a plurality of copying machines (hereinafter, referred to as "double-run").

FIG. 4 is a schematic view of the copying machine shown in FIG. Reference numeral 1201 denotes a platen glass, which is an original 1 to be read.
202 is placed. The original 1202 is illuminated by the illumination 1203, and the reflected light from the original 1202 is reflected by the mirror 120.
4 through 1206, the optical system 1207 causes the CCD 12
The image is formed on 08. Further, mechanically by the motor 1209, the mirror unit 1210 including the mirror 1204 and the illumination 1203 is driven at the speed V and the mirrors 1205, 120
The second mirror units 1211 including 6 are driven at a speed of V / 2, respectively, and the entire surface of the original 1202 is scanned.

An image processing unit 1212 processes the read image as an electric signal and outputs it as a print signal. Reference numerals 1213 to 1216 denote semiconductor lasers, which are driven by a print signal output from the image processing unit 1212.
The laser beams emitted by the respective semiconductor lasers form latent images on the photosensitive drums 1225 to 1228 by the polygon mirrors 1217 to 1220. 122
Numerals 1 to 1224 denote developing units for developing latent images with K, Y, C, and M toners, respectively, and the developed toners of the respective colors are transferred to the recording paper, and full-color print output is performed.

The recording paper fed from any of the recording paper cassettes 1229 to 1231 and the manual feed tray 1232 passes through the registration roller 1233 and the transfer belt 123.
4 is adsorbed on and conveyed. In synchronization with the feeding timing, the photosensitive drums 1228 to 1225 are preliminarily developed with toners of respective colors, and the toners are transferred onto the recording paper as the recording paper is conveyed.

The recording paper on which the toner of each color is transferred is separated and conveyed from the transfer belt 1234, the toner is fixed by the fixing device 1235, and the paper is discharged to the paper discharge tray 1236. [Flow of Image Signal] FIGS. 1A and 1B show an image processing unit 1212.
3 is a block diagram showing a configuration example of FIG. 1101-1103
Are R, G, and B CCD sensors, respectively, and the sensor 110
The outputs of 1 to 1103 are analog amplifiers 1104 to 11
The signal is amplified by 06 and converted into digital signals by the A / D converters 1107 to 1109. 1110
Reference numeral 1111 is a delay element, which includes sensors 1101 to 1103.
The spatial deviation between the two is corrected.

An interface circuit 1163 is used for exchanging image data with other copying machines and outputting image data of an original read by a copying machine to a plurality of copying machines. That is, the interface circuit 1
The reference numeral 163 sends the image signal read by the CCD 1208 to the image processing circuit in the subsequent stage, and also sends it to another copying machine connected by the interface cables 5 to 7, or vice versa. Control is performed to receive and send to the image processing circuit in the subsequent stage.

Reference numerals 1151 to 1156 and 1162 denote tristate gates which allow respective input signals to pass when signals OE1 to OE7 sent from a CPU (not shown) are "0". Table 1 shows an example of the relationship between the scaling processing contents and the signals OE1 to OE6.

[0017]

[Table 1] Reference numerals 1157 to 1160 denote scaling circuits, which scale the image signal sent from itself or another copying machine connected thereto in the main scanning direction.

Reference numeral 1112 is a color space converter for converting an RGB signal into a lightness signal L ^* and chromaticity signals a ^* and b ^* . Here, the L ^* a ^* b ^* signal is a signal representing a uniform color space defined by CIE. The L ^* a ^* b ^* signal is represented by the following equation. However, αij, X0, Y0, Z0 are constants. X, Y, Z in the above equations are signals generated by calculating RGB signals and are represented by the following equations.

[0019] Where βij is a constant 1113 is the encoder a, which encodes the lightness signal L ^* in units of 4 × 4 pixel blocks, for example, and the code signal L-code and an attribute indicating whether or not the pixel block is an edge portion. Signal E-co
Output de and. Reference numeral 1114 is an encoder b for chromaticity signals a ^* ,
For example, ^* b ^* is encoded in 4 × 4 pixel block units and a code signal ab-code is output. Although details will be described later, the characteristic here is that the lightness code signal L-code and the chromaticity code signal
The ab-code has a different code length depending on the attribute signal E-code, but the sum of the code lengths is the attribute signal E-co
It is always constant regardless of de, and the total sum of L-code, ab-code, and E-code is, for example, 64 bits.

On the other hand, 1115 is a feature extraction circuit that detects the presence or absence of two types of features for the pixel. The first feature is a black pixel, and the black pixel detection circuit 1115-1 generates a determination signal K1 ′ for determining whether the pixel is a black pixel. Further, the signal K1 ′ is input to the 4 × 4 area processing circuit 1115-3 and becomes the determination signal K1 for determining whether or not the inside of the 4 × 4 pixel block is the black pixel area.

The second feature is a character pixel, and the character area detection circuit 1115-2 generates a determination signal K2 'for determining whether the pixel is a character pixel. Further, the signal K2 ′ is input to the 4 × 4 area processing circuit 1115-4 and becomes a determination signal K2 for determining whether or not the inside of the 4 × 4 pixel block is a character area. 11
An image memory 16 stores a lightness code signal L-code, a chromaticity code signal ab-code, an attribute signal E-code, and determination signals K1 and K2 which are feature extraction results.

Reference numerals 1141 to 1144 denote density signal generation units for M, C, Y, and K, respectively, and 1141 to 1144 have substantially the same configuration. 1117 is a lightness information decoder a, which is a signal L ^{* based on} the L-code and E-code read from the image memory 1116 ^.
1118, which is a chromaticity information decoder b for decoding the signals a ^* and b ^* from the ab-code and E-code read from the image memory 1116. A color space converter 1119 converts the decoded signal L ^* a ^* b ^* into color components of M, C, Y, and K that are toner development colors. 1120 is a density converter, for example
ROM or RAM lookup table (hereinafter "LUT")
It is composed of). A spatial filter 1121 corrects the spatial frequency of the output image. An image correction circuit 1122 corrects the decoded image data.

A pattern generator 1161 outputs a constant pattern when calibrating the copying machine. Reference numerals 1164 to 1167 are gradation correctors, each of which is composed of, for example, a RAM LUT, and corrects the output characteristics of the image output device. A control unit 1165 includes a work RAM, a ROM that stores a program, and a microcomputer that executes the program. The control unit 1165 controls the above-described components according to the program.

In the present embodiment, the flow of the image signal is slightly different depending on the enlargement copying or the reduction copying, so the flow of the image signal in each case will be described below. [In the case of enlargement processing] The original shown in FIG.
When the enlargement process is performed as shown in (b), the scaling process is performed before the encoding (compression) process. Therefore, as shown in Table 1, each of the three signals OE1, OE3, and OE6 has a value of "0".
Set, 1151 out of tri-state gates,
1153 and 1156 are through, and the others are invalid.

As a result, the RGB image signal output from the interface circuit 1158 first undergoes the tristate gate 1151 and is then enlarged by the scaling circuits 1157 to 1159. The operation of the scaling processing circuit is known,
Detailed description is omitted. Next, the enlarged RGB image signal is sent to the color space converter 1112 and the feature extraction circuit 1115 via the tristate gate 1153,
It is encoded by the encoders 1113 and 1114, and the feature is extracted by the feature extraction circuit 1115. As a result, the image code signals L-code, ab-code and the characteristic signals K1, K2 are sent to the image memory 1116 and held therein.

The code read from the image memory 116 is
Density signal generation units 1141 to 114 for M, C, Y, and K, respectively
4 is decoded (expanded) as a density image signal, and tristate gate 1156 and gradation correctors 1164 to 116
After that, they are sent to the laser drivers for M, C, Y, and K respectively. [In the case of reduction processing] The original shown in FIG.
When the reduction processing is performed as shown in (c), the scaling processing is performed before the encoding (compression) processing. Therefore, as shown in Table 1, each of the three signals OE2, OE4, and OE5 has a value of "0".
Set the Tri-state gate to 1152,
1154 and 1155 are set to through, and the others are invalid.

As a result, the RGB image signal from the interface circuit 1158 is first transmitted to the tristate gate 115.
2 through the color space converter 1112 and the feature extraction circuit 1
It is sent to 115, encoded by the encoders 1113 and 1114, and its characteristic is extracted by the characteristic extraction circuit 1115. As a result, the image code signals L-code, ab-code and the characteristic signals K1, K2 are sent to the image memory 1116 and held therein.

The code read from the image memory 116 is
Density signal generation units 1141 to 114 for M, C, Y, and K, respectively
4 is decoded (expanded) as a density image signal, passes through the tristate gate 1155, and the scaling circuits 1157 to 116.
It is input to 0 and reduced. Next, it was reduced
The CMYK signals are sent to the laser drivers for M, C, Y, and K through the tristate gate 1154 and the gradation correctors 1164 to 1167, respectively.

[Brightness Information Encoder] FIG. 14 shows the brightness information L ^*.
FIG. 3 is a block diagram showing details of an encoder a1113 that encodes a. Further, FIG. 33 shows an example of the timing chart, and FIGS. 15 and 16 are views showing the concept of the brightness information encoding. Note that the encoding (compression) of the image data is performed, for example, by using FIG.
As shown in FIG. 5, a total of 1 main scanning 4 pixels × sub scanning 4 lines
A block of 6 pixels is used as a unit. Here, XPHS is a 2-bit signal indicating the main scanning position and repeats 0, 1, 2, and 3, and YPHS is a 2-bit signal indicating the sub-scanning position, which is 0, 1,
Repeat steps 2 and 3 and select the signals XPHS and YPHS as shown.
4 × 4 pixel blocks are cut out in synchronism with.

First, the concept of brightness information encoding is shown in FIG.
This will be described using 6. In the brightness information Xij (i, j = 1 to 4) cut out into the 4 × 4 pixel block shown in FIG.
When the 4 × 4 Hadamard transform shown in the equation is applied, FIG.
Yij (i, j = 1 to 4) shown in (b) is obtained. The Hadamard transform is a type of orthogonal transform that expands 4 × 4 data by a two-dimensional Walsh function, and a Fourier domain transforms a signal in the time domain or the spatial domain into the frequency domain or the spatial frequency domain. Is equivalent to. That is, the matrix Yij (i, j = 1 to 4) after Hadamard transform becomes a signal corresponding to each component of the spatial frequency of the matrix Xij (i, j = 1 to 4) of the input signal.

[0031] Where H is a 4 × 4 Hadamard matrix H ^T is the transposed matrix of H Here, as in the case of the two-dimensional Fourier transform, the Hadamard transform result Yij (i, j = 1 to 4) shows that the larger the value of i (that is, the row position), the higher the spatial frequency component in the sub-scanning direction. Are arranged, and the larger the value of j (that is, the column position), the higher the spatial frequency component is arranged in the main scanning direction. In particular, when i = j = 1, Yij = (1/4) ΣXij, and the signal corresponding to the DC component of the input data Xij (i, j = 1 to 4), that is, the average value (strictly speaking, the average value is A signal having a value multiplied by 4) is output.

It is generally known that an image read by an image scanner has few high spatial frequency components due to the resolution of a reading sensor such as CCD and the transmission characteristic of an optical system. Further, the visibility of the human eye is also high, and the sensitivity of the spatial frequency component is low, and the signal Yij (i, j = 1 to 4) after Hadamard transform is scalar-quantized, and
Zij (i, j = 1 to 4) shown in (c) is obtained.

FIG. 16A shows the number of bits of each element of the lightness information Xij (i, j = 1 to 4), and FIG. 16B shows the result of Amadal conversion.
The number of bits of each element of Yij (i, j = 1 to 4) and the number of bits of each element of the scalar quantization result Zij (i, j = 1 to 4) are shown in FIG. As shown, Y11, that is, the DC component is quantized with the largest number of bits (8 bits) to Z11, and the higher spatial frequency component is quantized with the smaller number of bits. Further, as shown in FIG. 15D, 16 elements of zij (i, j = 1 to 4) are grouped into a DC component and four AC components.
That is, as shown in Table 2, the DC component Z11 is assigned to the signal AVE and the main scanning AC components Z12 and Z1 are grouped into the signal L1.
3, Z14 is assigned, the sub-scanning AC components Z21, Z31, Z41 grouped to the signal L2 are assigned, the main scanning and sub-scanning mid-range AC components Z22, Z23, Z32, Z33 are assigned to the signal M, The high-frequency components Z24, Z34, Z42, Z43, and Z44 of the main scanning and the sub scanning which are grouped are assigned to the signal H.

[0034]

[Table 2] Further, the code length is changed depending on whether or not the pixel block is an edge portion in the image, and coding is performed for each group. For example, in the case of the edge portion, the code length is exemplarily shown in FIG. 16D, and in the case of the non-edge portion, the code length is exemplarily shown in FIG. 16E. That is, since the information of the AC component is important in the edge portion, a large code length is assigned to the AC component signals L1, L2, M, and H.

In FIG. 14, reference numerals 701, 702 and 703 denote line memories, which delay the image data by one line to cut out a pixel block as shown in FIG. A Hadamard transform circuit 704 performs the transform represented by the equation (3). That is, as shown in FIG. 33, the signal CL
In synchronization with K and XPHS, the terminal x of the Hadamard conversion circuit 704
1 has X11, X12, X13, X14, and terminal x2 has X21, X22, X23, X24
However, terminal x3 has X31, X32, X33, X34, and terminal x4 has X41, X4
2, X43, X44 are input respectively. The Hadamard-converted signal is delayed by 8 pulses of the signal CLK, and it is output from terminals y1 to Y.
11, Y12, Y13, Y14, terminals y2 to Y21, Y22, Y23, Y24, terminals y3 to Y31, Y32, Y33, Y34, terminals y4 to Y41, Y42, Y43, Y
44 is output respectively.

Reference numerals 705 to 708 each denote an LUT, which is composed of, for example, a ROM or the like, and performs the above-described scalar quantization. That is, in order to quantize the Hadamard-converted output into the number of bits as shown in FIG. 16C, the LUTs 705 to 708 are responsive to the Hadamard conversion result and the signal XPHS input to the address terminal A. Data is written in advance so as to output the scalar quantization result.

A grouping circuit 709 performs grouping for vector quantization. FIG. 17 is a block diagram showing a detailed configuration example of the grouping circuit 709. In the figure, reference numerals 101 to 116 denote flip-flops (hereinafter referred to as “F / F”), which input the signal CL
By delaying in synchronization with K, each data of 4 × 4 block shown in FIG. 15C is held. Then, the held data is divided into the groups shown in Table 2, and the signals AVE, L
Reference numerals 117 to 121 of 1, L2, M, and H are 2-input 1-output selectors. When "0" is input to the selection terminal S, the signal input to the terminal A is output, and "1" is output. When input, it outputs the signal input to terminal B. The signal XD0 input to the selection terminal S is the signal CLK and the signal CLK as shown in FIG.
In synchronization with XPHS, the signal becomes "0" only when the signal XPHS is "0", and otherwise becomes "1". Therefore, for each 4 × 4 block, the scalar quantization result for each group shown in Table 2 is output from the selectors 117 to 121.

Reference numerals 122 to 126 denote F / Fs, which delay the input signal by one pulse of the signal CLK, as shown in FIG. Further, 127 to 131 are also F / F, hold the input at the rising edge of the signal CLK4, and output the signals AVE, L1, L2, M and H at the timings shown in FIG. Again, in FIG. 14, reference numerals 710 to 713 are LUTs, which are constituted by, for example, a ROM or the like, and quantize the signals L1, L2, M, and H output from the grouping circuit 709 by known vector quantization. . Although the details will be described later, the signal ED1 input to the address terminal A of each LUT here is a signal indicating whether or not the pixel block is an edge portion.

The signal ED1 is input to the upper address of each LUT, and the signals L1, L2, M, and H are input to the lower addresses thereof. When the pixel block is an edge portion, the group L1 is set to 9 bits, Group L2 to 9 bits, group
Quantize M to 9 bits and group H to 8 bits to make a total of 43 bits including 8 bits of AVE. If the pixel block is a non-edge part,
L1 to 8 bits, Group L2 to 8 bits, Group M
Is quantized to 8 bits and group H is quantized to 7 bits, and the total is 39 bits including 8 bits of AVE.

Further, the quantization result is input to the F / F 714, held at the rising edge of the signal CLK4, and output as an L-code at the timing shown in FIG. On the other hand, 715
The LGAIN calculator calculates the lightness information Xij (i, j = 1 to 4 × 4 blocks at the same timing as the Hadamard conversion circuit 704.
4) its terminals A, B, C, is input to the D, lightness signal L ^* of amplitude (maximum value - LGAIN representing the minimum value), the lightness signal L ^* is the maximum value position (coordinates in the pixel block) And LMN representing the position (coordinates within the pixel block) at which the lightness signal L ^* has the minimum value are calculated.

Reference numeral 716 is a comparator, which compares the signal LGAIN with a threshold value Th preset in the fixed value register 717,
The comparison result ED is output. That is, when the pixel block is the edge portion, LGAIN> Th and the signal ED is “1”. When the pixel block is the non-edge portion, LGAIN <Th and the signal ED is “0”. Reference numerals 718 to 720 denote F / Fs, which delay the input signal ED in synchronization with the rising edge of the signal CLK4 to obtain the signal ED1 synchronized with the above-described vector quantization timing. 721 is also F / F, delays the input signal ED1 in synchronization with the rising edge of the signal CLK4,
Signal E-code signal is output.

FIG. 18 is a block diagram showing the detailed structure of the LGAIN calculator 715. In the figure, 201 to 20
Reference numeral 4 is an F / F, which holds the input data at the rising edge of the signal CLK. Reference numeral 205 denotes a maximum / minimum value detection circuit in the sub-scanning direction, the details of which are shown in FIG. In the figure, 30
1, 302 is a 2-input 1-output selector, 303 is a comparator, 304 is an inverter. If the input A> the input B, the output of the comparator 303 becomes "1", and the selector 3
01 outputs the signal input to the terminal A (that is, input A), and the selector 302 outputs the signal input to the terminal B (that is, input B). On the other hand, if input A ≦ input B, the output of the comparator 303 becomes “0”, and the selector 301
Outputs the signal input to the terminal B (that is, the input B), and the selector 302 outputs the signal input to the terminal A (that is, the input A). That is, the selector 301 has the maximum value ma
x (A, B) is output, and the selector 302 outputs the minimum value min (A, B).

Similarly, 305 and 306 are 2-input 1-output selectors, 307 is a comparator, and 308 is an inverter. The selector 305 outputs the maximum value max (C, D) and the selector 306 outputs the minimum value min ( C, D) outputs. Furthermore, 30
Reference numerals 9 and 311 are 2-input 1-output selectors, 310 is a comparator, 312 to 314 are inverters, and if max (A, B)
If> max (C, D), the output of the comparator 310 becomes "1", and the selector 309 outputs max (A, B). On the other hand, max
If (A, B) ≦ max (C, D), the output of the comparator 310 is “0”.
Then, the selector 309 outputs max (C, D). That is, the selector 309 outputs the maximum value max (A, B, C, D).
Further, the signals imx (0) and imx (1) indicate which of the inputs A to D has the maximum value by the following code.

When A is the maximum value: imx (1) = '0' and imx (0) = '0' When B is the maximum value: imx (1) = '0' and imx (0) = '1 'When C is the maximum value: imx (1) =' 1 'and imx (0) =' 0 'When D is the maximum value: imx (1) =' 1 'and imx (0) =' 1 ' And 315 and 317 are selectors with 2 inputs and 1 output, 3
16 is a comparator, and the selector 315 is a minimum value min (A, B,
Output C, D). The signals imn (0) and imn (1) indicate which of the inputs A to D has the minimum value by the following code.

When A is the minimum value: imx (1) = '0' and imx (0) = '0' When B is the minimum value: imx (1) = '0' and imx (0) = '1 'When C is the minimum value: imx (1) =' 1 'and imx (0) =' 0 'When D is the minimum value: imx (1) =' 1 'and imx (0) =' 1 ' In No. 18, 206 to 213 are F / Fs,
The max / min, imx, and imn output signals of the maximum / minimum value detection circuit 205 in the sub-scanning direction are each delayed by one pulse of the signal CLK.

Reference numeral 214 denotes a main-scanning-direction maximum value detection circuit, which outputs F / F209 to terminal A, F / F208 to terminal B, F / F207 to terminal C, and F / F206 to terminal D.
, That is, a signal obtained by delaying the signal max by one pulse of the signal CLK is input. In addition, F / F20 to terminal iA
9 output, F / F208 output to terminal iB, F / F output to terminal iC
The output of F207 and the output of F / F206 to the terminal iD, that is, a signal obtained by delaying the signal imx by one pulse of the signal CLK, are input.

FIG. 20 shows a maximum value detection circuit 214 in the main scanning direction.
3 is a block diagram showing a detailed configuration of FIG. In the figure,
401 is a 2-input / 1-output selector, 402 is a comparator, 4
Reference numeral 03 is an inverter, and if the input A> the input B, the output of the comparator 402 becomes “1”, and the selector 401 outputs the signal input to the terminal A (that is, the input A).
On the other hand, if input A ≦ input B, the output of the comparator 402 becomes “0”, and the selector 401 outputs the signal input to the terminal B (that is, input B). That is, the selector 40
1 outputs the maximum value max (A, B).

Further, the selector 404 has an input A> input B
If it is input iA is output, if input A ≤ input B is input
Output iB. Similarly, 405 and 408 are 2-input 1-output selectors, 406 is a comparator, and 407 is an inverter. That is, the selector 405 outputs the maximum value max (C, D), and the selector 408 inputs the input iC if input C> input D.
Is output, and if input C ≦ input D, input iD is output.

Reference numerals 409, 411 and 413 are 2-input 1-output selectors, 410 is a comparator, 412 is an inverter,
If max (A, B)> max (C, D), the output of the comparator 410 becomes "1", and the selector 409 outputs max (A, B).
On the other hand, if max (A, B) ≦ max (C, D), the output of the comparator 410 becomes “0”, and the selector 409 outputs max (C, D). That is, the selector 409 outputs the maximum value max (A, B, C, D).

Further, the signal imx is determined as follows depending on which of the inputs A to D has the maximum value. That is, the signal imx indicates the position (coordinates) where the lightness signal L ^* has the maximum value in the pixel block. When A is the maximum value: imx (3,2) = iA and imx (1) = '0' and imx (0) = '0' When B is the maximum value: imx (3,2) = iB and imx (1) = '0' and imx (0) = '1' When C is the maximum value: imx (3,2) = iC and imx (1) = '1' and imx (0) = '0' D Is the maximum value: imx (3,2) = iD and imx (1) = '1' and imx (0) = '1' In FIG. 18, reference numeral 215 denotes the main scanning direction minimum value detection circuit, which is connected to the terminal A. Output of F / F213, F / F212 to terminal B
Output, F / F211 output to terminal C, F / F2 output to terminal D
10 outputs, that is, signals obtained by delaying the signal min by one pulse of the signal CLK are input. In addition, F / F to terminal iA
213, the output of the F / F 212 to the terminal iB, the output of the F / F 211 to the terminal iC, the output of the F / F 210 to the terminal iD, that is, the signal imn delayed by one pulse of the signal CLK, respectively.

FIG. 21 shows a minimum value detection circuit 215 in the main scanning direction.
3 is a block diagram showing a detailed configuration of FIG. The details of the operation are omitted because they are substantially the same as the case of the maximum value detection circuit 214 in the main scanning direction, but the selector 507 sets the minimum value max (A, B, C, D).
Is output. Further, the signal imn is determined as follows depending on which of the inputs A to D has the minimum value. That is,
The signal imn indicates the position (coordinates) where the lightness signal L ^* has the minimum value in the pixel block.

When A is the minimum value: imn (3,2) = iA and imn (1) = '0' and imn (0) = '0' When B is the minimum value: imn (3,2) = iB and imn (1) = '0' and imn (0) = '1' When C is the minimum value: imn (3,2) = iC and imn (1) = '1' and imn (0) = ' When 0'D is the minimum value: imn (3,2) = iD and imn (1) = '1' and imn (0) = '1' In FIG. 18, 216 is a subtractor, which is the brightness in the pixel block. The value obtained by subtracting the minimum value min from the maximum value max of the signal L ^* is output.

Reference numerals 217 to 219 are 2-input 1-output selectors, and 220 to 222 are F / Fs. Selector 217-
As shown in FIG. 33, the signal XD1 input to the selection terminal S of the 219 becomes "0" only when the value of the signal XPHS is 1 in synchronization with the signals XPHS and CLK, and otherwise becomes "1". 'Is. Therefore, the selector 217 and the F / F 220 are located at the position (coordinates) where the brightness signal L ^* has the maximum value in the pixel block.
, A selector 218 and an F / F 221 output a signal LGAIN which is a difference between a maximum value and a minimum value of the lightness signal L ^* in the pixel block, and a selector 218 and an F / F 222 indicate a signal LGAIN in the pixel block. The signal LMN indicating the position (coordinates) where the lightness signal L ^* has the minimum value is output at the timing shown in FIG.

[Chromaticity Component Encoder] FIG. 22 shows the chromaticity information a ^* ,
It is a block diagram which shows the detail of the encoder b1114 which encodes b ^* . Further, FIG. 34 shows an example of the timing chart. In FIG. 22, reference numerals 729 to 731 denote line memories, which delay the input chromaticity signal a ^* by one line to form the signal into 4 × 4 pixel blocks. Reference numeral 724 is a quantizer, which is a line memory 729-7.
The a ^* of the 4 × 4 pixel block input from 31 is quantized.

In a similar manner, 725 to 727 are light lines, respectively.
Input chromaticity signal b ^*1 line late
To give the signal a 4 × 4 pixel block.
is there. Reference numeral 728 is a quantizer, which is a line memory 725-72.
B of 4 × 4 pixel block input from 7^*Quantize
It Outputs of quantizers 724 and 728, ie signal a
mean, signal again and signal bmean, signal gain are combined.
Becomes ab-code. Where the signal amean is a^*Direct current
Min, signal again is a^*Is the AC component of and the signal bmean is
b^*DC component of, bgain is signal bgain^*Is the AC component of.

23 and 24 are block diagrams showing a detailed configuration example of the quantizer 724 or the quantizer 728.
In the figure, reference numerals 601 to 624 denote F / Fs, which delay each of the four input signals by 6 pulses in synchronization with the rising of the signal CLK and synchronize with the encoder a1113 of the lightness information L ^* .

Reference numerals 625 and 626 are 4-input 1-output selectors. When 0 is input to the terminal S, the signal input to the terminal A is input, and when 1 is input to the terminal S, the signal is input to the terminal B. A signal input to the terminal C when 2 is input to the terminal S and a signal input to the terminal D when 3 is input to the terminal S are selected and output. Selector 6
The upper 2 bits (that is, bits 3 and 2) of the signal LMX are input to the terminal S input of 25, and the upper 2 bits (that is, bits 3 and 2) of the signal LMN are input to the terminal S of the selector 616.

On the other hand, 627 to 630 are F / Fs, respectively.
Then, the lower 2 bits (that is, bits 1 and 0) of the input signal LMN and the lower 2 bits (that is, bits 1 and 0) of the signal LMX are delayed by 4 pulses in synchronization with the rising edge of the signal CLK. 631 to 634 are also F / F, and delay the signal input from the selector 625 by 1 to 4 pulses in synchronization with the rising edge of the signal CLK. Each of 635 to 638 is also an F / F and outputs the signal input from the selector 626.
It is delayed by 1 to 4 pulses in synchronization with the rising edge of CLK.

Reference numerals 639 and 640 denote 4-input 1-output selectors. The selector 639 has an F / F6 at its selection terminal S.
According to the lower 2 bits of the synchronized signal LMX input from 30, the signal input from any of the F / F 631 to 634 is selected and output, and the selector 640 outputs the F / F 630 to its selection terminal S. Synchronized signal LMN input from
The signal input from any one of the F / Fs 635 to 638 is selected and output according to the lower 2 bits of. as a result,
In the 4 × 4 pixel block, the value of the chromaticity signal a ^* or b ^{* at} the position (coordinate) where the lightness signal L ^* has the maximum value is the selector 63.
9 is output as a signal MX, and the value of a ^* or b ^{* at} the position (coordinates) where the brightness signal L ^* becomes the minimum value is the selector 640.
Is output as a signal MN.

On the other hand, an average value calculator 641 outputs the average value (A + B + C + D) / 4 of the signals input to its input terminals A to D. 642 to 645 are F / Fs, and an average value calculator 641
The signal input from is synchronized with the rising edge of signal CLK 1
Delay by ~ 4 pulses. 646 is an average value calculator, F /
The average value (A + B + C + D) / 4 of the signals input from the F622 to 645 to the input terminals A to D is output as the signal ME. As a result, the average value of a ^* or b ^* in the 4 × 4 pixel block is output as the signal ME.

On the other hand, 647 to 650 are F / Fs, which delay the input signal LGAIN by 4 pulses in synchronization with the rising edge of the signal CLK and output it as a signal LG in synchronization with each signal MX, MN, ME. . In FIG. 24, signals MX, MN, ME, and LG are F / F.
651 to 654 are synchronized with the rising edge of the signal CLK.

A subtractor 655 subtracts the signal MN from the signal MX.
Jijiru That is, the signal L within the 4 × 4 pixel block^*Is the maximum
Signal a at the position where the value becomes the minimum and the position where the value becomes the minimum^*Also
Is b^*The difference MX-MN of is output. 657 is an LUT,
Signal a output from the F / F656 to the upper address terminal ^*
Or b^*Input the difference MX-MN and its lower address terminal
The signal LG output from the F / F 661 is input to. LUT
657 is a chromaticity signal a in the 4 × 4 pixel block^*Also
Is b^*Amplitude MX-MN of AC component and brightness signal L^*AC component of
Quantize ratio (MX-MN) / LG value with LG of 3 to 3 bits
Data is written in advance, and the data corresponding to the input
Output.

658 and 662 are 2-input 1-output selectors, and 659 and 663 to 667 are F / Fs. As a result,
The signal gain and the signal me at the timing shown in FIG.
Output an. Further, 668 is also a 2-input 1-output selector, and when the above-mentioned signal E-code is "1", that is, when the block is an edge portion, the upper 6 bits of the signal ME are signal me.
When the signal E-code is “0”, that is, when the block is a non-edge portion, the signal ME (8 bits) is output as the signal mean.

[Code Length] FIG. 3 is a diagram showing an example of the code length of a 4 × 4 pixel block in the coding system of the present embodiment. In the figure, 11 indicates a code length when it is determined that the pixel block is an edge portion, and 12 indicates a code length when it is determined that the pixel block is a non-edge portion.

One bit is assigned to the E-code which is a determination signal as to whether or not the pixel block at the beginning is an edge portion. In addition, the signal AVE, which is the DC component of the brightness information L ^* ,
Allocate 8 bits. At the edge portion, the brightness information L
^Since the AC component information of ^* is important, the number of bits to be assigned to the signals L1, L2, M, and H indicating the AC component is larger than that of the non-edge portion, and 9, 9, 9, and 8 bits are assigned, respectively. In the non-edge part, there are 8, 8, 8, and 7 bits, respectively.

On the other hand, the signals amean and bmean indicating the DC components of the chromaticity information a ^* and b ^{* have} 6 bits each at the edge portion,
Allocate 8 bits in the non-edge part. This is because the information on the DC component in the non-edge portion is more important than that in the edge portion. Further, 4 bits are assigned to each of the edge part and the non-edge part to the signals again and bgain indicating the AC component of the chromaticity information.

As a result, when the pixel block is an edge portion, a total of 43 bits is assigned to the lightness information L ^* and a total of 20 bits is assigned to the chromaticity information a ^* and b ^*, and the pixel block is a non-edge portion. In some cases, a total of 39 bits are assigned to the lightness information L ^* and a total of 24 bits are assigned to the chromaticity information a ^* and b ^* .
Together with the determination signal E-code indicating whether or not it is an edge portion, a code having a fixed length of 64 bits is obtained.

[Device Timing Chart] FIG. 30 is an example of a device timing chart of this embodiment. In the figure, the signal START is a signal indicating the start of the document reading operation.
The signal WPE represents a section in which the image scanner reads the original image, performs the encoding process, and writes in the memory. Signal IT
OP is a signal indicating the start of printing operation, and signals MPE, CPE, YPE, KP
E is a magenta semiconductor laser 1216, a cyan semiconductor laser 1215, and a yellow semiconductor laser 12 shown in FIG.
14 and black semiconductor laser 1213 respectively.

As shown in the figure, the signals CPE, YPE and KPE are
The signal MPE is delayed by time t1, t2, t3, respectively, which is controlled by the following relation with respect to the distances d1, d2, d3 shown in FIG. t1 = d1 / v, t2 = d2 / v, t3 = d3 / v (4) The signal HSYNC is the main scanning synchronization signal, and the signal CLK is the pixel synchronization signal. The signal YPHS is a count value of a 2-bit main scanning counter, and is generated by a circuit composed of an inverter 1001 and 2-bit counters 1002 and 1003, an example of which is shown in FIG.

The signal BLK is a synchronization signal in units of 4 × 4 pixel blocks, and is processed in units of 4 × 4 blocks at the timing indicated by BDATA. [Area Processing] FIG. 28 shows a 4 × 4 area processing circuit 1115.
4 is a block diagram showing a configuration example of -4. FIG.

In the figure, CLK is a pixel synchronization signal, HSYNC
Is a main scanning synchronization signal. Line memories 901 to 903 give a delay of one line. Each signal of X1, X2, X3 is one line in the sub-scanning direction with respect to the input signal X,
Delayed by 2 lines and 3 lines. 904 and 909 are adders, 905 to 908 are F / F, and as a result, the number of those which are '1' among X, X1, X2 and X3 corresponding to 4 pixels in the sub scanning direction of the binary signal X. To count.

Reference numeral 910 is a 2-input 1-output selector, and 911.
Is a NOR gate, 912 is an F / F, and X = counted in 4 × 4 block units in synchronization with the signal BLK generated from bit 0 of the signal XPHS and bit 1 of the signal XPHS.
The number of pixels C1 which is "1" is calculated and compared with the comparison value C2 preset in the register 913, and the output Y becomes "1" only when C1> C2, and otherwise "0".
And is output at the timing indicated by the signal BDATA in FIG.

The characteristic here is that the codes L-code and ab-code obtained by encoding and the characteristic signals K1 and K2 extracted by the characteristic extracting circuit 1115 are shown in FIG.
That is, there is a one-to-one correspondence in units of × 4 blocks.
That is, even when the image code and the characteristic signal are extracted in units of each 4 × 4 pixel block and stored and read at the same address in the memory or an address calculated from the same address, they can be read correspondingly.

That is, by storing the image information and the characteristic (attribute) information in association with each other at the same address in the memory or an address calculated from the same address, for example, the writing and reading control circuits of the memory can be made common and simplified. Further, even when the editing processing such as scaling / rotation is performed on the memory, it can be performed by a simple process, and the system can be optimized.

FIG. 31 is a diagram showing an example of a specific area process for character pixel detection. For example, FIG. 31 (a)
A portion 1201-1 of the image of the original 1201 as shown in FIG.
The result of the determination as to whether each pixel is a character pixel by the character area detection circuit 1115-2 is shown by a circle in FIG. That is, the circled pixels indicate the character area detection circuit 1115.
-The pixel detected at -2, the output corresponding to the pixel is K2 '
= '1', the output corresponding to the other pixels is K2 '
= '0'.

The determination result is stored in the register 913 in the area processing circuit 1115-4 shown in FIG. 28, for example.
By setting C2 = 4 and performing area processing, in each 4 × 4 block, there are five or more pixels that are determined to be character pixels, and when there are four or less pixels, the character area block is used. It is determined to be a block other than. Therefore, the output of the area processing circuit 1115-4 is the noise-reduced signal K2, an example of which is shown in FIG.
become.

Similarly, the black pixel detection circuit 1115-1
For the determination result K1 ′ of
A signal K1 corresponding to 4 × 4 blocks can be obtained by processing in 15-3. [Lightness Code Decoder] FIG. 35 is a block diagram showing a detailed configuration example of the decoder a1117 for decoding the lightness code signal L-code.

The decoder a1117 has the image memory 1116.
The lightness information L ^* is decoded by decoding the signal L-code read from and performing inverse Hadamard transform. The inverse Hadamard transform is an inverse transform of the Hadamard transform shown by the equation (3) and is defined by the equation (5). Where H is a 4 × 4 Hadamard matrix H ^T is the transposed matrix of H On the other hand, the Hadamard transform and the inverse Hadamard transform are linear operations, and when the Hadamard transform or the inverse Hadamard transform of the matrix X is expressed as H (X), the equation (6) generally holds.

H (X1 + X2 + ... + Xn) = H (X1) + H (X2) + ... + H (Xn) (6) Using this property, the inverse Hadamard transform is performed by the encoder a1.
Each frequency band defined in 113 is decomposed and performed in parallel. Here, the data matrix decoded from the code L1 is YL1, and the data matrix decoded from the code L2 is YL1.
Data matrix decoded from L2, code M is YM, code H
When the data matrix decoded from is set to YH, equation (7) holds.

H (YL1 + YL2 + YM + YH) = H (YL1) + H (YL2) + H (YM) + H (YH) (7) In FIG. 35, 1601 to 1604 are LUTs, respectively.
Then, for example, it is configured by a ROM or the like, and each LUT holds in advance the result of previously calculating the decoding process and the inverse Hadamard transform process. The code of L1 is assigned to the lower address of the LUT 1601.
At the lower address of the LUT 1602, the code of L2 is
At the lower address of 1603, the code of M is LUT160
The code of H is input to the lower address of 4, while the signal XP is input to the upper address (4 bits) of each LUT.
HS, YPHS and E-code are input.

Further, reference numeral 1605 denotes an adder, which is a part for performing addition corresponding to the expression (7), and which has frequency components (L1, L2,
Add the inverse Hadamard transform results of (M, H). The addition result is
It is an AC component of the brightness information L ^{* in} the 4 × 4 pixel block, and is output as an AC component signal LAC of the brightness information L ^* via the F / F 1606. If you want to decode all at once without using this method, the total of at least 31-bit code, 4-bit coordinates (XPHS, YPHS) and 1-bit E-code, that is, 36-bit address space ( In other words, a LUT with 64 Gbytes) is required, which is not realistic to realize. By using the above scheme, at most 1
It is only necessary to prepare a few 4-bit (9-bit code + 4-bit coordinate + 1-bit E-code) address space (16 kbyte) ROMs, which makes the configuration extremely simple. Also, it is easy to deal with the case where the code length is changed.

Reference numeral 1607 denotes an adder, which obtains a lightness signal L ^* by adding the signal LAC input from the F / F 1606 and the average value AVE input from the F / F 1609. The lightness signal L ^* output from the adder 1607 is F / F1.
At 608, the signal is output in synchronization with the rising edge of the signal CLK. [Chromaticity Code Decoder] FIG. 36 is a block diagram showing a detailed configuration example of the decoder b1118 for decoding the lightness code signal ab-code. .

The signal ab read from the image memory 1116
-code is synchronized with the rising edge of the signal CLK at the F / F 1701 and then decomposed into a-code and b-code.
It is decomposed into amean, bgain and bmean. Multiplier 17
The signal again decomposed in 02 (the signal a ^*
To the representative of the amplitude and the signal L ^* ratio of amplitudes), multiplied by the signals L ^* of the AC component LAC, by adding the signal amean a DC component of the signal a ^* in the adder 1704, decodes the signal a ^* . The decoded signal a ^* is output by the F / F 1706 in synchronization with the rising edge of the signal CLK.

Similarly, the signal bgain decomposed by the multiplier 1703 (representing the ratio of the amplitude of the signal b ^{* and} the amplitude of the signal L ^* as described above) is multiplied by the AC component LAC of the signal L ^* , and the adder is added. At 1705, the signal bmean, which is the DC component of the signal b ^* , is added to decode the signal b ^* . The decoded signal b ^* is F
/ F1707 is output in synchronization with the rising edge of the signal CLK.

[Color Space Converter] FIG. 12 shows the color space converter 1.
It is a block diagram which shows the structural example of 119. In the figure, reference numeral 2501 denotes a color space converter for converting an L ^* a ^* b ^* signal into an RGB signal, which is converted by the following equation. Note that βij '(i, j = 1,2,3) in equation (8) is equal to βij' in equation (2)
It is the inverse matrix of (i, j = 1,2,3). In addition, αij 'in equation (10)
(i, j = 1,2,3,4) is the inverse matrix of αij (i, j = 1,2,3,4) in the equation (1).

Reference numerals 2502 to 2504 denote logarithmic converters for converting the following equation. A black extraction circuit 2514 generates a black signal K1 by the following equation.

BK1 = min (M1, C1, Y1) (12) 2505 to 2508 are multipliers, M1, C1, Y1, BK1
Each signal of is multiplied by a predetermined coefficient a1, a2, a3, a4. 2515
Is an adder, which adds the outputs of the multipliers 2505-2508. That is, the output of the following formula is obtained from the adder 2515.

M (, C, Y or K) = a1M1 + a2C1 + a3Y1 + a4BK1 (13) 2509 to 2513 are registers, and the density signal generation unit m1
A11, a21, a31, a41, 0 in the same register of 141, and a12, a22, a32, a42, in the same register of the density signal generation unit c1142.
0 is stored in the same register of the density signal generation unit y1143 as a13, a
23, a33, a43, 0, and a14, a24, a34, a44, a14 'are set in the same register of the density signal generator k1144, respectively.

2531 to 2533 are AND gates and 253.
0 is a 2-input 1-output selector, 2520 is a NAND gate, and as a result, the black pixel determination signal K1 and the character area determination signal K2
It is determined whether or not the pixel is included in the black character area based on the logical product of a, a1, a2, a3, a4 as shown in an example in FIG.
Select each value of. Further, when the pixel is not included in the black character area, the processing of the following expression (14) is performed, and when the pixel is included in the black character area, the processing of the following expression (15) is performed.

[0090] That is, in the black character area, as shown in equation (15),
By outputting with a black (K) single color, it is possible to obtain output without color misregistration. On the other hand, (1
As shown in the equation 4), four colors of MCYK will be output, but the signal M based on the RGB signal read by the CCD sensor
1, C1, Y1, BK1 are corrected to the MCYK signal based on the spectral distribution characteristic of the toner by the calculation of the equation (14) and output.

[Spatial Filter] FIG. 26 shows the spatial filter 1
It is a block diagram which shows the structural example of 121. In the figure, reference numerals 801 and 802 denote line memories, respectively, which delay the input image signal by one line. 80
3 to 809 are F / Fs, and F / Fs 803 and 804
Delays the input image signal by 2 pixels, and the F / F805
˜807 delay the input image signal by one pixel each, and F / Fs 808 and 809 delay the input image signal by two pixels.

810 and 811 are adders,
The adder 810 adds the output of the F / F 805 and the output of the F / F 807, and the adder 811 adds the output of the F / F 804 and the F / F 804.
/ F809 output is added. Reference numerals 812 to 814 denote multipliers, respectively. The multiplier 812 outputs the coefficient b1 to the output of the adder 810, and the multiplier 813 outputs the coefficient b0 to the output of the F / F 805.
The multiplier 814 multiplies the output of the adder 811 by the coefficient b2. The outputs of the multipliers 812 to 814 are added by the adder 815.

On the other hand, 816 to 821 are registers, respectively, and the values b11, b12, b01, b02, b21 and b22 are held in advance by the respective registers. 822 to 824 are selectors, which are signals indicating whether or not the pixel is included in the character area.
The value held in the registers 816 to 821 is selected according to K2 and set in the coefficients b1, b2 and b2. FIG. 27 is a diagram showing an example of the relationship between the signal K2 and the coefficients b0, b1 and b2.
For example, b01 = 4/8, b11 = 1/8, b21 = 1/8, b02 = 12/8, b12 = -1 / 8,
When the value b22 = -1 / 8 is set in the registers 816 to 821 in advance, a smoothing filter is formed in K2 = '0' (that is, non-character area pixels) as shown in FIG. Removes high frequency noise from the image.
On the other hand, in K2 = '1' (that is, the character area pixel), the edge emphasis filter is formed to emphasize the edge portion of the character.

[Pixel Correction Circuit] FIG. 7 shows a pixel correction circuit 11
22 is a block diagram showing a configuration example of 22. FIG. In the figure,
CLK is a pixel synchronizing signal and HSYNC is a horizontal synchronizing signal. Four
Line memories 01 and 402 each delay the input image signal by one line.

F / Fs 403 to 411 are F / F 403.
˜405 delays the input image signal by one pixel each, and F / Fs 406 to 408 delay the image signal input from the line memory 401 by one pixel respectively.
The F / Fs 409 to 410 delay the image signals input from the line memory 402 by one pixel. As a result, the F / Fs 403 to 411, as shown in an example in FIG. 11, have a pixel of interest X22 and eight peripheral pixels X11 and X1 centered around X22.
A total of 9 pixels of 2, X13, X21, X23, X31, X32, X33 are output.

Reference numerals 411 to 414 denote pixel edge detection circuits.
As shown in an example in FIG. 10, | A for three inputs A, B, and C
The value -2B + C | / 2 is output. The target pixel X22 is input to all of the input terminals B of the four pixel edge detection circuits.
Further, X12 and X32 are input to the input terminals A and C of the edge detection circuit 411, respectively, and as a result, a = | X12-2.X22 + X
32 | / 2 is output. This a is the absolute value of the secondary differential amount in the sub-scanning direction indicated by θ1 in FIG. 11, and represents the edge strength in the θ1 (sub-scanning) direction.

X11 and X33 are input to the input terminals A and C of the edge detection circuit 412, respectively, and as a result, b = | X11-
2 · X22 + X33 | / 2 is output, but this b is the absolute value of the second derivative amount in the diagonally right downward direction indicated by θ2 in FIG.
It represents the strength of the edge in the (right diagonal down) direction. X21 and X23 are input to the input terminals A and C of the edge detection circuit 413, respectively, and as a result, c = | X21-2.X22 + X23 | / 2 is output. This c is θ3 in FIG. Is the absolute value of the secondary differential amount in the main scanning direction, and represents the edge strength in the θ3 (main scanning) direction.

X31 and X13 are input to the input terminals A and C of the edge detection circuit 414, respectively, and as a result, d = | X31-
2 · X22 + X13 | / 2 is output, but this d is the absolute value of the second derivative amount in the upper right direction shown by θ4 in FIG.
It represents the strength of the edge in the (upper right) direction. The outputs of these edge detection circuits 411 to 414 are the maximum value detection circuit 41.
Input to 5. The maximum value detection circuit 415 is input
It is determined which of a, b, c and d is the maximum, and the determination result is output as a 2-bit signal y1y0.

FIG. 8 is a block diagram showing a detailed configuration example of the maximum value detection circuit 415. In the figure, 421 is a comparator, which compares inputs a and b, and when a> b, outputs “1”, a
When ≦ b, '0' is output. Reference numeral 422 denotes a 2-input 1-output selector, which is a comparator 421 input to the select terminal S.
Depending on the result of the comparison, the input a or b is selected and output. That is, the maximum value max (a, b) of a or b is output. Similarly, the comparator 423 outputs the comparison result of the inputs c and d, and the selector 424 outputs the maximum value max (c, d) of c or d.

Further, the maximum values max (a, b) and max (c, d) are
The signal y1 is compared by the comparator 425. That is, y1 = when a or b is the maximum in input a, b, c, d
It becomes "1" and y1 = "0" when c or d is the maximum. Reference numeral 428 is an inverter, and 426, 427, and 429 are two-input NAND gates, respectively, and as a result, inputs a, b, c, d
In y, y0 = "1" is output when a or c is maximum, and y0 = "0" is output when b or d is maximum.

That is, the maximum value circuit 415 uses the maximum value max (a, b, c, d) of a, b, c or d to obtain the signal y of the following relation.
Output 1y0. When max (a, b, c, d) = a y1y0 = '11 'max (a, b, c, d) = b y1y0 = '10' max (a, b, c, d) = c When y1y0 = '01 'max (a, b, c, d) = d y1y0 = '00' Again, in FIG. 7, 416 to 419 are smoothing circuits respectively, and as shown in FIG. , (A + 2B + C) / 4 is output for three inputs of A, B, and C. Four smoothing circuits 4
The target pixel X22 is input to all of the input terminals B of 16 to 419.

Further, X12 and X32 are input to the input terminals A and C of the smoothing circuit 416, respectively, and as a result, a '= (X12 +
2 · X22 + X32) / 4 is output, and this a ′ represents the result of smoothing processing in the sub-scanning direction indicated by θ1 in FIG. X11 and X33 are input to the input terminals A and C of the smoothing circuit 417, respectively, and as a result, b ′ = (X11 + 2 · X22 + X33) / 4 is output. This b ′ is shown in FIG. Shows the result of the smoothing process in the diagonally right downward direction indicated by θ2.

X21 and X23 are input to the input terminals A and C of the smoothing circuit 418, respectively, and as a result, c '= (X21 + 2.X22
Although + X23) / 4 is output, this c'represents the result of smoothing processing in the main scanning direction indicated by θ3 in FIG. X31 and X13 are input to the input terminals A and C of the smoothing circuit 419, respectively, and as a result, d ′ = (X31 + 2 · X22 + X13) / 4 is output. This d ′ is shown in FIG. Shows the result of the smoothing processing in the diagonally upper right direction indicated by θ4.

The outputs of the smoothing circuits 416 to 419 are input to the 4-input / 1-output selector 420. The selector 420 selects and outputs any one of a ', b', c ', and d'input in the following relationship according to the signal y1y0. When y1y0 = '00 ', b'is output When y1y0 = '01', a'is output When y1y0 = '10 ', d'is output When y1y0 = '11', c'is output Therefore, the pixel correction circuit 1122 The output of is as follows.

When the edge amount in the θ1 direction is maximum, the smoothing output in the θ3 direction is maximum When the edge amount in the θ2 direction is maximum, the smoothing output in the θ4 direction When the edge amount in the θ3 direction is maximum, the smoothing output in the θ1 direction θ4 direction Smoothing output in the θ2 direction when the edge amount is maximum [pixel correction result] FIG. 32 is a diagram showing an example of the image correction result.

When an image having a density pattern as shown in FIG. 10A is subjected to encoding / decoding processing by block encoding, as shown in FIG. Raggedness may appear in units of 4 × 4 pixels. Therefore, by performing the above-described smoothing process on the same figure (b), as shown in the same figure (c), it is possible to obtain an image in which the roughness is reduced.

For example, the pixel indicated by A in FIG. 11B has a high density as compared with the pixel corresponding to A in FIG. A pixel is
Since the amount of edge (density gradient) in the direction indicated by θ4 in FIG. 11 is larger than the amount of edge in the other directions, it is smoothed in the direction of θ2 orthogonal to θ4 and corrected to a lower density. Similar corrections are made for the other pixels, and as a result, as shown in FIG. 7C, the overall shading is reduced.

Since the smoothing process is performed in the direction orthogonal to the density gradient, the sharpness of the character portion is not impaired. [Interface Circuit] FIG.
FIG. 63 is a block diagram showing a configuration example of 63. In the figure,
Reference numerals 21 to 25 denote tristate gates, which are controlled by control signals OEA, OEB, OEC, OED or OEE, respectively. Table 3 shows a control example of the tri-state gates 21 to 25.

Reference numeral 26 is an image signal input, 27 is an image signal output, and 28 and 29 are input / output to / from other copying machines. A certain copying machine connected to the input / output 28 (A side) and the input / output 29 ( Other copying machines connected to the B side) are sequentially connected by an interface cable, and have a form as shown in FIG.

[0110]

[Table 3] As shown in Table 3, when the stand-alone device, that is, each copying machine operates independently, the signal OEA is set to "0" and the input image signal is sent to the image processing circuit in the subsequent stage through the tri-state gate 21, and Other control signals are set to "1" to eliminate the connection with the outside.

In the case of printing one original image with a multi-strip device, that is, a plurality of devices, "at the time of output" in which an image signal read by itself is transmitted to another device and a device connected to the input / output 28 side. Receives image signals from the printer and prints "1 at input"
And "input 2" in which an image signal is received from a device connected to the input / output 29 side and printed. At the time of “outputting”, the signals OEA, OEB, OED are set to “0” and the signals OEC, OEE are set to “1”, so that the input image signal is set to the tristate gate 21.
To the image processing circuit in the subsequent stage via the tristate gates 22 and 24, and also to other devices.

"1 at the time of input" means that the signals OEC, OED are set to "0" and the signals OEA, OEB, OEE are set to "1", so that the input / output 2
The image signal input from the 8 side is sent to the image processing circuit in the subsequent stage via the tristate gate 23, and is also sent to the input / output 29 side via the tristate gate 24. "2 at input" sets signals OEB, OEE to "0" and signals OEA, OEC, O
By setting ED to “1”, the image signal input from the input / output 29 side is sent to the image processing circuit in the subsequent stage via the tristate gate 25, and at the same time, the tristate gate 22
And also to the input / output 28 side.

[Calibration of Image Forming Means] In the present embodiment, a plurality of copying machines are operated substantially simultaneously by the same image signal to output an image. It is important to maintain image stability in the plurality of copying machines. Is. Therefore, each copying machine has a test print function, and the output image thereof is used to correct the image output characteristics of the copying machine and to check whether the characteristics of the copying machine are within the correctable range.

At the time of test printing, as shown in Table 1, by setting the signal OE7 shown in FIG. 1 to "0" and the signal OE6 to "1", the test pattern from the pattern generator 1161 is output. To do. FIG. 42 is a diagram showing an example of the test image output by the test print.

In the figure, reference numerals 2801 to 2804 are test output portions of 8 gradations, 2801 is magenta, and 2
802 is printed in cyan, 2803 is printed in yellow, and 2804 is printed in black. The gradation characteristics peculiar to the copying machine appear in these four-color 8-gradation test patterns. That is, depending on the individual difference of the copying machine, there are some with low density and some with high density, but the characteristics are clearly expressed and the image output characteristics of the copying machine can be grasped by measuring the density of this test image. .

In this embodiment, a plurality of copying machines (see FIG.
(1) to (4) shown in 1), the test image obtained as a result is placed on the platen glass 1201 of the same copying machine (for example, copying machine 1), and read by CCD 1208 of the copying machine. Then, the density characteristic of the copying machine that outputs the test image is calculated. The advantage of reading with the same copier is that the output from multiple copiers is read individually. The advantage of using one copier as a reference is that correction errors caused by variations in the reading characteristics of each copier It is possible to prevent.

Further, device identification information such as 2805 is added on the test image. This information is
The copying machine is composed of, for example, a white or black mark group as indicated by 2805a to 2805e, and represents which copying machine outputs the test image. That is, by identifying the state of each mark (that is, white or black) and associating it with a binary number, it is possible to make a one-to-one correspondence between the copying machine and the test image. That is, for example, the device identification information 2810 shown in FIG. 43 is read as “00000” and the first copying machine,
The same 2811 is read as '00001' and the second copying machine, and the same 2812 as '00010' and the third copying machine, 2
813 is read as '00011' and the fourth copying machine, 28
14 is read as "00100", which corresponds to the fifth copying machine. The device identification information is shown in FIG.
It is not limited to the one shown in FIG. 2 or FIG. 43, and may be a bar code or a symbol including numbers and letters.

Since this embodiment has such a function, the user of this embodiment causes the copying machine to read the test image without being aware of which copying machine outputs the test image. Then, the copy machine that has output the test image can be corrected. [Structure of Image Forming Means] In this embodiment, a plurality of copying machines are operated with the same image signal at substantially the same time to perform printing, but it is important to maintain the image stability of the plurality of copying machines. Therefore, each copying machine has a test print function, and the image output characteristic of each copying machine is corrected by the output image. The output image can be used to check whether the characteristics of each copying machine are within the correctable range.

At the time of test printing, as shown in Table 1, by setting the signal OE7 shown in FIG. 1B to "0" and the signal OE6 to "1", the test pattern from the pattern generator 1161 is output. To do. FIG. 37 is a diagram showing an example of an image that has been test printed. In the figure, 1
Reference numerals 801 to 1804 denote 8-gradation test output portions drawn by M, C, Y, and K, respectively. The gradation characteristic peculiar to the copying machine appears in the test pattern of these 4 colors and 8 gradations. That is, although there are high and low densities depending on the individual difference of the copying machine, the characteristics of the copying machine can be represented clearly and the image output characteristics of the copying machine can be grasped by measuring the density of this test print. .

In this embodiment, this test print is placed on the platen glass 1201 and the image thereof is transferred to the CCD 120.
By reading at 8, the density characteristic of the copying machine is obtained. [Procedure of Density Characteristic Correction] FIG. 38 is a flowchart showing an example of the density characteristic correction procedure, which is executed by the control unit 1165 when instructed by an operation unit (not shown) connected to the control unit 1165. Is.

In this figure, in this embodiment, first, in step S1, test pattern output setting is performed. That is, Table 1
The control signals OE1 to OE7 are set so as to print the output of the pattern generator 1161 as shown in FIG. Then, in step S2, the tone correctors 1164 to 1167 are initialized. That is, each gradation corrector is set so that the input signal and the output signal are equal, as shown in FIG.

Subsequently, test printing is performed in step S3. The test print is the pattern generator 116.
1 produces an image as shown in FIG. As mentioned above, this test print is M, C, Y, K
There are eight gradation patterns for each of the four colors, and the gradation values are, for example, 20 (Hex), 40 (Hex), 60 (Hex), 80 (Hex).
x), A0 (Hex), C0 (Hex), E0 (Hex) and FF (Hex).

Subsequently, in step S4, the test print is placed on the platen glass 1201, the image of the test print is read by the CCD 1208, and the result read in step S5 is compared with an appropriate value to obtain a correction value. Is calculated, and it is determined in step S6 whether correction is possible. If the correction is possible, the correction value is written in the gradation correctors 1164 to 1167 in step S7. If the correction is impossible, the density characteristic error is set in step S8.

Subsequently, in step S9, the test pattern output setting is canceled and set in the normal copy operation shown in Table 1, and then the process is terminated. [Principle of Density Correction] FIG. 39 is a diagram showing the principle of density correction. The graph shown in the upper half of the figure shows the output when the test print is read by the CCD, and the horizontal axis shows the gradation value of the test print and the vertical axis shows the read value.
Reference numeral 2001 in the figure shows an appropriate value curve, and reference numeral 2002 shows an example of values actually output from the CCD. The magenta value is a green (G) CCD that has a complementary color relationship with magenta.
The result read in 1102 is used, the cyan value is read in the red (R) CCD 1101 which is in the complementary color relationship of cyan, and the yellow value is read in the blue (B) CCD 1103 which is in the complementary color relationship of yellow. Use the results.
As the black value, the result read by any one of the three CCDs, for example, the green (G) CCD 1102 is used.

Appropriate value curve 2001 and read value curve 2002
Difference appears as a deviation of the output characteristics peculiar to each copying machine.
The graph shown in the lower half of the figure is an example of the correction curve 2003 of the gradation corrector for correcting this deviation, in which the vertical axis represents the input of the gradation corrector and the vertical axis represents the output of the gradation corrector. . The correction curve 2003 includes a proper value curve 2001 and a read value curve 2
The calculation method will be described below.

A point 2004 is an appropriate reading value of the gradation value 20 (Hex), and an intersection 2005 of a straight line drawn from this point in parallel with the horizontal axis and the measured value curve 2002 is a gradation value 20 (Hex). Shows the actual readings for. Therefore, a straight line drawn from the intersection point 2005 in parallel to the vertical axis and the input 20 (He
x) intersection with a straight line drawn parallel to the horizontal axis 2006
Indicates a correction value for the gradation value 20 (Hex).
The correction curve 2003 can be obtained by repeating the same calculation operation for other gradations to obtain a correction value.

[When Density Correction is not Possible] Here, the density correction is not performed in all cases, and the correction cannot be performed when the read value is far from the proper curve. That is, as shown in the upper half of FIG. 40, when the read value curve 2012 is significantly different from the appropriate value curve 2101, the correction curve becomes as shown in 2103, and the correction curves are shown in the regions 2104 and 2015. It is saturated and cannot be corrected. If this saturated part is a very small part of the whole, there is practically no problem, but in the case shown in FIG.

[Density Correction in Double-Link System] In the double-link system, density correction is performed independently for each device. If the system includes a device for which density correction is determined to be impossible, the device other than that device outputs an image. In the above description and the drawings, the coding method based on 4 × 4 block formation has been described as an example, but the present embodiment is not limited to this, and m × n block formation, and others. It is possible to use a coding method such as block quantization or orthogonal transformation of.

Further, in the above description and the drawings,
An example of outputting a gradation image of each developing color as a test print and correcting the output density characteristics has been described, but the present embodiment is not limited to this, and each developing color is mixed as a test print. An image may be output, the image may be read, and, for example, the coefficients a11 to a44 in the equation (14) may be corrected to optimum values. In this case, the tint characteristic of each device is corrected.

Further, in the above description and the drawings,
An example has been described in which each device connected to the multiplex system reads its own test print image by its own image reading means and corrects its own output characteristics. In this case, it is premised that the reading characteristics of the image reading means of the respective devices connected to the multiplex system are substantially the same, and if the reading characteristics vary, the output characteristics of the respective devices cannot be corrected. There are cases.

Therefore, the image of the test print output by each device connected to the multiplex system is read by the image reading means of the specific device, and the correction value of each device is calculated.
If the output characteristics of each device are corrected by transferring the calculated correction value to the corresponding device, the output characteristics of a plurality of devices can be matched accurately. Of course, the same effect can be obtained by directly transferring the image signal output by the image reading means to the corresponding device and calculating the correction value by the device.

As described above, in this embodiment, in a system in which image forming apparatuses such as a color copying machine are connected in series, each apparatus is provided with a density (or tint) calibrating means, so that each apparatus can be calibrated. Whether or not the correction is possible is determined from the result of reading the test print output by, and if the correction is possible, the output characteristics are corrected, so that the densities (or tints) between the images output by the respective devices can be made uniform.

The present invention may be applied to either a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0134]

As described above, according to the present invention, it is possible to provide an image forming system for setting a correction value of an image signal on the basis of an image signal obtained by reading a test image. When is output, it has the effect of aligning the density and color.

[Brief description of drawings]

FIG. 1A is a block diagram illustrating a configuration example of an image processing unit according to an embodiment of the present invention.

FIG. 1B is a block diagram illustrating a configuration example of an image processing unit according to the present exemplary embodiment.

FIG. 2 is a diagram showing a system configuration example of the present embodiment.

FIG. 3 is a diagram showing an example of a code length of a 4 × 4 pixel block in the encoding system of the present embodiment.

4 is a schematic view of the copying machine shown in FIG.

5 is a block diagram showing a configuration example of an interface circuit shown in FIG. 1A.

FIG. 6 is a diagram showing an example of a scaling process.

FIG. 7 is a block diagram showing a configuration example of a pixel correction circuit shown in FIG. 1B.

8 is a block diagram showing a detailed configuration example of a maximum value detection circuit shown in FIG.

9 is a block diagram showing a detailed configuration example of the smoothing circuit shown in FIG.

10 is a block diagram showing a detailed configuration example of the pixel edge detection circuit shown in FIG.

FIG. 11 is a diagram showing an example of a target pixel and its peripheral pixels.

FIG. 12 is a block diagram showing a configuration example of the color space converter shown in FIG. 1B.

13 is a diagram showing an example of selecting coefficients a1, a2, a3 and a4 shown in FIG.

FIG. 14 is a block diagram showing details of an encoder a shown in FIG. 1A.

FIG. 15 is a diagram showing a concept of lightness information encoding according to the present embodiment.

FIG. 16 is a diagram showing the concept of lightness information encoding according to the present embodiment.

FIG. 17 is a block diagram showing a detailed configuration example of the grouping circuit shown in FIG. 14.

FIG. 18 is a block diagram showing a detailed configuration of the LGAIN calculator shown in FIG. 14.

19 is a block diagram showing a detailed configuration example of a sub-scanning direction maximum value / minimum value detection circuit shown in FIG.

20 is a block diagram showing a detailed configuration of a main-scanning-direction maximum value detection circuit shown in FIG.

FIG. 21 is a block diagram showing a detailed configuration of a main-scanning-direction minimum value detection circuit shown in FIG. 18.

22 is a block diagram showing a detailed configuration of an encoder b shown in FIG. 1A.

FIG. 23 is a block diagram showing a detailed configuration of the quantizer shown in FIG. 22.

FIG. 24 is a block diagram showing a detailed configuration of the quantizer shown in FIG. 22.

FIG. 25 is a diagram showing an example of a pixel block according to the present embodiment.

FIG. 26 is a block diagram showing a configuration example of the spatial filter shown in FIG. 1B.

27 is a diagram showing an example of the relationship between the coefficients b0, b1 and b2 shown in FIG. 26 and the signal K2.

28 is a block diagram showing a configuration example of a 4 × 4 area processing circuit shown in FIG. 1A.

FIG. 29 is a diagram showing a configuration example of a counter circuit that outputs a sub-scanning position count signal XPHS and a main scanning position count signal YPHS according to the present embodiment.

FIG. 30 is an example of a device timing chart of the present embodiment.

FIG. 31 is a diagram showing an example of specific area processing related to character pixel detection according to the present embodiment.

FIG. 32 is a diagram showing an example of an image correction result of the present embodiment.

FIG. 33 is an example of a timing chart of the encoder a shown in FIG. 1A.

FIG. 34 is an example of a timing chart of the encoder b shown in FIG. 1A.

[Fig. 35] Fig. 35 is a block diagram illustrating a detailed configuration example of the decoder a in Fig. 1B.

[Fig. 36] Fig. 36 is a block diagram illustrating a detailed configuration example of the decoder b in Fig. 1B.

FIG. 37 is a diagram showing an example of a test print image of the present embodiment.

FIG. 38 is a flowchart showing an example of a density characteristic correction procedure of the present embodiment.

FIG. 39 is a diagram showing the principle of density correction of the present embodiment.

FIG. 40 is a diagram showing an example of a case where density correction is impossible.

41 is a diagram showing an input / output example of an initialization state of the gradation corrector shown in FIG. 1B.

FIG. 42 is a diagram showing an example of a test image output by a test print.

FIG. 43 is a diagram showing a usage example of the device identification information shown in FIG. 42.

[Explanation of symbols]

 1 to 4 full color copying machine (copying machine) 5 to 7 interface cable 205 sub-scanning direction maximum value / minimum value detection circuit 214 main scanning direction maximum value detection circuit 215 main scanning direction minimum value detection circuit 411 to 414 pixel edge detection circuit 416 to 419 Smoothing circuit 704 Hadamard transform circuit 709 Grouping circuit 715 LGAIN calculator 724,728 Quantizer 1163 Interface circuit 1112 Color space converter 1113 Lightness information encoder a 1114 Chromaticity information encoder b 1115 Features Extraction circuit 1116 Image memory 1141 to 1144 Density signal generation unit 1117 Lightness information decoder a 1118 Chromaticity information decoder b 1119 Color space converter 1120 Density converter 1121 Spatial filter 1122 Image correction circuit 1161 Pattern generator 1164 to 1164 67 tone corrector 1165 controller 1212 image processing section 2501 color space transformer 2514 black extraction circuit

Claims (8)

[Claims] 1. An image forming apparatus, which forms an image signal representing a given color test image and information for specifying an image forming apparatus. 2. A common reading unit for reading an image of an original and outputting an image signal, a color test unit for outputting an image signal representing a color test image, and an image output from the reading unit or the color test unit. A correction unit that corrects a signal; and a plurality of forming units that form an image corresponding to an image signal that represents the color test image on a recording medium, the correcting unit that forms the test image formed by the forming unit. An image forming system, wherein a correction value of an image signal is set based on an image signal read by a common reading unit. 3. The image forming system according to claim 2, wherein the forming unit forms, together with the color test image, information for specifying the forming unit on the recording medium. 4. An interface means for exchanging signals with another image forming apparatus is provided between the reading means and the correcting means, and the interface means outputs from the reading means. The image signal received from the other image forming apparatus is output to the correction means, and the image signal is transmitted to another image forming apparatus other than the source of the image signal. The image forming system according to claim 2, wherein the image is transmitted. 5. The correcting means determines whether or not the output characteristic of the forming means can be corrected, and corrects the image signal so that the output characteristic can be corrected if the output characteristic of the forming means can be corrected. The image forming system according to any one of claims 2 to 4, which is characterized. 6. The image forming system according to claim 5, wherein the output characteristic is a density characteristic of an image to be formed. 7. The image forming system according to claim 5, wherein the output characteristic is a tint characteristic of an image to be formed. 8. The correction unit obtains a correction value of an image signal based on an image signal obtained by reading a test image formed by another image forming apparatus by the reading unit, and the correction value is obtained via the interface unit. The image forming system according to any one of claims 2 to 7, wherein the correction value is transmitted to another image forming apparatus.