JP3291056B2 - Image processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus, and more particularly to an image processing method and apparatus for encoding (compressing) and decoding (expanding) full-color image data.

[0002]

2. Description of the Related Art Conventionally, as a device for separating (encoding) full-color image data into brightness information and chromaticity information for each predetermined pixel block, for example, Japanese Patent Application No. 63-1418.
An apparatus disclosed in No. 26 or the like has been proposed.

In such a compression system, for example,
The coding of the AC component of the chromaticity information is performed using the correlation between the brightness information and the chromaticity information in units of 4 pixels × 4 lines. Further, according to the characteristics of the image information, the attribute of the image
And encodes them differently.

[0004]

However, in the above-mentioned conventional example, in the case of a document in which an arbitrary image is macroscopically formed by a combination of artificial patterns at a pixel unit level, such as a halftone image, the brightness information Therefore, there is a problem that the reproducibility of the coded and decoded image is deteriorated. In particular, in the highlight portion, the attribute of the brightness information is not correctly classified, and there is a disadvantage that the image quality is greatly deteriorated because optimal encoding is not performed.

For example, in the case of a halftone original, since the chromaticity of the halftone dot is completely different from the chromaticity of the cloth of the manuscript paper, the image region that looks monotonous macroscopically is also the same as the character region and the like. It will be judged. For this reason, encoding is selected in which the amount of information allocated to the DC component of the chromaticity is small, and a pseudo contour is generated or a highlight portion is roughened.

The present invention has been made in view of the above conventional example. For example, an image formed by macroscopically forming an arbitrary image by combining artificial patterns at a pixel unit level is encoded and decoded. It is an object of the present invention to provide an image processing method and an image processing method that provide good image reproducibility even when the image processing is performed.

[0007]

In order to achieve the above object, an image processing method according to the present invention comprises the following steps. That is, an image processing method for processing a full-color image signal, an input step of inputting a full-color image signal,
A separation step of separating the full-color image signal into brightness information and chromaticity information in pixel block units; and a quantization / encoding by separating the brightness information of the full-color image signal into a DC component and an AC component for each pixel block. A first encoding step of calculating a difference value between a maximum value and a minimum value of brightness information in the pixel block, and a second calculating step of calculating an average value of chromaticity information in the pixel block. 2 calculation steps;
A third calculating step of calculating a difference value between chromaticity information at a position where the brightness information takes a maximum value in the pixel block and chromaticity information at a position where the brightness information takes a minimum value, and the first calculation Calculating a difference ratio indicating a ratio between the difference value calculated in the step and the difference value calculated in the third calculation step;
A second encoding step for encoding, and the second encoding step when the difference value calculated in the first calculation step is larger than a predetermined value.
A non-linear quantized version of the average calculated in the calculating step is output. If the difference calculated in the first calculating step is smaller than a predetermined value, the average calculated in the second calculating step is quantized. And a third encoding step of outputting without encoding.

According to another aspect of the present invention, there is provided an image processing apparatus for processing a full-color image signal, comprising: input means for inputting a full-color image signal; and converting the full-color image signal into brightness information and chromaticity information in pixel block units. Separating means for separating, brightness information of the full-color image signal for each pixel block, first coding means for separating and quantizing and coding the DC component and AC component, and brightness information of the pixel block. A first calculator for calculating a difference value between a maximum value and a minimum value, a second calculator for calculating an average value of chromaticity information in the pixel block, and a maximum value of brightness information in the pixel block. Third calculating means for calculating a difference value between the chromaticity information of the position to be taken and the chromaticity information of the position having the minimum value of the lightness information; and the third calculating means calculates the difference value between the third value and the third value. Calculation A second encoding unit for obtaining and encoding a difference ratio indicating a ratio with respect to the difference value calculated by the unit; and a second encoding unit for encoding when the difference value calculated by the first calculation unit is larger than a predetermined value. A non-linearly quantized version of the calculated average value is output, and the first
An image processing apparatus comprising: a third encoding unit that outputs, without quantizing, the average value calculated by the second calculation unit when the difference value calculated by the calculation unit is smaller than a predetermined value. Is provided.

[0009]

According to the present invention, when encoding an input full-color image signal, the present invention separates the image signal into brightness information and chromaticity information for each pixel block, and sets the maximum brightness information in the pixel block. Calculate the difference between the value and the minimum value,
The average value of the chromaticity information in the pixel block is calculated, and the difference value between the chromaticity information at the position where the maximum value of the brightness information in the pixel block is obtained and the chromaticity information at the position where the minimum value of the brightness information is obtained Is calculated, and a difference ratio indicating a ratio between the calculated difference value of the brightness information and the calculated difference value of the chromaticity information is calculated and encoded. When the difference value of the calculated brightness information is larger than a predetermined value, Non-linearly quantized output of the calculated average value of the chromaticity information is output, and when the calculated difference value of the brightness information is smaller than a predetermined value, the average value of the calculated chromaticity information is not quantized. Operate to output.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

[Explanation of Apparatus Outline (FIG. 1)] FIG. 1 is a block diagram showing an outline configuration of a full-color copying machine which is a typical embodiment of the present invention. In FIG. 1, reference numeral 201 denotes a platen glass on which a document 202 to be read is placed. The original 202 is illuminated by a light source 203, passes through mirrors 204 to 206, and is transmitted to a CCD 2 by an optical system 207.
An image is formed on the image 08. Further, a mirror unit 210 including a mirror 204 and a light source 203 is driven by a motor 209.
Are mechanically driven at a speed (V), and mirrors 205 and 2
The second mirror unit 211 including the drive unit 06 is driven at a speed of 1/2 V, and the entire surface of the document 202 is scanned. Reference numeral 212 denotes an image processing circuit which processes the read image information as an electric signal and outputs it as a print signal.

Reference numerals 213 to 216 denote semiconductor lasers,
The laser beams driven by the print signals output from the image processing circuit unit 212 and emitted by the respective semiconductor lasers form latent images on the photosensitive drums 225 to 228 by the polygon mirrors 217 to 220. 2
Reference numerals 21 to 224 denote developing units for developing latent images using black (Bk), yellow (Y), cyan (C), and magenta (M) toners, respectively. To a full-color printout.

Paper fed from one of the paper cassettes 229 to 231 and the manual feed tray 232 is attracted onto a transfer belt 234 via a registration roller 223 and is conveyed. Synchronized with the paper feed timing,
The toners of the respective colors are developed on the photosensitive drums 225 to 228 in advance, and the toner is transferred to the paper as the paper is transported.

The paper on which the toner of each color is transferred is separated / separated.
The sheet is conveyed, the toner is fixed on the sheet by the fixing device 235, and the sheet is discharged to the sheet discharge tray 236.

[Overview of Image Processing Circuit (FIGS. 2 and 3)] FIGS. 2 and 3 are block diagrams showing the configuration of the image processing circuit 212. 2 to 3, 101 to 103
Are red (R), green (G), and blue (B), respectively.
The outputs from the respective sensors are amplified by the corresponding analog amplifiers 104 to 106 and output as digital signals by the corresponding A / D converters. Reference numerals 110 and 111 denote delay memories, respectively, for correcting a spatial shift between the three CCD sensors 101 to 103.

Reference numerals 151 to 156 denote tristate gate circuits, which are set as shown in Table 1 by a CPU (not shown) in accordance with the contents of the scaling process.
Only when the OE6 signal is "0", the input signal is output. Reference numerals 157 to 160 denote magnification circuits, each of which scales an image signal in the main scanning direction.

Reference numeral 112 denotes a color space converter, which converts an RGB signal into a lightness signal (L ^* ) and chromaticity signals (a ^* , b ^* ). Here, the L ^* , a ^* , b ^* signal is a signal representing a chromaticity component defined as an L ^* , a ^* , b ^* space as an international standard in the CIE, and the L ^* , a ^* , b ^* signal Is calculated according to equation (1). Here, α _ij , X ₀ , Y ₀ , and Z ₀ are constants.

X, Y, and Z are signals calculated and generated based on the RGB signals, and are expressed by equation (2). Here, β _ij is a constant.

Reference numeral 113 denotes an encoder for a brightness signal, and L ^*
The signal is encoded in units of 4 × 4 pixel blocks, and the encoded signal (L-code) is output. Reference numeral 114 denotes a chrominance signal encoder, which encodes a ^* and b ^* signals into 4 × 4 pixels. Encode in block units and output the encoded signal (ab-code).

Reference numeral 115 denotes a feature extraction circuit, which
A determination signal (K ₁') Black picture that causes
Element detection circuit 115a and a determination signal (K₁') And enter 4
It is determined whether or not the inside of the × 4 pixel block is a black pixel area.
4 × 4 area processing circuit 115b for determining
The determination signal (K_Two') Fire
Character region detection circuit 115c, the determination signal (K_Two')
And whether the inside of the 4 × 4 pixel block is a character area
It is composed of a 4 × 4 area processing circuit 115d for making a determination.
You.

Reference numeral 116 denotes an image memory, which is an encoded signal of lightness information (L-code) and an encoded signal of chromaticity information (ab-code).
), A determination signal (K ₁ ) as a result of feature extraction, and
The judgment signal (K ₂ ) is stored.

Reference numerals 141 to 144 denote magenta (M),
This is a density signal generation circuit for cyan (C), yellow (Y), and black (Bk), and has almost the same configuration.

117a, 117b, 117c, and 1
Reference numeral 17d denotes a brightness information decoder which decodes the L ^* signal by using the coded signal (L-code) read from the image memory 116, and outputs 118a, 118b, 118c, and 11
Reference numeral 8d denotes a decoder for chromaticity information, which decodes the a ^* signal and the b ^* signal using the encoded signal (ab-code) read from the image memory 116.

119a, 119b, 119c, and 1
19d is a color space converter, which decodes L ^* , a ^* , b
^* A conversion circuit that converts signals into respective color components of magenta (M), cyan (C), yellow (Y), and black (Bk), which are toner development colors. 120a, 120b, 120
Reference numerals c and 120d denote density conversion circuits, which are ROM or RAM look-up tables (hereinafter referred to as LUTs).
It consists of. 121a, 121b, 121c, and
Reference numeral 121d denotes a spatial filter that corrects a spatial frequency of an output image. 122a, 122b, 122
Reference numerals c and 122d denote pixel correction circuits that correct decoded image data.

[0025]

[Table 1] [Brightness Component Encoder 113 (FIGS. 4 to 14)] FIG. 4 is a block diagram showing a configuration of the brightness information encoder 113. As shown in FIG.
FIGS. 5 and 6 are diagrams conceptually showing the flow of brightness information encoding.

Here, the encoding (compression) of the image data is
As shown in FIG. 7, the processing is performed using a total of 16 pixels of 4 pixels (main scanning direction) × 4 lines (sub scanning direction) as a unit of one block. In FIG. 7, XPHS is a 2-bit signal indicating the main scanning position, and is “0”, “1”, “2”,
A signal indicating a value of “3” is repeatedly output, and YPHS is a 2-bit signal indicating a sub-scanning position.
Signals indicating the values of “1”, “2”, and “3” are repeatedly output. In synchronism with these signals, 1 of 4 pixels × 4 lines
Blocks are cut out.

First, the concept of the brightness information encoding will be described with reference to FIGS.
This will be described with reference to FIG. As indicated by 401 in FIG. 5, the brightness information of one cut-out block is represented by X _ij (i, j = 1 to
4), when this is subjected to a Hadamard transform of 4 rows × 4 columns shown in equation (3), a matrix (Y _ij (i, j = 1 to 4)) as indicated by 402 in FIG. 5 is obtained. obtain. The Hadamard transform is a kind of orthogonal transform, which expands data of 4 rows × 4 columns by a two-dimensional Walsh function, and transforms a signal in a time domain or a spatial domain into a frequency domain or a spatial frequency domain by a Fourier transform. Equivalent to That is, the matrix after the Hadamard transform (Y _ij (i, j = 1 to 1)
4)) is a matrix of input signals (X _ij (i, j = 1 to 4))
Is a signal corresponding to each component of the spatial frequency of.

[0028] Here, H is a 4 × 4 Hadamard matrix, and H ^T is H
Is a transposed matrix.

As in the case of the two-dimensional Fourier transform, the output matrix of this Hadamard transform (Y _ij (i, j = 1
4)), the higher the value of i (i.e., the row position), the higher the spatial frequency component in the sub-scanning direction is arranged, and the larger the value of j (i.e., the column position), the higher the value of i in the main scanning direction. High spatial frequency components are located. In particular,
When i = j = 1, Y _ij = (（) ΣX _ij , and
DC component of input data X _ij (i, j = 1 to 4), that is,
A signal corresponding to the average value (strictly, a signal having a value four times the average value) is output.

Further, generally, the read image is a CC
It is known that there are not a few high spatial frequency components depending on the reading resolution of a reading sensor such as D and the transmission characteristics of an optical system. By utilizing this characteristic, the signal Y _ij (i, j = 1 to 4) after the Hadamard transform is scalar-quantized, and a matrix (Z _ij (i, j) as shown by 403 in FIG.
= 1 to 4).

FIG. 6A shows one block of brightness information X _ij.
The number of bits of each element of (i, j = 1 to 4) is shown in FIG.
Has an output matrix of the Hadamard transform (Y _ij (i, j = 1 to 1)
4)), the output matrix (Z _ij (i, j) of the scalar-quantized Hadamard transform is shown in FIG.
= 1 to 4)) indicates the number of bits of each element. As shown in these figures, Y ₁₁ , that is, the DC component is quantized to 8 bits, which is the largest, to be Z _11, and each Y _ij is quantized with a smaller number of bits as the spatial frequency is higher.

Further, Z_ij(I, j = 1 to 4)
The elements are represented by a DC component and a 4
Group into two AC components. That is, as shown in Table 2.
And AVE as a DC component as Z₁₁Is assigned to L1
Z as scanning AC component_{twenty one}, Z ₁₃, Z₁₄Into groups
And Z2 is added to L2 as a sub-scanning AC component_{twenty one}, Z₃₁, Z ₄₁
Are grouped and assigned, and M is assigned to
Z as the area AC component_{twenty two}, Z_{twenty three}, Z₃₂, Z₃₃Group
And assigned to H as a high-frequency component of main scanning and sub-scanning
Z_{twenty four}, Z₄₂, Z₄₃, Z₄₄And assign them.

[0033]

[Table 2] In FIG. 4, 701 to 703 are line memories,
By delaying each image data by one line, FIG.
The pixel block as shown in FIG. Reference numeral 704 denotes a Hadamard transform circuit, which performs the transform represented by Expression (3).

That is, as shown in FIG.
In synchronization with the PHS signal, X ₁₁ , X ₁₂ , X ₁₃ , and X ₁₄ signals are applied to X ₁ of the Hadamard conversion circuit 704, and X ₂₁ , X ₂₂ , X ₂₃ , and X are applied to X ₂ of the Hadamard conversion circuit 704. ₂₄ signals are stored in X ₃ of the Hadamard conversion circuit 704 as X ₃₁ , X ₃₂ ,
The X ₃₃ and X ₃₄ signals are input to X ₄ of the Hadamard conversion circuit 704, and the X ₄₁ , X ₄₂ , X ₄₃ and X ₄₄ signals are input. Further, the signal subjected to the Hadamard transform is delayed by eight pulses of the CLK signal, and the signals from Y ₁ to Y ₁₁ ,
Y ₁₂ , Y ₁₃ , and Y ₁₄ are Y _{2 of the} Hadamard transform circuit 704.
, Y ₂₁ , Y ₂₂ , Y ₂₃ , and Y ₂₄ are converted into Hadamard transform circuits 7
Y ₃₁ from Y ₃ of _{04, Y 32, Y 33,} Y 34 is, Y ₄₁ from Y ₄ Hadamard transform circuit _{704, Y 42, Y 43,} Y 44 is output.

Reference numerals 705 to 708 denote LUT ROMs for executing the scalar quantization described with reference to FIGS. That is, the output after the Hadamard transform is shown in FIG.
RO is quantized to the number of bits as shown in FIG.
In each of the addresses M705 to 708, data is written in advance so as to output a scalar-quantized result as an input after Hadamard transform and an output corresponding to the XPHS signal. Reference numeral 709 denotes a circuit for performing grouping for vector quantization (hereinafter, referred to as a grouping circuit), and the detailed configuration thereof is shown in FIGS.

In FIGS. 9 and 10, reference numerals 801 to 816 denote flip-flop circuits, each of which applies a delay synchronized with the CLK signal, and is included in one block composed of 4 pixels × 4 lines shown at 403 in FIG. 5 are stored, and AVE, L as shown in 404 of FIG.
Data divided into groups of 1, L2, M, and H are extracted. Reference numerals 817 to 821 denote 2 → 1 selectors. When “0” is input to the S terminal,
The value of the A-side input is output to the output terminal (Y), and when "1" is input to S, the value of the B-side input is output to the output terminal (Y).

Reference numerals 822 to 826 denote flip-flop circuits which apply a delay in synchronization with the CLK signal. XD
0 signal is the CLK signal and XPHS as shown in FIG.
Synchronized with the signal, "0" only when the XPHS signal is "0"
Otherwise, the signal becomes “1”. As a result, for each block composed of 4 pixels × 4 lines,
The scalar quantization results for each group shown in Table 2 are output from the selectors 817 to 821 and the flip-flops 822 to 821.
The signal is delayed by one pulse of the CLK signal by 826, and is output from the Q output of each flip-flop at the timing shown in FIG. Further, 827 to 831 are also flip-flop circuits, which hold input data at the rising edge of the CLK4 signal, and output AVE, L1, L at the timing shown in FIG.
2, M and H signals are output.

Further, in FIG.
A UT ROM that quantizes signals output from L1, L2, M, and H of the grouping circuit 709 by a known vector quantization technique. Each of the L1 groups has 9 bits. 9 L2 groups
Bit, the group of M is quantized to 8 bits, and the group of H is quantized to 8 bits.
Synchronization is achieved at the rise of the K4 signal, and the signal is output as an L-code signal at the timing shown in FIG.

Reference numeral 715 denotes an LGAIN calculator.
Each of the input terminals A, B, C and D is composed of 4 pixels × 4 lines at the same timing as the input to the input terminals X ₁ , X ₂ , X ₃ and X ₄ of the Hadamard conversion circuit 704. An L ^* signal is input in block units, and an LGAIN signal representing the amplitude (maximum value−minimum value) of the brightness signal (L ^* ) for each block, and position information (coordinates in the block) at which L ^* takes the maximum value
The position information (the coordinates in the block) LMN at which LMX and L ^* take the minimum value is calculated.

FIG. 11 is a block diagram showing a detailed configuration of the LGAIN calculator 715. In FIG.
To 904 are flip-flops for input data CL
It is held at the rise of the K signal. Reference numeral 905 denotes a search circuit for a maximum value and a minimum value in the sub-scanning direction. FIG.

In FIG. 12, 1001 to 1002 are 2
→ 1 is a selector, 1003 is a comparator, and 1004 is an inverter. Selectors 1001 to 1002 and comparator 10
03, the data input to each of the A input terminal and the B input terminal, if A (input value to the A input terminal)> B (B
Input value to the input terminal), the comparator 1003
The output of the output terminal (Y) becomes “1” and the selector 10
01 from the output terminal (Y) of the A
A signal is output from the output terminal (Y) of the selector 1002 to the B signal input to the B input terminal. On the other hand, A ≦ B
, The output of the output terminal (Y) of the comparator 1003 becomes “0”, and the output terminal (Y) of the selector 1001
The B signal input to the B input terminal from the
02 output terminal (Y) from the A input terminal
A signal is output. As a result, the value of max (A, B) is output from the output terminal (Y) of the comparator 1001, and the value of min (A, B) is output from the output terminal (Y) of the comparator 1002.
The value of B) is output.

Similarly, reference numerals 1005 to 1006 denote 2 → 1 selectors, 1007 denotes a comparator, and 1008 denotes an inverter. Here, the selectors 1005 to 1006 and the comparator 10
07, the data input to each of the A input terminal and the B input terminal, if C (input value to the A input terminal)> D (B
Input value to the input terminal), the comparator 1007
The output of the output terminal (Y) becomes “1” and the selector 10
05 input terminal A from the output terminal (Y)
The signal is output from the output terminal (Y) of the selector 1006 to the D signal input to the B input terminal. On the other hand, C ≦ D
, The output of the output terminal (Y) of the comparator 1007 becomes “0”, and the output terminal (Y) of the selector 1005
The D signal input to the B input terminal from the
06 from the output terminal (Y) to the A input terminal
A signal is output. As a result, the value of max (C, D) is output from the output terminal (Y) of the comparator 1005, and min (C, D) is output from the output terminal (Y) of the comparator 1004.
The value of D) is output.

Further, 1009 and 1011 are 2 → 1 selectors, 1010 is a comparator, and 1012 to 1014 are inverters. If max (A, B)> max (C, D)
, The output of the comparator 1010 becomes “1”, and the value of max (A, B) is output from the output terminal (Y) of the selector 1009. If max (A, B) ≦ max
If it is x (C, D), the output of the comparator 1010 is “0” and the value of max (C, D) is
9 output terminal (Y). As a result, max
The value of (A, B, C, D) is output from the output terminal (Y) of the selector 1009 as a signal (max). Also, signals imx (0) and signal imx (1) include A, B,
A code indicating which of C and D has the maximum value is output as follows. That is, when A takes the maximum value, imx
(1) = 0 and imx (0) = 0, when B takes the maximum value, imx (1) = 0 and imx (0) = 1, when C takes the maximum value, imx (1) = 1 and imx (0) = 0,
When D takes the maximum value, imx (1) = 0 and imx
(0) = 1.

Similarly, 1015 and 1017 are 2 → 1 selectors and 1016 are comparators, and if min (A,
B)> min (C, D), the comparator 101
6 is "1", and the value of min (C, D) is output from the output terminal (Y) of the selector 1015.
When in (A, B) ≦ min (C, D), the output of the comparator 1016 is “0”, and min (A, B)
Is output from the output terminal (Y) of the selector 1015. As a result, the value of min (A, B, C, D) is output from the output terminal (Y) of the selector 1015 as a signal (min). Also, the signal imn (0) and the signal imn
In (1), a code indicating which of A, B, C, and D has the minimum value is output as follows. That is, when A takes the minimum value, imn (1) = 0 and imn (0) =
When 0 and B take minimum values, imn (1) = 0 and imn
When (0) = 1, C takes the minimum value, imn (1) = 1 and imn (0) = 0, and when D takes the minimum value, imn
(1) = 1 and imn (0) = 1.

Referring again to FIG.
Are flip-flop circuits, and max and min, which are output signals of the maximum / minimum value search circuit 905 in the sub-scanning direction.
Each of min, imx, and imn is given a delay of one pulse of the CLK signal. Reference numeral 914 denotes a circuit for searching for the maximum value in the main scanning direction.
3 is shown.

In FIG. 13, 1101 is a 2 → 1 selector, 1102 is a comparator, and 1103 is an inverter.
The selector 1101 and the comparator 1102 each have two input signal terminals A and B, and the A terminal receives the A signal and the B terminal receives the B signal. Here, if A (the value of the A signal)> B (the value of the B signal), the comparator 1102
Is "1", and an A signal is output to the output terminal (Y) of the selector 1101. On the other hand, if A ≦ B, the output of the comparator 1102 becomes “0”, and the B signal is output to the output terminal (Y) of the selector 1101. As a result, the value of max (A, B) is output to the output terminal (Y) of the selector 1101.

In the selector 1104, if two input signals iA and iB to the selector are set to A
If (value of iA signal)> B (value of iB signal), then
An iA signal is output from the output terminal (Y) of the selector 1104, and if A ≦ B, the selector 1104
Output terminal (Y) outputs an iB signal.

Similarly, 1105 is a 2 → 1 selector, 11
06 is a comparator and 1107 is an inverter. Each of the selector 1105 and the comparator 1106 has two input signal terminals A and B. A signal is input to the A terminal, and D signal is input to the B terminal. Here, if C (value of C signal)> D
If it is (the value of the D signal), the output of the comparator 1106 becomes “1”, and the C signal is output to the output terminal (Y) of the selector 1105. On the other hand, if C ≦ D, the output of the comparator 1106 is “0” and the selector 1106
The output terminal (Y) 105 outputs a D signal. As a result, the output terminal (Y) of the selector 1105 has max
The value of (C, D) is output.

In the selector 1108, if two input signals iC and iD to the selector are set to A,
If (value of iC signal)> B (value of iD signal),
An iC signal is output from the output terminal (Y) of the selector 1108, and if A ≦ B, the selector 1108
Output terminal (Y) outputs an iD signal.

Further, 1109, 1111 and 11
13 is a 2 → 1 selector, 1110 is a comparator, and 1112 is an inverter. Selector 1109 and comparator 111
0 With respect to the input signal to each of the two input terminals A and B,
If max (A, B)> max (C, D), the output of the comparator 1110 is “1”, and the output terminal (Y) of the selector 1109 is connected to max (A, B). Is output. On the other hand, if max (A, B) ≦ max
In the case of (C, D), the output of the comparator 1110 becomes “0”, and max (C, D) is output to the output terminal (Y) of the selector 1109. As a result, the output terminal (Y) of the selector 1109 has max (A, B,
C, D) are output.

The output signals imx (0) and imx are determined by which input takes the maximum value among the input signals A, B, C and D.
The values of x (1) and imx (3 to 2) are determined as follows. That is, when A takes the maximum value, imx (3 to 2) = iA, im
x (1) = 0, imx (0) = 0 When B takes the maximum value, imx (3 to 2) = iB, im
x (1) = 0, imx (0) = 1 When C takes the maximum value, imx (3-2) = iC, im
x (1) = 1, imx (0) = 0 When D takes the maximum value, imx (3-2) = id, im
x (1) = 1 and imx (0) = 1.

Thus, imx is a signal indicating the position (coordinate) where the L ^* signal takes the maximum value in one block composed of 4 pixels × 4 lines.

On the other hand, in FIG. 11, reference numeral 915 denotes a circuit for searching for the minimum value in the main scanning direction, the details of which are shown in FIG.

In FIG. 14, reference numeral 1201 denotes a 2 → 1 selector, and 1202 denotes a comparator. Each of the selector 1201 and the comparator 1202 has two input signal terminals A and B. The A terminal receives the A signal and the B terminal receives the B signal. Here, if A (value of the A signal)> B (value of the B signal), the output of the comparator 1202 becomes “1”, and the B signal is output to the output terminal (Y) of the selector 1201. Is done. On the other hand, if A ≦ B, the comparator 1
The output of 202 becomes “0”, and the A signal is output to the Y output of the selector 1201. As a result, the selector 120
The value of min (A, B) is output to the output terminal (Y) of No. 1.

Further, regarding input signals iA and iB input to two input terminals A and B of selector 1203,
If A (the value of the iA signal)> B (the value of the iB signal), iB is output from the output terminal (Y) of the selector 1203.
A signal is output. If A ≦ B, an iA signal is output from the output terminal (Y).

Similarly, 1204 is a 2 → 1 selector,
1205 is a comparator. Selector 1204 and comparator 1
205 has two input signal terminals A and B, respectively.
The C signal is input to the terminal, and the D signal is input to the B terminal. Here, if C> D, the output of the comparator 1205 becomes “1” and the output terminal (Y) of the selector 1204
Outputs a D signal. On the other hand, if C ≦ D, the output of the comparator 1205 becomes “0”, and the C signal is output to the output terminal (Y) of the selector 1204. As a result, mi is output to the output terminal (Y) of the selector 1204.
The value of n (C, D) is output.

Further, regarding the input signals iC and iD input to the two input terminals A and B of the selector 1206,
If A (value of iC signal)> B (value of iD signal), iD is output from the output terminal (Y) of selector 1206.
A signal is output. If A ≦ B, an iC signal is output from the output terminal (Y).

Further, 1207, 1209 and 1210 are 2 → 1 selectors, and 1208 is a comparator. Selector 1
207 and two input terminals A of each of the comparators 1208,
For the input signal to B, if min (A, B)> mi
If n (C, D), the output of the comparator 1208 is “1”, and min (C, D) is output to the output terminal (Y) of the selector 1207. On the other hand, if
When (A, B) ≦ min (C, D), the output of the comparator 1208 is “0”, and min (A, B) is output to the output terminal (Y) of the selector 1207. As a result, the output terminal (Y) of the selector 1207
The value of (A, B, C, D) is output.

The output signals imn (0) and imn are determined based on which of the input signals A, B, C and D takes the minimum value.
The values of n (1) and imn (3 to 2) are determined as follows. That is, when A takes the minimum value, imn (3 to 2) = iA, im
n (1) = 0, imn (0) = 0 When B takes the minimum value, imn (3-2) = iB, im
When n (1) = 0 and imn (0) = 1 C takes the minimum value, imn (3 to 2) = iC, im
n (1) = 1, imn (0) = 0 When D takes the minimum value, imn (3 to 2) = iD, im
n (1) = 1 and imn (0) = 1.

As described above, imn is a signal indicating the position (coordinate) where the L ^* signal takes the minimum value in one block composed of 4 pixels × 4 lines.

Referring again to FIG. 11, reference numeral 916 denotes a subtractor, and L ^{* in} one block composed of 4 pixels × 4 lines ^.
A value obtained by subtracting the minimum value (min) from the maximum value (max) of the signal is output. 917 to 919 are 2 → 1 selectors, 92
0 to 922 are flip-flop circuits. Also, XD
One signal is an XPHS signal and a CLK signal as shown in FIG.
In synchronization with the signal, the signal is "0" only when the value of the XPHS signal is "1", and is "1" otherwise. Furthermore, the maximum value of the L ^* signal in one block - LGAIN signal is a minimum value, LMX signal indicating the position (coordinates) in one block in the case of L ^* signal takes the maximum value, L ^* signal takes the minimum value The LMN signal indicating the position (coordinate) in one block in the case is output at the timing shown in FIG.

In FIG. 4, reference numeral 716 denotes a comparator.
6 from the LGAIN calculator 715 to the input terminal A of LG.
An AIN signal and a signal (a certain constant value) from a CPU (not shown) are input to its input terminal B. Comparator 7
For 16 input signals, A (value of LGAIN signal)> B
If (signal value from CPU), the output (L _FLG ) from the comparator 716 will be “1”, and if A <B, it will be “0”.

This L _FLG signal is input as a determination signal of a quantization circuit inside a chromaticity information encoder 114 described later.

[Chromaticity component encoder 114 (FIGS. 15 to 1)
9)] FIG. 15 is a block diagram showing the structure of the chromaticity component encoder 114 for chromaticity information. FIG. 16 is a time chart showing the operation timing of the chromaticity component encoder 114.

In FIG. 15, 7201 to 7203 are 1
This is a line memory that gives a line delay, and is for processing the a ^* signal in the chromaticity information in units of blocks composed of 4 pixels × 4 lines. 7204 is a ^*
This is a signal quantization circuit. Reference numerals 7205 to 7207 denote line memories that provide a one-line delay, and process b ^* signals in chromaticity information in block units. Reference numeral 7208 denotes a b ^* signal quantization circuit similar to 7204.

FIGS. 17 to 19 show the a ^* signal quantization circuit 72.
FIG. 41 is a block diagram showing a detailed configuration of a 04 and b ^* signal quantization circuit 7208.

In FIGS. 17 and 18, 1501 through 15
Numeral 24 denotes a flip-flop circuit which gives a delay synchronized with the rise of the CLK signal and synchronizes with the brightness information encoder 113. 1525-
Reference numeral 1526 denotes a 4 → 1 selector, which receives 2 from the s input terminal.
When the bit input signal is “0”, the value input from the output terminal (Y) to the input terminal (A) is output. When the 2-bit input signal is “1”, the value input from the output terminal (Y) to the input terminal. (B) outputs the value input thereto, outputs the value input from the output terminal (Y) to the input terminal (C) when the 2-bit input signal is "2", and outputs the 2-bit input signal. When the signal is "3", a value input from the output terminal (Y) to the input terminal (D) is output. The upper 2 bits of the LMX signal are input to the 2-bit input signal input from the s input terminal of the selector 1525, and LM is input to the s input terminal of the selector 1526.
The upper two bits of the N signal are input.

On the other hand, 1531 to 1542 are flip-flops.
Circuit, each of which is the same as the rising edge of the CLK signal.
Give the expected delay. 1543 to 1544 is 1525
4 → 1 selector similar to １５1526, and selector 1
The s input terminal of 543 is below the synchronized LMX signal.
2 bits are input, and the s input of the selector 1544 is similarly input.
The lower two bits of the synchronized LMN signal are
Is entered. Thus, L within one block^* signal
At the position (coordinates) where^* Signal (a ^* Signal volume
From the child circuit 7204) or b^* Signal (b^* Signal quantization
Circuit 7208) is output as MX and
L in the bag^* A at the position (coordinate) where the signal takes the minimum value^* 
Signal or b^* The value of the signal is output as MN.

On the other hand, reference numeral 1551 denotes an average calculator.
Average of input signals input from input terminals A, B, C, D
Output the value. 1552 to 1555 are flip-flops
Circuits, each of which is synchronized with the rising edge of the CLK signal.
Give a delay. 1556 is the same average value as 1551
It is a calculator, input from its input terminals A, B, C, D.
And output the average value of the input signals. As a result, one block
A in the field^* Signal (a ^* (From signal quantization circuit 7204)
Or b^* Signal (b^* (From the signal quantization circuit 7208)
The average value is output as ME.

Further, reference numerals 1557 to 1560 denote flip-flop circuits, each of which gives a delay in synchronization with the rise of the CLK signal and converts the LGAIN signal to MX, MN, MXN.
The signal is synchronized with each signal of the ME and output as an LG signal.

In FIG. 19, MX, MN, ME, LG
Are input to the flip-flops 1601 to 1604 at C
Synchronization is achieved at the rise of the LK signal. A subtractor 1605 subtracts the value of MN from the value of MX to obtain 1
Within a block, L ^* signal (from a ^* signal quantization circuit 7204) a ^* signal at the position where the position and L ^* signal which takes the maximum value takes a minimum value or b ^* signal (b ^* signal quantization circuit 72
08) is calculated.

Further, 1606, 1610 to 1611 are
This is the lip flop and the difference calculated by the subtractor 1605
The minute value is passed through the flip-flop 1606 to the RO for the LUT.
M1607 address (A_Fifteen~ A₈ ). one
On the other hand, the LG signal is supplied to flip-flops 1604 and 1611.
To the address of the LUT ROM 1607 (A₇ ~ A
₀ ) And the address of the LUT ROM 1607
(A₁₆) Contains L_FLG A signal is input. RO for LUT
M1607 contains a within one block.^* Signal (a ^* signal
From the quantization circuit 7204) or b^* Signal (b^* Signal quantum
L) of the amplitude of the AC component of^* Signal
Value of ratio (MX-MN) / LG to amplitude of AC component
And L_FLG When the signal is "1", it is quantized to 4 bits
If it is "0", it is quantized to 2 bits
Are written in advance and output as data.

Similarly, the LUT ROM 1618 stores 1
A ^* signal (from a ^* signal quantization circuit 7204) or b ^* signal (from b ^* signal quantization circuit 7208) in the block
The value of the average value ME is 6 when the L _FLG signal is “1”.
The data quantized into bits, and when it is "0", the data which is still 8 bits is written in advance and output as data. The data in the LUT ROMs 1607 and 1618 follows the frequency distribution of empirically obtained image data.
The output data from the LUT ROM 1618 when the L _FLG signal is "1" is composed of a large number of codes in a smaller value of the a ^* and b ^* signals so that the reproducibility of the highlight portion of the image data is improved. It is non-linearly quantized to allocate.

1608 and 1612 are 2 → 1 selectors, 1
Reference numerals 609 and 1613 to 1617 denote flip-flop circuits, which output the gain signal and the mean signal at the timing shown in FIG.

[Operation Timing of Apparatus (FIG. 20)] FIG.
0 is a time chart showing the operation timing of the image processing apparatus of the present embodiment. In FIG. 20, a START signal is a signal indicating the start of a document reading operation of the image processing apparatus according to the present embodiment, and a WPE signal is a signal indicating a time during which the image scanner reads a document to perform encoding processing and memory writing. The ITOP signal is a signal indicating the start of a printing operation, the MPE signal is a section signal for driving the magenta semiconductor laser 216 shown in FIG. 1, and the CPE signal is for driving the cyan semiconductor laser 215 shown in FIG. The YPE signal is an interval signal for driving the yellow semiconductor laser 214 shown in FIG. 1, and the BPE signal is an interval signal for driving the black semiconductor laser 213 shown in FIG.

As shown in FIG. 20, the CPE signal, the YPE
Signal for each BPE signal MPE signals are delayed by a time interval _{t 1, t 2, t 3} . These values are respectively the distance (d ₁ ) between the photosensitive drums 228 and 227 and the distance (d ₁ ) between the photosensitive drums 228 and 226 shown in FIG.
₂ ), with respect to the distance (d ₃ ) between the photosensitive drums 228 and 225, t ₁ = d ₁ / v, t ₂ = d ₂ / v, and t ₃ = d ₃ / v.
(V is the paper feed speed).

The HSYNC signal is a main scanning synchronization signal, CLK
The signal is a pixel synchronization signal. The YPHS signal is a count value of the 2-bit sub-scanning counter, and the XPHS signal is 2 bits.
This is the count value of the main scanning counter in bits. These signals are generated by an inverter 1801 and 2-bit counters 1802 and 1803 as shown in FIG. 21 with a START signal as an input of a HYSNC signal.
The BLK signal is a periodic signal in units of one block,
Processing is performed in units of one block at the timing indicated by TA.

[Area Processing (FIGS. 22 to 23)] FIG.
FIG. 4 is a block diagram illustrating a configuration of an area processing circuit 115b that performs an area process on a block basis. In FIG. 22, CLK is a pixel synchronization signal, and HSYNC is a main scanning synchronization signal. Reference numerals 1901-1903 denote line memories for giving one-line delay, and output signals X from the respective line memories
₁ , X ₂ and X ₃ are delayed by one line, two lines and three lines, respectively, in the sub-scanning direction with respect to the input signal X.
Reference numeral 1904 denotes an adder, which counts the number of X _0, X _1, X _{2, and} X ₃ corresponding to four pixels in the sub-scanning direction of the binary signal (X) whose value is “1”.

1910 is a 2 → 1 selector, and 1911 is N
An OR gate 1912 is a flip-flop. XP
NOR gate 191 by HS (0) and XPHS (1)
In synchronization with the BLK signal generated in step 1, the number of pixels C ₁ in which the value of the binary signal (X) counted in the block is “1” is calculated, and the value C ₁ is set in the register 1913 in advance. The comparison value C ₂ is compared in the comparator 1914. Here, when C ₁ > C ₂ , the output (Y) of the comparator 1914 is “1”, and when C ₁ ≦ C ₂ , the output (Y) is “0”, and FIG. Are output at the timing according to the BDATA signal shown in FIG.

Here, the characteristic features are that the image code (L-code signal and ab-code signal) obtained by the encoding and the characteristic signal (K ₁ , K
₂ ) is a one-to-one correspondence in blocks of 4 pixels × 4 lines shown in FIG.

As a result, the image code and the characteristic signal are extracted for each block unit and stored at the same address in the memory or at an address calculated from the same address.
Also in the case of reading, it becomes possible to read correspondingly.

Accordingly, by storing the image information and the characteristic (attribute) information in the same address in the memory or at the address calculated from the same address, for example, a common write and read control circuit for the memory can be used. It is possible to simplify and simplify the editing process such as scaling / rotation on the memory, so that the system can be optimized. .

FIG. 23 is a diagram showing an example of a specific area process for character pixel detection. For example, manuscript 2001
As shown in 2003, the determination result of each pixel as to whether or not it is a character pixel is shown for a part 2002 of the character
For each pixel in the portion of text _{2002, "○" K 1 '} = 1, K 1 in the other pixels' pixel represented by a is determined to = 0. In this case, in the area processing circuit 115b,
For example, by setting C ₂ = 4, a signal K ₁ with reduced noise (noise) as shown in 2004 can be obtained for one block.

Also, the determination result K ₂ ′ of the black pixel detection circuit is processed by the area processing circuit 115d) having the same configuration, whereby a signal K ₂ corresponding to each block can be obtained.

[Lightness Component Decoders 117a to 117d]
(FIG. 24)] FIG. 24 shows a brightness component decoder 117a-1.
It is a block diagram which shows the structure of 17d. The brightness information is decoded by subjecting the decoded data to inverse Hadamard transform using the L-code signal read from the image memory 116 to decode the L ^* signal. The inverse Hadamard transform is (3)
This is the inverse of the Hadamard transform shown in the equation, and is defined by equation (4).

[0086] Here, H is a 4 × 4 Hadamard matrix, and H ^T is H
Is a transposed matrix.

On the other hand, the Hadamard transform and the inverse Hadamard transform are linear operations, and when the Hadamard transform or the inverse Hadamard transform of the matrix X is expressed as H (X), the equation (5) generally holds.

H (X ₁ + X ₂ +... + X ₃ ) = H (X ₁ ) + H
(X ₂ ) +... + H (X _n )... (5) By utilizing this property, the inverse Hadamard transform is decomposed into each frequency band defined by the brightness information encoder and is performed in parallel.

Here, the data matrix decoded by the L1 code is Y _L1 , the data matrix decoded by the L2 code is Y _L2 , the data matrix decoded by the M code is Y _M , H When the data matrix decoded by the code is Y _H , the expression (6) is satisfied.

H (Y _L1 + Y _L2 + Y _M + Y _H ) = H (Y _L1 ) + H (Y _L2 ) + H (Y _M ) + H (Y _H ) (6) Reference numerals 2101 to 2104 denote ROMs for the LUT. , The values of the encoding processing and the inverse Hadamard transform processing are calculated in advance. The lower bits of the addresses of the LUT ROMs 2101 to 2104 are L1 code (9 bits), respectively.
The L2 code (9 bits), the M code (8 bits), and the H code (8 bits) are input, and the LUT ROM 2101 is input.
XPS (2 bits) and YPHS (2 bits) are input to the upper bits (4 bits) of the addresses of .about.2104, respectively. When the above address is input, the value of the inverse Hadamard transform at the position (coordinate) in each block is output. Reference numeral 2105 denotes an adder, which performs addition corresponding to the equation (6), and includes each frequency component (L1, L2, M,
This is a part for adding the result of the inverse Hadamard transform in H). When the result of the addition (the AC component in one block of the L ^* signal) is obtained, the L
Output as the AC component LAC of ^* .

If decoding is performed collectively without using this method, the LUT of the address space (64 gigabytes) of a total of 36 bits including a code of 34 bits and a coordinate position of 4 bits (XPHS, YPHS) is used. It is not realistic to try to achieve this technically. However, by using the method described above, a maximum of 1
It is only necessary to prepare several ROMs having a 3-bit address space (8 kilobytes), which simplifies the configuration. Further, it is easy to cope with a case where the code length is changed.

[0092] 2107 is an adder, by adding the 1-block average value AVE of L ^* AC component LAC and L ^* signal obtaining L ^* signal after decoding. This signal is output by the flip-flop 2108 in synchronization with the rise of the CLK signal.

[Chromaticity component decoders 118a to 118d]
(FIG. 25)] FIG. 25 shows the brightness component decoders 118a-1
It is a block diagram which shows the structure of 18d. Image memory 11
The ab-code signal read from 6 is synchronized at the rising edge of the CLK signal in the flip-flop 2201, and is decomposed into an a-code signal and a b-code signal as shown in FIG. Is further decomposed into an a _gain signal and an a _mean signal, and a b _gain signal and a b _mean signal. Then, the brightness information L ^* is _added to the a _gain signal which is the ratio of the amplitude of the L ^* signal to the amplitude of the a ^* signal in one block by the multiplier 2202 ^.
Is multiplied by the AC component (LAC) of the a ^* signal, and an adder 2204 adds the a _mean signal, which is the DC component of the a ^* signal, to the value.
^* Decode the signal. The decoded a ^* signal is output by the flip-flop 2206 in synchronization with the rising edge of the CLK signal.

Similarly, the multiplier 2203 multiplies the b _gain signal, which is the ratio of the amplitude of the L ^* signal to the amplitude of the b ^* signal in one block, by the AC component (LAC) of the brightness information L ^* , and In 2205, b _mean which is a DC component of the b ^* signal
Add the signals and decode the b ^* signal. Decrypted b
^{The *} signal is output by the flip-flop 2207 in synchronization with the rising edge of the CLK signal.

[Color space converters 119a to 119d (FIG. 2)
6)] FIG. 26 is a block diagram showing a configuration of the color space converters 119a to 119d. In FIG. 26, reference numeral 2301 denotes a conversion circuit for converting the L ^* , a ^* , and b ^* signals into RGB signals, and the conversion is performed by Expression (7).

[0096] However, Also, [α _ij '] _{i, j = 1,2,3} is [α _ij ] in equation (1).
_i, the inverse matrix of _{j = 1,2,3, [β ij '} ] i, j = 1,2,3 is, [beta _{ij] i,} the inverse of _{j = 1, 2, 3} of the formula (2) It is a matrix.

Each of the luminance / density converters 2302 to 2304 performs a conversion according to equation (10).

[0098] The black extraction circuit 2305 performs conversion according to the equation (11),
Generate a black signal (Bk ₁ ).

Bk ₁ = min (M _1, C _1, Y ₁ ) (11) In multipliers 2306 to 2309, C ₁ , M ₁ , Y ₁ , Bk
Predetermined coefficients a ₁ to each signal of _1, a _2, a _3, multiplied by a _4, executes adding operation in the adder 2310. In this way, the sum-product operation shown in Expression (12) is performed.

(Output C, M, YorBk) = a₁ M₁+ a_Two 
C₁+ a_Three Y₁+ a_Four Bk₁(12) Each of the registers 2311 to 2315 has a color space converter 1
In the case of 19a, a ₁₁, A₁₂, A₃₁, A₄₁, 0 is the color
In the case of the space transformer 119b, a₁₂, A_{twenty two}, A₃₂, A
₄₂, 0 is the color space converter 119c, a₁₃, A
_{twenty three}, A₃₃, A₄₃, 0 is the color space converter 119d.
Is a₁₄, A_{twenty four}, A₃₄, A₄₄, A '₁₄ Is set
You.

Reference numerals 2331 to 2333 denote gate circuits, 233
0 is a 2 → 1 selector circuit, and 2320 is a NAND gate circuit. As a result, the logical product of the black pixel determination signal (K ₁ ) and the character area determination signal (K ₂ ) determines whether the pixel is a black character area. As shown in FIG. 27,
The values of ₁ , a ₂ , a ₃ , and a ₄ are selected. If the area is not a black character area, processing according to equation (13) is performed. If the area is a black character area, processing according to equation (14) is performed.

[0102] That is, in the black character area, as shown in Expression (14), black (B
k) By outputting in a single color, an output without color shift can be obtained. On the other hand, in the region other than the black character area, as shown in Expression (13), output is performed in four colors of M, C, Y, and Bk. based _{M 1, C 1, Y 1} , M based an Bk ₁ signal to the spectral distribution characteristic of the toner, C, Y, and outputs the corrected Bk signal.

Therefore, according to this embodiment, the input full-color image signal is divided into block units each composed of 4 pixels × 4 lines, and the brightness information and the chromaticity information are divided into the block image signal units. Separately encode. In particular, chromaticity information can be encoded by changing its encoding length in accordance with the amplitude value of the AC component of the brightness information.

In this embodiment, the difference between the maximum value and the minimum value of L ^* of one block composed of 4 pixels × 4 lines is used as a determination signal for separating an image area. It is not limited. For example, as shown in FIG. 28, the distance in the color space between the maximum value and the minimum value of the chromaticity information can be used.

That is, the inputted a ^* signal is stored in the line memories 2501 to 2503 (the b ^* signal is stored in the line memory 2508).
２５2510), and input to the input terminals A to D of the aGAIN calculator 2504 and the bGAIN calculator 2511, respectively. The obtained aGAIN signal and bG
The AIN signal is divided by multipliers 2505 and 2512 to 2
, And further added by an adder 2506 to obtain rG
It is output as an AIN signal. The threshold value sent from the CPU (not shown) is input to the input terminal (B) of the comparator 2507 and the other input terminal (A) of the rGAIN signal. Here, A (threshold from CPU) <B (rG
AIN signal value), the output of comparator 2507 (L
_FLG ) becomes "1", and when A≥B, "0" is output.

Further, in the present embodiment, the case where the input RGB signal is converted into the YMCBk signal has been described, but the present invention is not limited to this. For example, FIG.
The full-color image signal separated into red (R), green (G), and blue (B) is converted into a YUV signal by the conversion circuit 2601 according to the equation (15) as in the full-color image encoder shown in FIG. You can also.

[0107] Here, c ₁ , c ₂ , c ₃ , c ₄ , and c ₅ are constants.

Here, Y is L^* Represents brightness information in the same way as
U and V are a^* And b^* As well as color
This is a signal representing the degree. 2602 uses discrete cosine transform
DCT circuit that performs n × n (n is a power of 2; n =
4,8,16,32 ...) pixel discrete cosine transform (D
CT). By the DCT transform, the Y signal is
Expanded to each spatial frequency component, and coded by encoder 2606
For example, it is encoded by a Huffman code. Change
, A Y amplitude detector 260 having the same configuration as 715
3, the amplitude of the Y signal in the n × n pixels (Y-GAI
N) is calculated. On the other hand, 2604 is the same as 7204
A circuit having a configuration, wherein a U signal with respect to an amplitude of a Y signal
Amplitude ratio (U_gain) And the DC component of the U signal (U_mean)
Output and use as U-code. Similarly, 2605 is 7
204 is a circuit having a configuration similar to that of FIG.
The amplitude ratio of the V signal to_gain) And the DC signal of the V signal
Minutes (V _mean) And output as V-code. Further
And Y-code, U-code, and V-code
Sign.

Note that the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0110]

As described above, according to the present invention, an input full-color image signal is divided into predetermined units, and each of the predetermined units is separated into brightness information and chromaticity information and encoded. In particular, since the DC component of the chromaticity information is non-linearly encoded, more efficient encoding, that is, encoding with a shorter code length for the same image quality degradation, and encoding with less image quality degradation for the same code length. There is an effect that can be performed.

As a result, the reproduced image obtained by encoding and decoding the input image, for example, the roughness of the halftone dot image area can be eliminated, so that the image reproducibility can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus that is a typical embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an image processing circuit 212.

FIG. 3 is a block diagram illustrating a configuration of an image processing circuit 212.

FIG. 4 is a block diagram illustrating a configuration of a brightness information encoder 113.

FIG. 5 is a diagram illustrating an outline of quantization processing of a blocked image signal executed by a brightness information encoder 113;

6 is a diagram illustrating a specific example of the quantization processing illustrated in FIG. 4;

FIG. 7 is a diagram illustrating a state in which an image signal is divided into blocks in a main scanning direction and a sub-scanning direction.

FIG. 8 is a time chart showing operation timings of the brightness information encoder 113.

FIG. 9 is a block diagram illustrating a configuration of a grouping circuit 709.

FIG. 10 is a block diagram illustrating a configuration of a grouping circuit 709.

FIG. 11 is a block diagram showing a configuration of an LGAIN calculator 715.

FIG. 12 shows a maximum / minimum value search circuit 905 in the sub-scanning direction.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 13 is a block diagram illustrating a configuration of a maximum value search circuit 914 in the main scanning direction.

FIG. 14 is a block diagram showing a configuration of a minimum value search circuit 915 in the main scanning direction.

FIG. 15 is a block diagram illustrating a configuration of a chromaticity component encoder 114.

FIG. 16 is a time chart showing the operation timing of the chromaticity component encoder 114.

FIG. 17 is a block diagram showing a configuration of an a ^* signal quantization circuit 7204 and a b ^* signal quantization circuit 7208.

18 is a block diagram illustrating a configuration of an a ^* signal quantization circuit 7204 and a b ^* signal quantization circuit 7208. FIG.

FIG. 19 is a block diagram showing a configuration of an a ^* signal quantization circuit 7204 and a b ^* signal quantization circuit 7208.

FIG. 20 is a time chart illustrating the operation timing of the entire image processing apparatus.

FIG. 21 is a block diagram showing a configuration of an XPHS signal and YPHS signal generation circuit.

FIG. 22 is a block diagram illustrating a configuration of an area processing circuit 115b that performs an area process on a block basis composed of 4 pixels × 4 lines.

FIG. 23 is a diagram showing a specific example of area processing for character pixel detection.

FIG. 24 is a block diagram illustrating a configuration of lightness component decoders 117a to 117d.

FIG. 25 is a block diagram illustrating a configuration of chromaticity information decoders 118a to 118d.

FIG. 26 is a block diagram illustrating a configuration of color space converters 119a to 119d.

FIG. 27 shows a coefficient (a) for each signal of C ₁ , M ₁ , Y ₁ , and Bk ₁ used for the multiplication operation in multipliers 2306 to 2309.
₁ , a ₂ , a ₃ , a ₄ ).

FIG. 28 is a block diagram showing another embodiment of a determination signal generation circuit for separating an image area.

FIG. 29 is a block diagram showing another embodiment of a full-color image encoder.

[Explanation of symbols]

 101-103 CCD 107-109 A / D converter 110-111 Delay circuit 112 Color space converter 113 Lightness information encoder 114 Chromaticity information encoder 116 Image memory 117a-117d Lightness information decoder 118a-118d Color Degree information decoders 141 to 144 Decoders 151 to 156 Tri-state gates 157 to 160 Magnification circuit 202 Reading document 212 Image processing circuit 225 to 228 Photosensitive drum

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-42968 (JP, A) JP-A-63-185163 (JP, A) JP-A-1-311786 (JP, A) Patent 3162792 (JP, A B2) Patent 326452 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1/41-1/419

Claims (12)

(57) [Claims] 1. An image processing method for processing a color image signal, an input step of inputting a color image signal, and a separation step of separating said full-color image signals into brightness information and the chromaticity information of the pixel block, A first encoding step of separating and quantizing and encoding the brightness information of the full-color image signal into a DC component and an AC component for each pixel block unit; and a maximum value and a minimum value of the brightness information in the pixel block. Difference
A first calculating step of calculating a partial value ; a second calculating step of calculating an average value of chromaticity information in the pixel block; and a color at a position where a maximum value of brightness information in the pixel block is obtained.
Chromaticity information of the position where the minimum value of the brightness information and the brightness information is obtained;
A third calculation step of calculating a difference value, the difference value calculated in the first calculation step 3
Indicating the ratio with the difference value calculated in the calculation step of
Seek min ratio, a second encoding step of encoding, the difference value calculated in the first calculation step exceeds a predetermined value
Is larger than the average calculated in the second calculation step.
A non-linear quantized version of the average is output and the first calculation
When the difference value calculated in the process is smaller than the predetermined value
Quantizing the average value calculated in the second calculation step;
And a third encoding step of outputting the image data without any processing. 2. The non-linear quantization of the average value of chromaticity information is represented by allocating a large amount of code code to an image signal with low chromaticity, and expressing it by assigning a large amount of code code to an image signal with low chromaticity. 2. The image processing method according to claim 1, wherein the image is represented by a small number of codes. 3. An image processing apparatus for processing a color image signal input means for inputting a color image signal, separating means for separating the color image signal into luminance information and chromaticity information of the pixel block, First encoding means for separating and quantizing and encoding the brightness information of the full-color image signal into a DC component and an AC component for each pixel block unit; a maximum value and a minimum value of the brightness information in the pixel block ; Difference
First calculating means for calculating a fractional value ; second calculating means for calculating an average value of chromaticity information in the pixel block; and a color at a position at which a maximum value of brightness information in the pixel block is obtained.
Chromaticity information of the position where the minimum value of the brightness information and the brightness information is obtained;
A third calculating means for calculating a difference value between the first and second calculating means;
Indicating the ratio to the difference value calculated by the calculation means
Seek min ratio, a second coding means for coding the difference value calculated by said first calculating means exceeds a predetermined value
Is larger than the average calculated by the second calculating means.
A non-linear quantized version of the average is output and the first calculation
When the difference value calculated by the means is smaller than the predetermined value
Quantizing the average value calculated by the second calculating means
An image processing apparatus comprising: a third encoding unit configured to output the image data without using the third encoding unit. 4. The non-linear quantization of the average value of the chromaticity information is represented by assigning a large amount of code code to an image signal having a low chromaticity and expressing it by assigning a large amount of code code to an image signal having a low chromaticity. 4. The image processing apparatus according to claim 3, wherein the image is represented by a small number of codes. 5. The first encoding unit performs an orthogonal transform on the brightness information for each pixel block unit ,
The image processing apparatus according to claim 3, wherein the direct current component and the alternating current component are separated . 6. The image processing apparatus according to claim 5 , wherein the orthogonal transform is a Hadamard transform. 7. The image processing apparatus according to claim 5 , wherein the orthogonal transform is a discrete Fourier transform or a discrete cosine transform. 8. The image processing apparatus according to claim 3, wherein the encoded code length is a fixed length code. 9. The image processing apparatus according to claim 3, wherein said input means has an image reading means for optically reading a full-color image and converting it into an electric signal. 10. The image processing apparatus according to claim 3, further comprising storage means for storing information of the encoded full-color image. 11. The image processing apparatus according to claim 3, further comprising image forming means for decoding the information of the encoded full-color image, and visualizing and outputting the decoded full-color image on a recording medium. Image processing device. 12. The image forming apparatus according to claim 11, wherein the image forming unit includes a plurality of image forming units corresponding to color components and a conveying unit that sequentially conveys a recording medium to the plurality of image forming units. An image processing apparatus as described in the above.