JPH0738496B2 - Substrate layout method for integrated circuit device - Google Patents
Substrate layout method for integrated circuit deviceInfo
- Publication number
- JPH0738496B2 JPH0738496B2 JP63136180A JP13618088A JPH0738496B2 JP H0738496 B2 JPH0738496 B2 JP H0738496B2 JP 63136180 A JP63136180 A JP 63136180A JP 13618088 A JP13618088 A JP 13618088A JP H0738496 B2 JPH0738496 B2 JP H0738496B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit element
- terminals
- circuit elements
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、パッケージに封止された集積回路素子を印
刷配線板上に実装する集積回路素子の基板レイアウト方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for laying out an integrated circuit element encapsulated in a package on a printed wiring board.
第２図は従来のこの種の実装方法を示す平面図であり、
図において、１は印刷配線板、２は前記印刷配線板１上
に実装配置される第１の集積回路素子、３は同じく第２
の集積回路素子であり、これら第1,第２の集積回路素子
2,3には多数の端子が突設されている。４は前記第１の
集積回路素子２の端子のうちのクロック端子、５は前記
第２の集積回路素子３の端子のうちのクロック端子、６
は前記クロック端子４と５とを結ぶ配線パターン、７は
前記第１の集積回路素子２と第２の集積回路素子３との
間隔を示す。FIG. 2 is a plan view showing a conventional mounting method of this type,
In the figure, 1 is a printed wiring board, 2 is a first integrated circuit element mounted and arranged on the printed wiring board 1, and 3 is a second integrated circuit element.
Integrated circuit elements, and these first and second integrated circuit elements
A large number of terminals are projected on 2 and 3. 4 is a clock terminal among the terminals of the first integrated circuit element 2, 5 is a clock terminal among the terminals of the second integrated circuit element 3, and 6
Is a wiring pattern connecting the clock terminals 4 and 5, and 7 is a distance between the first integrated circuit element 2 and the second integrated circuit element 3.
次に従来の実装方法について説明する。Next, a conventional mounting method will be described.
印刷配線板１に実装された第１の集積回路素子２および
第２の集積回路素子３は共に４方向に多数の端子が突出
しているため、相対する辺に並ぶクロック端子４および
５と外部回路（図示せず）との接続パターン用の間隔７
が広くとられている。したがって、第２図においては、
第１の集積回路素子２のクロック端子４と第２の集積回
路素子３のクロック端子５は、配線パターン６により接
続されている。Since the first integrated circuit element 2 and the second integrated circuit element 3 mounted on the printed wiring board 1 each have a large number of terminals protruding in four directions, the clock terminals 4 and 5 arranged on opposite sides and the external circuit are arranged. Interval 7 for connection pattern with (not shown)
Is widely adopted. Therefore, in FIG.
The clock terminal 4 of the first integrated circuit element 2 and the clock terminal 5 of the second integrated circuit element 3 are connected by a wiring pattern 6.
上記のような従来の実装方法では、配線パターン６の長
さは、間隔７より長くなるため、クロック端子4,5の周
波数が高い場合には、不要輻射が発生し易くなる。ま
た、外来ノイズによる影響も受け易いなどの問題点があ
った。In the conventional mounting method as described above, since the length of the wiring pattern 6 is longer than the interval 7, unnecessary radiation is likely to occur when the frequency of the clock terminals 4 and 5 is high. There is also a problem that it is easily affected by external noise.
この発明は、上記のような問題点を解決するためになさ
れたもので、不要輻射が少なく、耐ノイズ性に優れた集
積回路素子の基板レイアウト方法を得ることを目的とす
る。The present invention has been made to solve the above problems, and an object thereof is to obtain a substrate layout method for an integrated circuit element which has less unnecessary radiation and excellent noise resistance.
この発明に係る集積回路素子の基板レイアウト方法は、
集積回路素子を、印刷配線板偶数象限どうし上または奇
数象限どうし上に相対して配置するとともに、各集積回
路素子の中心線よりも他の素子に近い側にクロック端子
が位置するように各集積回路素子を配置し、かつクロッ
ク端子どうしを配線パターンで接続するものである。A substrate layout method for an integrated circuit device according to the present invention is
The integrated circuit elements are arranged so as to face each other on the even-numbered quadrants or on the odd-numbered quadrants, and each integrated circuit is placed such that the clock terminals are located closer to other elements than the center line of each integrated circuit element. The circuit elements are arranged and the clock terminals are connected by a wiring pattern.
この発明における実装方法では、クロック端子どうしが
短い配線パターンで接続され、不要輻射の発生を抑え
る。In the mounting method according to the present invention, the clock terminals are connected to each other by a short wiring pattern to suppress generation of unnecessary radiation.
以下、この発明の一実施例を第１図について説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図において、１は印刷配線板、２はこの印刷配線板
１の第３象限に実装された第１の集積回路素子、３は同
じく印刷配線板１の第１象限に実装された第２の集積回
路素子、４は前記第１の集積回路素子２のクロック端
子、５は前記第２の集積回路３のクロック端子、６は前
記クロック端子４および５を接続する配線パターン、８
は前記第１の集積回路素子２と第２の集積回路３のｘ方
向の相対する辺の延長線間の間隔、９は同じくｙ軸方向
の相対する辺の延長線間の間隔を示し、10は前記各集積
回路素子2,3の中心線を示す。In FIG. 1, 1 is a printed wiring board, 2 is a first integrated circuit element mounted in the third quadrant of the printed wiring board 1, and 3 is a second integrated circuit element similarly mounted in the first quadrant of the printed wiring board 1. Integrated circuit element, 4 is a clock terminal of the first integrated circuit element 2, 5 is a clock terminal of the second integrated circuit 3, 6 is a wiring pattern for connecting the clock terminals 4 and 5, 8
Is the distance between the extension lines of the opposite sides of the first integrated circuit element 2 and the second integrated circuit 3 in the x direction, and 9 is the distance between the extension lines of the opposite sides in the y axis direction, and 10 Indicates the center line of each of the integrated circuit elements 2 and 3.
次に、この発明の一実施例の実装方法について説明す
る。Next, a mounting method according to an embodiment of the present invention will be described.
第１の集積回路素子２および集積回路素子３は、図のよ
うに間隔８および間隔９（共にその幅の最小値は0mm）
を持つ座標軸の第３および第１象限（また第２および第
４象限）に相対して配置される。The first integrated circuit element 2 and the integrated circuit element 3 have a space 8 and a space 9 (both have a minimum width of 0 mm) as shown in the figure.
Are located relative to the third and first quadrants (and also the second and fourth quadrants) of the coordinate axis having.
また、クロック端子４およびクロック端子５は、それぞ
れ他の端子に近い方の辺上で、しかも各集積回路素子2,
3の中心線10に対するよりも、他の素子に近い方に含ま
れるように配置される。このクロック端子４およびクロ
ック端子５は、配線パターン６で接続される。この場
合、４′,5′をクロック端子として、接続してもよい。In addition, the clock terminal 4 and the clock terminal 5 are on the sides closer to the other terminals, and the integrated circuit elements 2,
It is arranged to be included closer to other elements than to the center line 10 of 3. The clock terminal 4 and the clock terminal 5 are connected by a wiring pattern 6. In this case, 4'and 5'may be used as clock terminals for connection.
なお、上記実施例では、一般にQFP（Quad Flat Packag
e）およびPLCC（Plastic Leaded C−hip Carrier）と呼
ばれる表面実装用パッケージの例を示したが、PGA（Pin
Grid Arry）と呼ばれる多ピンパッケージでも同様の効
果を奏する。It should be noted that in the above embodiment, generally, QFP (Quad Flat Packag
e) and PLCC (Plastic Leaded Chip Carrier) examples of surface mount packages are shown.
The same effect can be achieved with a multi-pin package called Grid Arry).
以上説明したように、この発明は、集積回路素子を印刷
配線板の偶数象限どうし上または奇数象限どうし上に相
対して配置するとともに、前記各集積回路素子の中心線
よりも他の素子に近い側にクロック端子が位置するよう
に前記各集積回路素子を配置し、かつクロック端子どう
しを配線パターンで接続するので、クロック端子間を接
続する配線パターンの距離が短くなり、したがって、不
要輻射の少ない、かつ外来ノイズにほとんど影響されな
い集積回路素子の実装が可能となる。また、実装面積も
少なくて済む等の利点が得られる。As described above, according to the present invention, the integrated circuit elements are arranged so as to face each other on even quadrants or odd quadrants of the printed wiring board, and are closer to other elements than the center line of each integrated circuit element. Since each integrated circuit element is arranged so that the clock terminal is located on the side and the clock terminals are connected by the wiring pattern, the distance of the wiring pattern connecting the clock terminals is shortened, and therefore, unnecessary radiation is reduced. In addition, it is possible to mount an integrated circuit element that is hardly affected by external noise. Further, there are advantages such as a small mounting area.
第１図はこの発明の一実施例による実装方法を示す配置
図、第２図は従来の実装方法を示す配置図である。 図において、１は印刷配線板、２は第１の集積回路素
子、３は第２の集積回路素子、4,5はクロック端子、６
は配線パターン、8,9は間隔、10は中心線である。 なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a layout showing a mounting method according to an embodiment of the present invention, and FIG. 2 is a layout showing a conventional mounting method. In the figure, 1 is a printed wiring board, 2 is a first integrated circuit element, 3 is a second integrated circuit element, 4,5 are clock terminals, and 6
Is a wiring pattern, 8 and 9 are intervals, and 10 is a center line. The same reference numerals in each drawing indicate the same or corresponding parts.
Claims (1)
ケージに封止された集積回路素子を、印刷配線板に複数
個実装する方法において、前記集積回路素子を印刷配線
板の偶数象限どうし上または奇数象限どうし上に相対し
て配置するとともに、前記各集積回路素子の中心線より
も他の素子に近い側にクロック端子が位置するように前
記各集積回路素子を配置し、かつ前記クロック端子どう
しを配線パターンで接続することを特徴とする集積回路
素子の基板レイアウト方法。1. A method of mounting a plurality of integrated circuit elements, each of which has terminals protruding in four directions and sealed in a surface mounting package, on a printed wiring board, wherein the integrated circuit elements are even quadrants of the printed wiring board. The integrated circuit elements are arranged relative to each other or on the odd quadrants, and the integrated circuit elements are arranged so that the clock terminals are located closer to other elements than the center line of the integrated circuit elements, and A method for laying out a substrate for an integrated circuit device, which comprises connecting clock terminals with a wiring pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63136180A JPH0738496B2 (en) | 1988-06-01 | 1988-06-01 | Substrate layout method for integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63136180A JPH0738496B2 (en) | 1988-06-01 | 1988-06-01 | Substrate layout method for integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01304794A JPH01304794A (en) | 1989-12-08 |
| JPH0738496B2 true JPH0738496B2 (en) | 1995-04-26 |
Family
ID=15169207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63136180A Expired - Fee Related JPH0738496B2 (en) | 1988-06-01 | 1988-06-01 | Substrate layout method for integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0738496B2 (en) |
-
1988
- 1988-06-01 JP JP63136180A patent/JPH0738496B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01304794A (en) | 1989-12-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |