JPH0738381A - Digital filter and quadrature modulation device using the same - Google Patents

Abstract

PURPOSE:To provide a digital filter with high performance disregarding that a circuit scale can be remarkably reduced and a quadrature modulation device using the same. CONSTITUTION:A selector 10 performs the time division multiplex of two kinds of base band signals of digital format. A delay circuit 11 comprises a shift register of seven stages as a whole. The same kinds of base band signals appear on the output of the delay circuits 11a, 11c, 11e. and 11g. A coefficient generation circuit 12 generates a delayed base band signal and filter coefficients (h1-h4) of digital format multiplied at a multiplication circuit 13, respectively. An adder circuit 14 computes the sum total of multiplication results (m1-m4) of digital format outputted from the multiplication circuit 13 as a whole, and outputs it as a filtering result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a finite impulse response type digital filter, and a quadrature modulator for amplitude-modulating two or more baseband signals with mutually orthogonal carrier signals using the digital filter.

[0002]

2. Description of the Related Art Generally, a quadrature modulator using digital processing band-limits two different types of baseband signals with digital low-pass filters, and amplitude-modulates mutually orthogonal carrier signals with the band-limited baseband signals. Then, these are combined. FIG. 22 is a diagram illustrating a configuration of the conventional orthogonal transform device 8. The orthogonal transform device 8 is composed of digital low-pass filters (LPF) 81 and 82, multiplication circuits 84 and 85, an addition circuit 86, and a sine wave oscillator (OSC) 83 that generates two orthogonal carrier wave signals.

The operation of the orthogonal transform device 8 will be described below.
The digital low-pass filters 81 and 82 respectively filter one of the two different types of base band signals in digital format by digital processing, and input only predetermined frequency components to the multiplication circuits 84 and 85. The multiplying circuits 84 and 85 multiply the baseband signals of the digital format whose band is limited respectively, and the carrier signals of the digital format which are input from the sine wave oscillator 83 and are orthogonal to each other by digital processing, and add the circuits. 8
Enter in 6. The adder circuit 86 adds the digital multiplication results input from the multiplier circuits 84 and 85 by digital processing, and outputs the result as a modulation output. The digital modulation result is further digital-to-analog converted, subjected to processing such as band limitation, and sent out on the transmission path.

The two digital low-pass filters 81 and 82 used in the orthogonal transform device 8 usually have the same characteristics, and generally have the structure shown in FIG. FIG. 23 shows
Digital low-pass filters 81 and 82 shown in FIG.
It is a figure which illustrates the structure of. In FIG. 23, delay circuits (D _{1 to} D ₄ ) 91a to 91d delay an input signal in digital form for each reference time (clock signal period) and propagate it. Coefficient generation circuits 92a to 92d
Respectively generate filter coefficients in digital form. The multiplication circuits 93a to 93d are delay circuits 91a to 92.
d output signals and coefficient generation circuits 92a to 92d
The filter coefficient output from each is multiplied by digital processing. The adder circuits 94a to 94c add the output signals of the multiplier circuits 93a to 93d by digital processing.

[0005]

However, the configuration of the above-described orthogonal transform device has the following problems. (1) Two digital low-pass filters having the same characteristics are required, which causes redundancy in the circuit. (2) Since the multiplication circuit and the sine wave oscillator are required, the circuit amount increases. Therefore, the device becomes expensive and is disadvantageous in terms of circuit mounting. (3) It is necessary for the multiplication circuit to be devised to suppress the leakage of the carrier signal to the output side, which causes deterioration of the quality of the modulation output. (4) It is necessary to adjust the oscillation frequency of the sine wave oscillator and the output power level. Therefore, it takes time and effort to manufacture and adjust the multiplication circuit and the sine wave oscillator.

A digital filter and a quadrature modulator using the same according to the present invention have been made in view of the above-mentioned problems of the prior art. In a quadrature modulator for quadrature modulating two kinds of baseband signals, the conventional quadrature modulator is used. In a digital filter circuit which was required for two per one quadrature modulation circuit, these two digital filter circuits are made common, and time-sequential filtering output signals are time-division multiplexed and output. The purpose is to significantly reduce the scale. Further, it is an object of the present invention to provide an inexpensive digital processing type quadrature modulation device which can achieve size reduction, weight reduction and power consumption reduction by using this digital filter.

Further, in the above-mentioned digital filter, there is provided a digital filter capable of separating a time-division-multiplexed digital-format filtering output signal into signals thereof in order to support applications other than quadrature modulation. It is another purpose to do. Moreover, 2
It is an object of the present invention to provide a quadrature modulator and a digital filter that can handle more than one type of baseband signal.

[0008]

In order to achieve the steam object, the digital filter of the present invention independently filters a plurality of input signals in digital form, and outputs the filtering result at a predetermined time corresponding to the number of input signals. A digital filter having a predetermined number of taps output in a time-division multiplexed format in slots, wherein each of the input signals is sequentially assigned to a predetermined time slot at a period corresponding to the number of input signals and time-division multiplexed. Multiplexing means for forming a multiplexed signal; at least one delay means for sequentially giving a delay of a predetermined unit time obtained by multiplying the number of the predetermined time slots by a predetermined time to the multiplexed signal; Each of the delay means is provided in correspondence with each other, and the multiplexed signal and the front of the same type output from each of the delay means are provided. Multiplied by a predetermined coefficient respectively input signal, and a multiplication and addition means for outputting the filtering result and calculates the sum of the respective multiplication results.

Further, the multiplication and addition means stores a combination of the multiplexed signal and the numerical values output from the respective delay means in advance, and the multiplication and addition results obtained based on the respective predetermined coefficients. It is characterized in that the multiplication and addition results corresponding to the combination of the multiplexed signal and the numerical values output from each of the delay units are output as a filtering result.

Further, the multiplication and addition means correspond to a combination of numerical values output from the multiplexed signal and a part of each of the delay means in advance, and the multiplexed signal and a part of each of the delay means. A plurality of storage means for storing the multiplication and addition results obtained on the basis of the respective predetermined coefficients, and a multiplication of each of the storage means corresponding to a combination of the multiplexed signal and the numerical values output from the delay means. And addition means for calculating the sum of addition results and outputting the result as a filtering result.

Further, the present invention is characterized by further comprising separating means for sequentially separating the filtering results of the multiplexed signals, for each filtering result of the signals of the same type.

The quadrature modulator of the present invention is a modulator for performing quadrature modulation by using a plurality of digital baseband signals having a predetermined phase relationship as a modulation signal, and the plurality of input signals are independent of each other. And a filtering means for outputting the filtering result in a time-division multiplexed format in a predetermined time slot corresponding to the number of input signals.

Further, there is further provided band limiting means for band limiting the output signal of the converting means with a frequency having a predetermined relationship with the frequency of the time slot as a center frequency in a predetermined pass band centered on the center frequency. It is characterized by

Further, the center frequency and the frequency of the time slot have the following relationship.

[0015]

[Number 2] _{f o = (1 + 2m)} nf C / 4 ··· (2) However, (1 + 2m) n / 4 is an integer, f _o is the center frequency, f _C of the band limiting means, said time slot The frequencies m and n are arbitrary positive integers.

Further, the band limiting means is an analog band pass filter, and further comprises conversion means for converting the filtering result output from the filtering means into an analog signal and inputting it to the band limiting means. And

Further, there is further provided invalidating means for passing only the output signal of the converting means corresponding to a predetermined time width of each time slot of the filtering result and invalidating the output signal outside the time width. It is characterized by

Further, among the filtering results, only a filtering result of a predetermined time width of each time slot is validated, and a digital invalidating means for invalidating the filtering result other than the time width is further provided. The converting means is characterized in that only the effective part of the filtering result is digital-to-analog converted.

Further, the filtering means used in the quadrature modulator of the present invention is characterized in that it is any of the above-mentioned digital filters of the present invention. Further, the input signals are two types of signals that are orthogonal to each other. Further, the input signals are two sets of two kinds of signals which are orthogonal to each other, and the two sets of input signals have a predetermined phase relationship.

[0020]

A plurality of baseband signals input to the filter are time-division multiplexed, a delay corresponding to the degree of multiplexing is sequentially given, and a filter is performed for each baseband signal of the same type among the multiplexed baseband signals. The coefficients are multiplied and the sum of the multiplication results is calculated. With this configuration, a large number of baseband signals are multiplied by the filtering coefficient, and
The multiplication result can be performed by the same digital filter. Therefore, the redundancy of the circuit of the digital filter is reduced, which is advantageous in miniaturization and mounting.

The output signal after digital / analog conversion of the multiplexed filtered output signal of the digital filter is banded at a frequency having a predetermined relationship with the repetition frequency of the time slot of the filtered output signal (frequency of the time slot). By limiting and obtaining the quadrature modulation output, the multiplication circuit and the sine wave oscillator of the quadrature modulator are not required. Therefore, the circuit amount of the quadrature modulator can be reduced, and the labor for adjusting the multiplication circuit and the sine wave oscillator becomes unnecessary. Further, since there is no multiplication circuit, it is possible to obtain a quadrature modulation output of good quality without leakage of the carrier signal to the output side.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of a digital filter of the present invention and a quadrature modulator using the same will be described. The digital filter of the present invention described below is intended for use in a quadrature modulator. For this reason, the output is in the form of time-division-multiplexed filter link results of the input signal, although a plurality of types of signals are simultaneously filtered. Therefore, in order to adapt the digital filter of the present invention to general applications other than the quadrature modulator, it is necessary to add a separating means for separating the filtering result for each input signal. It is also possible to separate the filtering result into a number smaller than the number of inputs according to the use and output each to a separate circuit. For example, it is possible to filter four types of input signals and output the filtering results to two systems in which the filtering results of the first and second input signals and the third and fourth input signals are multiplexed. is there. A digital filter having such a configuration has four
It is suitable for applications such as phase shift modulation.

In the quadrature modulator of the present invention, the output of the above-mentioned digital filter of the present invention is D / A converted,
The conversion result is filtered using the BPF, and a two-phase shift keying signal (hereinafter abbreviated as BPSK signal) having a required carrier frequency is extracted. The digital filter output is made so as to alternately output the signals of the respective channels, as described above. Therefore, the signal obtained by D / A converting the output of the digital filter is a combination of two BPSK signal waves. This chopper means 2
The phase difference between the two BPSK signal waves is appropriately given to improve the quality of the output signal. When the baseband signal is input in two channels and is a binary signal, the output of the quadrature modulator is a four-phase PSK signal (hereinafter abbreviated as QPSK signal). When the input of the baseband signal is the n channel and the signal is a binary signal, the output of the quadrature modulator is an n-phase PSK signal wave. Also, when the amplitude of the baseband signal is not binary,
The output of this device is a quadrature amplitude modulation (hereinafter abbreviated as QAM signal) signal. As the carrier frequency, an appropriate value can be selected from values of integral multiples of the clock under predetermined conditions.

Hereinafter, the first digital filter of the present invention will be described.
An example will be described. FIG. 1 is a diagram showing the configuration of a digital filter 1 of the present invention in the first embodiment. The digital filter 1 of the present invention is an improvement of a four-stage FIR (finite impulse response) type digital filter. First, for example, two types of baseband signals of digital format are input in parallel with an 8-bit width. Is time-division multiplexed. The position in the time axis direction where each baseband signal is multiplexed is also called a time slot. The repetition frequency of this time slot is i × f _s (frequency of time slot) when i (i is an integer) types of baseband signals are input to the digital filter 1 at the frequency f _s.
Becomes A delay in units of a clock signal cycle (two clock signal cycles) corresponding to the type of the base band signal is added to the multiplexed base band signal. The respective output signals of the means for giving a delay of two clock signal periods are the same kind of baseband signals. The baseband signals of the same type are sequentially multiplied by the filter coefficient to calculate the sum thereof, and these baseband signals are filtered by the same circuit.

The selector 10 receives, for example, parallel inputs.
2 types of 8-bit wide digital baseband signals
(I channel signal, Q channel signal)
Apply to lots and time-division multiplex. Delay circuit (D₁
~ D₇) 11a to 11g are 8-bit wide D-free
It consists of a flip-flop and has a total of 7 shift levels.
Make up a Dista. The delay circuits 11a to 11g have a base band.
Time-division multiplexing with the selector 10 in synchronization with the input cycle of the range signal
Sequentially shifts the digitized baseband signal in digital form
It As a result, the delay circuits 11a, 11c, 11e, 11
The baseband signals appearing at the output of g are of the same type. You
That is, the baseband signal sequence I_a, I_b, I_c...
And baseband signal sequence Q_a, Q_b, Q_c..., select
Output signal sequence of the selector 10 when multiplexed by the rectifier 10.
Is, for example, I_a, Q_a, I_b, Q_b, I_c, Q_c, ...
・ ・ It becomes. The delay circuits 11a to 11g use this selector.
Basebands that are sequentially input for 10 output band signal sequences
The shift is performed every input period of the range signal. Therefore, delay times
Baseband signal d output from path 11a₁Is Q_dIs
In this case, the baseband signal d output from the delay circuit 11c₂
Is Q_c, The baseband signal d output from the delay circuit 11e
₃Is Q_b, The baseband signal output from the delay circuit 11g
d_FourIs Q_aBecomes On the contrary, it is output from the delay circuit 11a.
Baseband signal d₁Is I_dDelay circuit 11c
Baseband signal d output from₂Is I_c, Delay circuit 11
baseband signal d output from e₃Is I_b, Delay circuit 1
Baseband signal d output from 1g _FourIs I_aBecomes

The coefficient generating circuits 12a to 12d generate digital-type filter coefficients (h _{1 to} h ₄ ) which are multiplied by the delayed baseband signal in the multiplying circuit 13, respectively. Multiplier circuit 13a~13d multiplies the digital form baseband signals d ₁ to d ₄ of which are respectively input and the filter coefficients h ₁ to h ₄ by the digital processing. The adder circuits 14a to 14c respectively include the multiplier circuit 13
a multiplication result m ₁ and multiplication circuit 13b multiplication result m ₂ , multiplication circuit 13a multiplication result m ₃ and multiplication circuit 13b multiplication result m ₄ , and addition circuit 14a addition result m ₁₂ and addition circuit 14b addition The result m ₃₄ is added by digital processing. That is, the addition circuits 14a to 14c as a whole
The sum of the digital multiplication results (m _{1 to} m ₄ ) output from the multiplication circuits 13a to 13d is calculated and output as a filtering result. Note that, in FIG. 1, the connection of the baseband signal and the clock signal of the digital filter 1 which are input for simplification of the drawing are omitted (the same applies hereinafter). In the following description, when referred to as a digital filter clock signal or a quadrature modulator clock,
The clocks that specify the unit delay time of the multiplex of the baseband signal of each digital filter or the digital filter of each quadrature modulator are shown. Further, when the clock of the baseband signal is described, a clock having the same frequency as the data rate of the baseband signal input to each digital filter or the quadrature modulator is shown.

The operation of the digital filter 1 will be described below. FIG. 2 is a time chart showing the timing of signals of each part of the digital filter 1 shown in FIG. In FIG.
(A) shows the clock signal phase of the input baseband signal. (B) shows the clock signal phase of the digital filter 1. (C) shows one baseband signal I (I channel signal). (D) shows another baseband signal Q (Q channel signal). (E) shows the output signal of the selector 10. (F), (G),
(H), (I) shows the result of the multiplication m ₁ ~m ₄ of each multiplication circuit 13 a to 13 d. However, for convenience of illustration, only the multiplication results I and Q are shown as h _k × I and the like. (J) shows the addition result S of the addition circuit 14c.

In FIG. 2 (J), the even phase of the clock signal of the digital filter 1 shown in FIG. 2 (B) corresponds to the multiplication result of the I channel signal, and the digital filter shown in FIG. 2 (B) is also provided. The odd phase of the clock signal of 1 corresponds to the result of the multiplication result of the Q channel signal. That is,
The addition result S ₈ of the adder circuit 14c in the clock signal phase 8 of the digital filter 1 is expressed by the following equation. The addition result S ₈ is the filtering result of the I channel signal.

[0029]

[Equation 3] S ₈ = h ₁ × I _d + h ₂ × I _C + h ₃ × I _b + h ₄ × I _a (3)

The addition result S ₉ of the adder circuit 14c in the clock signal phase 9 of the next digital filter 1 is expressed by the following equation. The addition result S ₉ is the filtering result of the Q channel signal.

[0031]

## EQU4 ## S ₉ = h ₁ × Q _d + h ₂ × Q _C + h ₃ × Q _b + h ₄ × Q _a (4)

Similarly, the addition result of the adder circuit 14 _C after the clock signal phase 10 of the digital filter 1 is expressed by the following equation.

[0033]

S ₁₀ = h ₁ × I _e + h ₂ × I _d + h ₃ × I _C + h ₄ × I _b ... (5.1) S ₁₁ = h ₁ × Q _e + h ₂ × Q _d + h ₃ × Q _c + h ₄ × Q _b ... (5.2)

Therefore, as the addition result of the adding circuit 14c, the filtering results of the I channel signal and the Q channel signal appear alternately, that is, in a time division multiplexed manner.

The second digital filter of the present invention will be described below.
An example will be described. FIG. 3 is a book according to the second embodiment.
It is a figure which shows the structure of the digital filter 2 of invention. Digi
The digital filter 2 performs multiplication like the digital filter 1.
And calculation by addition, delay circuits 11a, 1
Output signals d of 1c, 11e and 11g₁~ D _FourCombination of
Calculate the filtering result corresponding to the
It is stored in the address of ROM 21 corresponding to
Output signal d when filtering₁~ D_FourCombination of
Filtering results from ROM 21 using address as address
It is configured to read the fruit. Note that here
Each part of the digital filter 2
This is the same for each part where the same reference numeral is given to the data 1. ROM2
1 is the output signal d₁~ D_FourCorresponding to the combination of
Store the calculated filtering at the corresponding address
It The digital filter 2 in the second embodiment is a digital filter.
Coefficient generating circuits 12a to 12d in the digital filter 1.
The multiplication circuits 13a to 13d and the addition circuits 14a to 1
3 is replaced by the ROM 21. Digi
By configuring the digital filter 2 as described above,
It is possible to reduce the circuit scale as a body.
Also, the operation speed becomes faster.

The third embodiment of the present invention will be described below.
FIG. 4 is a diagram showing the configuration of the digital filter 3 of the present invention in the third embodiment. In the digital filter 3, the ROM 21 shown in the second embodiment is divided into two, and the ROM 31 is divided.
a and 31b, which are output signal d ₁ of delay circuit 11a and output signal d ₂ of delay circuit 11b, and output signal d ₃ of delay circuit 11c and output signal d of delay circuit 11d, respectively.
₄ is read as an address, and ROM 31a, 3
It is configured to add the output signals of 1b to obtain the filtering result. The parts of the digital filter 3 not described here are the same as the parts shown by attaching the same reference numerals to the digital filter 1 shown in the first embodiment and the digital filter 2 shown in the second embodiment. Is.

The ROMs 31a and 31b have delay times, respectively.
Output signal d of path 11a₁And the output signal d of the delay circuit 11b
₂, And the output signal d of the delay circuit 11c₃And delay circuit
11d output signal d₃Calculated in advance corresponding to the combination of
The filtered results are then combined with their output signals
It is stored in the address indicated by. The adder circuit 32 is R
Output signal r in digital format of OM 31a, 31b₁,
r ₂Are added by digital processing. Digital fill
ROM that stores filtering results
Is arbitrary, add the output signals of these ROMs
The number of adder circuits is increased according to the number of ROMs
It is configured to calculate the sum of output signals. Third implementation
The configuration of the example digital filter 3 is, for example, a baseband signal.
Has a large signal width (number of bits), for example, 16 bits
In such cases, solve the problem of insufficient number of ROM address lines.
There is an advantage that it can be erased.

The fourth digital filter of the present invention will be described below.
An example will be described. FIG. 5 is a diagram showing the configuration of the digital filter 4 of the present invention in the fourth embodiment. In the configuration of the digital filter 4, four types of baseband signals (A, B, C, D) can be filtered by the same circuit. In order to cope with an increase in the types of baseband signals, the digital filter 4 uses the unit delay time as 4 clock signals of the digital filter 4. Each part of the digital filter 4 which is not described here is the same as the part to which the digital filter 1, 2, 3 is denoted by the same reference numeral. The selector 40 is a 4-input 1-output selector, and synchronizes with the clock signal of the digital filter 4 to time-division-multiplex four types of baseband signals A to D in digital format.
Delay circuits _{(D 2 ~D 5) 41a,} (D 6 ~D 9) 41
_{b, (D 10 ~D 13)} 41c is composed of a shift register or the like, respectively, into a baseband signal input, giving the respective delays of four periods in the clock signal period of the digital filter 4. Similarly to the digital filter 1, the digital filter 4 also includes the delay circuit 11a and the adder circuit 41a.
~41c output signal d ₁ to d ₄ from each is baseband signals of the same type, by computing the sum are multiplied by the filter coefficients h ₁ to h ₄ to these output signals d ₁ to d ₄ , Baseband signals A to D are obtained as filtering results.

The baseband signals handled by the digital filter 4 are limited to four types, for example, it is possible to increase to five types or decrease to three types. in this case,
For example, when the number of baseband signals is increased, the multiplicity of the selector 40 is increased according to the type of baseband signal, the clock frequency of the digital filter 4 is increased, and the addition circuit according to the type of baseband signal. The delay time given by each of 41a to 41c is increased. Further, also in the digital filter 4, like the digital filters 2 and 3 shown in the second and third embodiments, the coefficient generation circuits 12a to 12d, the multiplication circuits 13a to 13d, and
The addition circuits 14a to 14c may be replaced with a storage device such as a ROM that stores the filtering result in advance.

FIG. 6 shows the digital filter 4 shown in FIG.
5 is a time chart showing the operation of the selector 40 of FIG. In FIG. 6, (A) shows the phase of the clock signal of the input baseband signal, (B) shows the clock signal phase of the digital filter 4, and (C) shows the first baseband signal A. , (D) show the second baseband signal B, and (E)
Shows C for the third baseband signal, (F) shows D for the fourth baseband signal, and (G) shows the output signal of the selector 40. As can be seen with reference to FIG. 6, the selector 4
0 switches the input baseband signals A to D by the clock signal of the digital filter 4 which is four times the data frequency of each baseband signal to time-division-multiplex the baseband signals.

As shown in FIG. 6G, the adder circuit 41a
~ 41c clock signal of digital filter 4 respectively
When a delay of 4 cycles is given, the output signal of the delay circuit 11a is
Issue d ₁Is the baseband signal A_dIn the case of, the output of the adder circuit 41a
Force signal d₂Is the baseband signal A _C, Output of adder circuit 41b
Signal d₃Is the baseband signal A_C, Output signal of the adder circuit 41c
Issue d_FourIs the baseband signal A_dBecomes Similarly, the delay times
Output signal d of path 11a₁Is the baseband signal B_dIf
Output signal d of the arithmetic circuit 41a₂Is the baseband signal B_C, Addition
Output signal d of circuit 41b₃Is the baseband signal B_C, Addition times
Output signal d of path 41c_FourIs the baseband signal B_dBecomes Late
Output signal d of the extended circuit 11a₁Is the baseband signal C_dPlace
Output signal d of the adder circuit 41a₂Is the baseband signal
C_C, The output signal d of the adder circuit 41b₃Is the baseband signal C
_C, The output signal d of the adder circuit 41c_FourIs the baseband signal C_d
Becomes Output signal d of the delay circuit 11a₁Is the baseband signal
D_dIn the case of, the output signal d of the adder circuit 41a₂Is the baseband
Signal D_C, The output signal d of the adder circuit 41b₃Is the baseband signal
Issue D_C, The output signal d of the adder circuit 41c_FourIs the baseband signal
D_dBecomes Therefore, it is input to the multiplication circuits 13a to 13d.
The baseband signals to be reproduced are of the same type and are shown in the first embodiment.
For each baseband signal as with the digital filter 1
It is possible to obtain each filtering result
It

Hereinafter, the fifth digital filter of the present invention will be described.
An example will be described. FIG. 7 is a diagram showing the configuration of a 2-channel output digital filter 50. The digital filters 1 to 4 described in each of the above embodiments are configured to output the filtering result in a multiplexed state so as to be suitable for the quadrature modulator of the present invention described later. The digital filter 50 is provided with a separation circuit in order to apply the above digital filter to other general uses.

In FIG. 7, the digital filter 51
Is any one of the digital filters 1 to 4 described in the first to fourth embodiments.
The separation circuit (SW) 52 separates the time-division-multiplexed baseband signal I-channel signal and Q-channel signal filtering results output from the digital filter 51 into individual filtering results. The separation circuit 52 may be further provided with, for example, an interface circuit or the like for adjusting the timing with various devices connected to the digital filter 50.

FIG. 8 is a diagram showing a circuit example of the separation circuit 52. FIG. 9 is a time chart showing the operation of separation circuit 52 shown in FIG. Each signal waveform of FIG. 9 shows a signal waveform of each portion of the separation circuit 52 denoted by the same reference numeral in FIG. In FIG. 9, (A) is a signal waveform of the clock CLK1 of the baseband signal, (B) is a signal waveform of the clock CLK2 of the digital filter 50,
(C) is the input signal S of the separation circuit 52, and (D)
Is the clock CLK1 of the odd digital filter 50.
(E) is a component extracted from the phase of the clock CLK1 of the even-numbered digital filter 50, and (F) and (G) are used to match the output timing of the two channels. It is the one with the correct timing. The signal shown in (F) is used as an I channel signal output, and the signal shown in (G) is used as a Q channel signal output.

The separating circuit 52 is a D flip-flop 52.
1 to 523. Further, in FIGS. 8 and 9, CLK1 represents a clock signal of a baseband signal, and C
LK2 is a clock signal for the digital filter 50. The operation of the separation circuit 52 will be described below. The D flip-flop 521 is the clock signal C of the baseband signal shown in FIG. 9A at the falling timing of the clock signal CLK2 of the digital filter 50 shown in FIG. 9B.
Latch LK1. The D flip-flop 522 latches the output signal S of the digital filter 51 at the rising timing of the non-inverted output signal of the D flip-flop 521, and the D flip-flop 524 performs the digital filtering at the rising timing of the inverted output signal of the D flip-flop 521. Latch the output signal of 51. At the rising timing of the clock CLK1 of the baseband signal, the D flip-flop 52 shown in FIGS.
The output signals of 2, 524 are latched by the D flip-flops 523, 524, respectively.
The I channel signal output and the Q channel signal output shown in (F) and (G) are used.

FIG. 10 is a diagram showing the configurations of the 4-channel output digital filter 55 of the present invention and the 2-channel output digital filter 60. In FIG.
(A) shows the configuration of the digital filter 55, and (B) shows the configuration of the digital filter 56. The digital filter 55 separates the filtering output of the digital filter 4 shown in FIG.
The digital filter 60 is a format in which the output signal of the digital filter 4 is time-division multiplexed with the filtering output corresponding to the baseband signals A and C, and the baseband signals B and D are also included.
The filtering output corresponding to is output in a time-division multiplexed format.

In FIG. 10A, the digital filter 56 is the digital filter 4 or a modification thereof. The separation circuit 57 separates the output signal of the digital filter 56 into four channels corresponding to the baseband signals A to D,
Further, if necessary, the timings of the respective output signals are adjusted and output.

In FIG. 10B, the digital filter 61 is the digital filter 4 or a modification thereof.
The separation circuit 62 time-division multiplexes the output signal of the digital filter 61 with the filtering output corresponding to the baseband signals A and C, and time-division multiplexing the filtering output corresponding to the baseband signals B and D. And output in the same format with the correct timing.

FIG. 11 is a time chart of the operation of the separation circuits 57 and 62 of the digital filters 55 and 60 shown in FIG. In FIG. 11, (A) shows the clock of the baseband signal, (B) shows the input signals of the separation circuits 57 and 62, and (C) to (F) show four output signals of the digital filter. The output signal of the separation circuit when dividing into channels is shown. (C) is the output A signal of the separation circuit 57, (D) is the output B signal of the separation circuit 57, (E) is the output C signal of the separation circuit 57, (F) ) Is a signal of the output D of the separation circuit 57.
(G) and (H) show the output signal of the separation circuit 62, and (G) shows the first channel A and the third channel C.
2H shows the multiplexed output signal of the second channel B
And a fourth channel D multiplexed output signal is shown.

As a sixth embodiment, a first example of the quadrature modulator of the present invention using the digital filters shown in the first to fifth embodiments will be described below. FIG. 12 is a diagram showing the configuration of a first digital processing type quadrature modulation circuit 65 using the digital filter of the present invention. In FIG. 12, the digital filter 66 is one of the digital filters 1 to 3 of the present invention shown in the first to third embodiments. The filtering output of the digital filter 66 is input to a digital / analog conversion circuit (D / A) 67 and converted into an analog signal. Chopper circuit 6
Reference numeral 8 invalidates the analog output signal obtained as a result of the conversion in the digital / analog conversion circuit 67 at a time interval of a predetermined pattern (the output signal is set to 0 level). The chopper circuit 68 converts the signal waveform of the output signal I of the digital / analog conversion circuit 67 into a pulse-shaped signal waveform. In this way, by making the output signal of the digital / analog conversion circuit 67 into a pulse-shaped signal waveform, the 0th-order hold characteristic is improved to a high frequency, the aperture distortion effect of the modulated wave is reduced, and the frequency of the modulated output signal is reduced. It is possible to improve the characteristics. However, while the chopper circuit 68 is effective in improving the performance of the quadrature modulation circuit 65, the quadrature modulation circuit 65
It is not a mandatory configuration requirement of. Band pass filter (BP
F) 69 is a frequency having a relationship below the clock signal and the quadrature modulation circuit 65 as the center frequency f _o, a higher frequency side with respect to the center frequency, and has a predetermined passband low frequency side, The output signal of the chopper circuit 68 is filtered.

FIG. 13 is a circuit diagram of the chopper circuit 6 shown in FIG.
It is a figure which shows the structure of No. 8. The chopper circuit 68 is composed of a changeover switch controlled by a gate signal.
In FIG. 13, a signal I is an input signal of the chopper circuit 68, and a signal O is an output signal of the chopper circuit 68.
The input side of the chopper circuit 68 has a terminal to which the signal I is input and two terminals connected to the ground side (0 V). By selecting the input side from the digital / analog conversion circuit 67 of these terminals, The output signal of the digital / analog conversion circuit 67 is passed to validate the output signal of the chopper circuit 68, and the output signal of the chopper circuit 68 is invalidated by selecting the ground side.

FIG. 14 is a time chart for explaining the operation of the digital processing type first quadrature modulation circuit 65 of the present invention. In FIG. 14, (A) is a clock of the quadrature modulation circuit 65. (B) and (C) show the digital filter 66.
3D is an example of an input signal to the digital / analog converter circuit 67. FIG. 4D shows an output signal waveform of the digital / analog conversion circuit 67. The signal waveform is obtained by alternately switching the signal waveforms obtained by filtering two input signals every clock cycle. Equal to (E) is a gate signal of the chopper circuit 68,
(F) shows the output signal waveform of the digital / analog conversion circuit 67 cut out in pulses by the chopper circuit 68. (F) shows the I channel signal and the Q channel signal as shown in (G). Have a shape that appears alternately. (G) is a diagram showing the I channel signal and the Q channel signal of the output signal of the digital / analog conversion circuit 67, and (G _a ) is the output signal of the digital / analog conversion circuit 67 shown in (G). I channel signal in
(G _b ) is the Q channel signal of the output signals of the digital / analog conversion circuit 67 shown in (G),
(H) is another example of the gate signal of the chopper circuit 68 shown in (E), and (I) is the output signal of the chopper circuit 68 when the gate signal shown in (H) is input. is there.

14A to 14G_b) Signal waves shown in
It will be explained with reference to the shape. (G_a) And (G_a) Has a phase
They differ by a certain amount. That is, in the case of this figure, I
The channel signal has a clock period (T_C= 1 / f _C)of
It is ahead of the Q channel signal by 1/4 cycle. (G
_a) And (G_b) From each BPSK signal
The addition results in a QPSK signal. Quadrature modulation circuit of the present invention
The digital filter 66 of 65 has the first filter as described above.
Examples of the digital filters 1 to 3 shown in the third embodiment
It is either. Output signals of digital filters 1-3
Is (G_a), The I-channel signal shown in FIG.
(G_b) The Q channel signal shown in FIG.
It is in the form of a signal. Of this digital filter 66
Desired carrier frequency component using BPF from output signal
To obtain the QPSK signal. As described below,
Carrier frequency (center frequency of bandpass filter 69)
Equal to the clock frequency of the quadrature modulation circuit 65, and
Is the clock frequency f_CTo have a certain relationship with
QPSK signal can be extracted by selecting
It

When the signal waveform of the gate signal of the chopper circuit 68 is as shown in FIG. 14 (H), the output signal of the chopper circuit 68 is as shown in (I). Figure 1
4 (A) to (G _b ), which is different from the above case,
As shown in (J), the phase of the I channel signal is 3 / of the cycle of the clock of the quadrature modulation circuit 65 (T _C = 1 / f _C ).
It is ahead of the Q channel signal by 4 periods. Also in this case, the QPSK signal can be generated by selecting the carrier frequency f _o equal to the clock frequency or having a predetermined relationship as described later.

FIG. 16 is a diagram for explaining the relationship between the phase difference given by the gate signal and the carrier frequency which becomes the QPSK wave, and the phase space of the modulation output at that time. In the time chart of FIG. 15, when the phase difference between the I channel signal and the Q channel signal and the carrier frequency f _o satisfy the relationship of the following equation, the output signal of the bandpass filter 69 is QPSK.
Become a signal. Here, when n is an arbitrary positive integer, the phase difference between the I channel signal and the Q channel signal is T _C / n (T _C
= 1 / f _C ),

[0056]

[6] _{f o = (1 + 2m)} nf C / 4 ··· (6) Here, n and m are the combination of a (1 + 2m) n / 4 = integer. f _C is the clock frequency of the quadrature modulation circuit 65.

For example, in the example shown in FIG. 14, n = 4
is there. That is, for example, f when m = 0_o= F_C,
f when m = 1_o= 3f_CIs a QPSK signal
It The phase difference between the I channel signal and the Q channel signal is T_C/
When n, carrier frequency f _oI channel signal and Q channel
The phase difference between the channel signals is 2π / n. Therefore, these
Phase difference of the signal_CIn case of / 4, f_C= F_oIt is
The condition that
The components of the transmitted signal have a phase difference of π / 2. Servant
The obtained quadrature modulation signal (bandpass filter 69
Output signal) becomes a QPSK signal. Also, the phase difference is 3
T_CIn case of / 4, I channel signal and Q channel signal
Since the phase difference is 3π / 2, a QPSK signal is also generated.
It

FIG. 15 is a diagram showing frequency spectra and phases of I-channel signals and Q-channel signals. Figure 15
14, (A) and (C) show the frequency spectra of the I-channel signal and the Q-channel signal shown in (G _a ), (G _b ) of FIG. 14, respectively, and (B) of FIG.
4 (G _a ) shows the phase of the I-channel signal,
(D) shows the phase of the Q channel signal shown in FIG. 14 (G _b ) when the phase of the I channel signal shown in (B) is used as a reference, and (E) shows the bandpass. An example of characteristics of the filter 69 is shown. (F) shows the carrier frequency f _o from the output signal of the chopper circuit 68 shown in FIG. 14 (F).
Represents the phase space of the QPSK signal when is selected to be equal to the clock frequency f _C of the quadrature modulation circuit 65. When the phases of the I channel signal and the Q channel signal shown in (B) and (C) are shifted by 90 degrees, the output signal of the quadrature modulation circuit 65 becomes a QPSK signal. In this case, carrier frequency f _o = f
_In the case of _C , 3f _C , ..., The output signal of the quadrature modulation circuit 65 becomes a QPSK signal. When a frequency component whose carrier frequency f _o is equal to the clock frequency f _C of the quadrature modulation circuit 65 is taken out using the bandpass filter 69 having the frequency characteristic shown in (E), it is as shown in (D). A spectrum QPSK signal can be generated.

Similarly, the QPSK signal can be generated from the output signal of the chopper circuit 68 shown in FIG. In FIG. 15, (G) and (I) show the frequency spectra of the I channel signal and the Q channel signal shown in FIG. 14 (J), respectively. (H) indicates the phase of the I channel signal shown in (G), and (J)
Indicates the phase for each frequency component of the Q channel signal with reference to (H). The phases of (H) and (J) are 9
When they are deviated by 0 degree, the output signal of the bandpass filter 69 becomes the QPSK signal. That is, the carrier signal frequency f
_C = f _o, the output signal of the band-pass filter 69 is QPSK signal in the case of 3f _o · · ·. When a frequency component whose carrier frequency f _o is equal to the clock frequency f _C of the quadrature modulation circuit 65 is extracted using the bandpass filter 69 having the frequency characteristic shown in (K), QPSK of the frequency spectrum shown in (K) It is possible to generate a signal. (L) is a QPS when the output signal of the chopper circuit 68 shown in FIG. 14 (J) is selected so that the center frequency f _o is equal to the clock frequency f _C of the quadrature modulation circuit 65.
The phase space of a K signal is shown.

As a seventh embodiment, a second example of the quadrature modulator of the present invention using the digital filters shown in the first to third embodiments will be described below. FIG. 16 is a diagram showing the configuration of a second digital processing type quadrature modulation circuit 70 using the digital filter of the present invention. First, the configuration of the quadrature modulation circuit 70 will be described. Each part of the quadrature modulation circuit 70 not described here is the same as the part described with the same reference numerals attached to the quadrature modulation circuit 65.

The quadrature modulation circuit 70 has a chopper circuit 71 in front of a digital / analog conversion circuit 67 instead of the chopper circuit 68 of the quadrature modulation circuit 65 shown in the sixth embodiment, and a digital / analog conversion circuit 67. Digitally inserts zero data that sets the output signal of to the reference value (zero level). The digital / analog conversion circuit 67 has a conversion cycle of at least 1/2 or less of the cycle of the time slot of the output signal of the digital filter 66, or the data input from the chopper circuit 71.
Analog / digital conversion is performed sequentially regardless of the operation clock of 0. By configuring the quadrature modulation circuit 70 as described above, the digital / analog conversion circuit 67 converts the zero level portion inserted into the time slot of the output signal of the digital filter 66 by the chopper circuit 71 into a zero level. This operation eventually leads to the quadrature modulation circuit 65.
Is equivalent to inserting a zero level into the output signal of the digital / analog conversion circuit 67 by the chopper circuit 68, and effectively reduces the aperture distortion of the output signal of the quadrature modulation circuit 70.

The operation of the quadrature modulation circuit 70 will be described below. The digital filter 66 is one of the digital filters 1, 2, and 3 shown in the first to third embodiments, filters the input I-channel signal and Q-channel signal, and time-division-multiplexes the filtering results of these signals. Convert and output. The chopper circuit 71 digitally inserts zero data into a predetermined range of each time slot of the output signal of the digital filter 66. Chopper circuit 7
The output signal 1 is converted into an analog signal in the digital / analog conversion circuit 67. Chopper circuit 7
The output signal of 1 is filtered by the bandpass filter 69, and only a predetermined frequency component is output. As described above, the output signal waveform of the digital / analog conversion circuit 67 of the quadrature modulation circuit 70 becomes the same as the output signal waveform of the chopper circuit 68 of the quadrature modulation circuit 65, that is, the signal waveform shown in FIG. . A QPSK signal can be obtained by filtering the output of the digital / analog conversion circuit 67 with the bandpass filter 69.

The structure of the chopper circuit 71 will be described below. FIG. 17 is a diagram showing a configuration example of the chopper circuit 71 of the second quadrature modulation circuit 70. When the digital output signal of the digital filter 66 has an n-bit width, each switch (SW _i ) switches the input signal I _i (i is an integer) and the zero data Z _i according to the gate signal, and outputs O _i.
Output to.

FIG. 18 is a diagram showing a configuration example of each switch of the chopper circuit 71. The chopper circuit 71 includes switches 712a and 712b and a NOT circuit 713. In FIG. 18, switches 712a and 712b
Is a switch controlled by a gate signal. As shown in FIG. 18, the switch 712a and the switch 712 are
b performs operations opposite to each other with respect to the same logical value of the gate signal. Therefore, if the gate signal is a logical one,
Switch 712a is closed and switch 712b is open. If the gate signal is a logic zero, switch 712a is open and switch 712b is closed.

As the eighth embodiment, a multi-channel quadrature modulator of the present invention using the digital filter shown in the fourth embodiment will be described below. FIG. 19 is a diagram showing a configuration of a digital processing type multi-channel quadrature modulation circuit 75 using the digital filter of the present invention. In the eighth embodiment, the case where quadrature modulation is performed on four types of baseband signals is shown as an example. Each part of the quadrature modulation circuit 75 not described here is the same as the sixth embodiment,
The same applies to the respective parts shown by attaching the same symbols to the quadrature modulation circuits 65 and 70 of the seventh embodiment.

The structure and operation of the quadrature modulation circuit 75 will be described below. In FIG. 19, the digital filter 76
Is the digital filter 4 of the fourth embodiment or a digital filter shown as a modification thereof. That is, 4
The types of baseband signals are filtered, and the respective filtering results are time-division multiplexed and output. The output signal (filtering result) of the quadrature modulation circuit 75 is digital / analog converted by the digital / analog conversion circuit 67. The chopper circuit 68 cuts out the analog output signal of the digital / analog conversion circuit 67 at each time interval of a predetermined pattern for each output cycle,
Switching between the input signal and zero level. As described in the sixth and seventh embodiments, the chopper circuit 68 changes the output signal of the digital / analog conversion circuit 67 into a pulse-shaped signal waveform, so that the zero-order hold characteristic is improved. It improves up to the range frequency, reduces the aperture distortion effect of the modulated wave, and improves the frequency characteristic of the modulated wave. The output signal of the chopper circuit 68 is band-limited by the bandpass filter 69 and output. Quadrature modulation circuit 7
It is also possible to have a configuration in which the chopper circuit 71 is placed in front of the digital / analog conversion circuit 67 of No. 5 and the chopper circuit 68 is removed, that is, a configuration similar to the quadrature modulation circuit 70 shown in the seventh embodiment. Further, the types of input baseband signals are not limited to four types, and by appropriately changing the configuration of the digital filter and chopper circuit 68,
It is possible to perform quadrature modulation on any number of baseband signals.

FIG. 21 is a time chart for explaining the operation of the multi-channel quadrature modulator 75 described above.
20, (A) is the clock of the input baseband signal, (B) is the output signal of the digital filter 76, (C) is the gate signal of the chopper circuit 68, and (D) is. , Digital / analog conversion circuit 67
Is a signal waveform obtained by cutting out the output signal waveform of (1) in a pulse shape by the chopper circuit 68. The gate signal is generated at a timing when the filtering result of the baseband signals A to D becomes π / 8 in phase with the clock signal of the quadrature modulation circuit 75. With reference to the signal of the baseband signal A, the second
The baseband signal of is delayed by 2/8 of the clock period (T _C ). The third baseband signal C is delayed by 5/8, the fourth baseband signal D is delayed by 7/8, (E)
Is another example of the gate signal of the chopper circuit 68, (F) is an output signal of the chopper circuit 68,
(G) is another example of the gate signal of the chopper circuit 68, and (H) is an output signal of the chopper circuit 68 when the gate signal shown in (G) is input.

As shown in FIGS. 20A to 20F, when the signal of the first baseband signal is used as a reference, the signal of the second channel B is 3π / 8 of the clock period (T _C ), The signal of the third channel C is 5π / 8, and the signal of the fourth channel D is 6
It is delayed by π / 8. As described above, the phase point of the signal can be arranged every T _C / 8 by giving an appropriate gate signal. As a result, the carrier frequency f _o
By taking out a predetermined frequency component by a bandpass filter 69 the clock frequency f _o of the quadrature modulation circuit 75 to select the appropriate relationship with, it is possible to obtain 8-phase PSK signal.

As shown in FIGS. 20G and 20H, the amplitude levels of the signals of the first and second channels (A and B) are the same as those of the third and fourth channels (C and D). ) Is given to the circuit so that it is different from the amplitude level of the signal. At this time, the phase point of the signal is arranged for each T _C / 4 and the amplitude is arranged in two ways. Therefore, a QAM signal can be obtained by extracting a necessary frequency component by the BPF.

FIG. 21 shows the phase of the output signal shown in FIG. In FIG. 21, (A) corresponds to FIG.
9 (D) shows the phase space of the 8-phase PSK signal when the clock frequency is selected as the carrier frequency, and (B)
Is 8 when the carrier frequency f _o and the clock frequency f _C of the quadrature modulation circuit 75 are selected from FIG. 21 (D).
The phase space of the phase PSK signal is shown, and (C) shows the quadrature modulation circuit 75 as the carrier frequency f _o from FIG. 21 (H).
3 shows the phase space of the QAM signal when the clock frequency f _C is selected.

[0071]

As described above in detail, according to the digital filter of the present invention, a plurality of input digital signals are time-division-multiplexed and then a predetermined digital filter is used as a unit for the period of the clock frequency. By performing a filtering operation with delay, it is possible to filter a plurality of input signals by the same circuit. Therefore, the redundancy of the circuit of the digital filter can be reduced, and therefore, the size and cost of the digital filter can be reduced, which is advantageous in mounting. Further, since this filtering result is output in a time-division multiplexed format, the application to the quadrature modulator of the present invention is facilitated. Further, by separating the output signal of the digital filter of the present invention, application to other than the quadrature modulator is facilitated.

The quadrature modulation apparatus of the present invention synthesizes two baseband signals in this type of apparatus, shapes the digital signal waveform, passes the signal through a chopper circuit, and directly extracts the quadrature modulation output from the output signal waveform. Because
It is inexpensive, can be miniaturized, and does not impair the required characteristics. Therefore, the present invention significantly reduces the circuit scale of the digital filter. Further, the multiplication circuit and the sine wave oscillator, which were required in the conventional quadrature modulator, are not required. Further, the labor for manufacturing and adjusting the multiplication circuit and the sine wave oscillator, which are required in the conventional quadrature modulator, is eliminated.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a digital filter of the present invention in a first embodiment.

FIG. 2 is a time chart showing the timing of signals of various parts of the digital filter shown in FIG. In FIG.
(A) shows the clock signal phase of the input baseband signal, (B) shows the clock signal phase of the digital filter 1, (C) shows one baseband signal I (I channel signal). (D) shows another baseband signal Q (Q
Channel signal), (E) indicates an output signal of the selector 10, (f), (G), (H), and (I) indicate multiplication results m _{1 to} m ₄ of the multiplication circuit, (J) is
The addition result S of the adder circuit 14c is shown.

FIG. 3 is a diagram showing a configuration of a digital filter of the present invention in a second embodiment.

FIG. 4 is a diagram showing a configuration of a digital filter of the present invention in a third exemplary embodiment.

FIG. 5 is a diagram showing a configuration of a digital filter of the present invention in a fourth exemplary embodiment.

6 is a time chart showing the operation of the selector of the digital filter shown in FIG. In FIG. 6, (A)
Indicates the phase of the clock signal of the input baseband signal,
(B) shows the clock signal phase of the digital filter, (C) shows the first baseband signal A, and (D).
Represents the second baseband signal B, (E) represents the third baseband signal C, (F) represents the fourth baseband signal D, and (G) represents the selector. The output signal of is shown.

FIG. 7 is a diagram showing a configuration of a 2-channel output digital filter.

FIG. 8 is a diagram illustrating a circuit example of a separation circuit.

9 is a time chart showing the operation of the separation circuit shown in FIG. In FIG. 9, (A) is the signal waveform of the clock CLK1 of the baseband signal, and (B) is
Is the signal waveform of the clock CLK2 of the digital filter, (C) is the input signal S of the separation circuit,
(D) is an odd digital filter clock CLK
1 is a component extracted from the phase of 1, and (E) is a component extracted from the phase of the clock CLK1 of the even digital filter, and (F) and (G) are for matching the output timing of the two channels. It is the one with the correct timing.

FIG. 10 is a diagram showing configurations of a 4-channel output digital filter of the present invention and a 2-channel output digital filter.

11 is a time chart of the operation of the separation circuit of the digital filter shown in FIG. In FIG.
(A) shows the clock of the baseband signal.
(B) shows an input signal of the separation circuit, and (C) to (F).
Shows the output signal of the separation circuit when the output signal of the digital filter is divided into four channels, (C) is the signal of the output A of the separation circuit, and (D) is the signal of the output B of the separation circuit. Where (E) is the signal of the output C of the separation circuit, (F) is the signal of the output D of the separation circuit,
(G) shows the multiplexed output signals of the first channel A and the third channel C, and (H) shows the second channel B and the fourth channel.
3 shows a multiplexed output signal of channel D of FIG.

FIG. 12 is a first example using the digital filter of the present invention.
FIG. 3 is a diagram showing a configuration of a digital processing type quadrature modulation circuit of FIG.

13 is a diagram showing a configuration of the chopper circuit shown in FIG.

FIG. 14 is a time chart explaining the operation of the first digital processing quadrature modulation circuit of the present invention. In FIG. 14, (A) is a clock of the quadrature modulation circuit,
(B) and (C) are examples of the input signal to the digital filter, (D) shows the output signal waveform of the digital / analog conversion circuit, and (E) is the gate signal of the chopper circuit, (F) shows the output signal waveform of the digital / analog conversion circuit cut out in pulses by a chopper circuit, and (G) shows the I channel signal and Q channel signal of the output signal of the digital / analog conversion circuit. (G _a ) is the digital signal shown in (G) /
The I channel signal of the output signals of the analog conversion circuit, (G _b ) is the Q channel signal of the output signals of the digital / analog conversion circuit shown in (G),
(H) is a modification of the gate signal of the chopper circuit shown in (E), and (I) is an output signal of the chopper circuit when the gate signal shown in (H) is input.

FIG. 15 is a diagram showing frequency spectra and phases of I-channel signals and Q-channel signals. In FIG.
(A) and (C) are respectively (G _a ),
The frequency spectra of the I channel signal and the Q channel signal shown in (G _b ) are shown. (B) is FIG. 14 (G _a ).
Shows the phase of the I channel signal shown in (D),
_14B shows the phase of the Q channel signal shown in FIG. 14G when the phase of the I channel signal shown in FIG. 14B is used as a reference, and FIG.
14F shows the phase space of the QPSK signal when the carrier frequency f _o is selected to be equal to the clock frequency f _C of the quadrature modulation circuit from the output signal of the chopper circuit shown in FIG. ) And (I) respectively show the frequency spectrums of the I channel signal and the Q channel signal shown in FIG. 14 (J), (H) shows the phase of the I channel signal shown in (G), and J) shows the phase for each frequency component of the Q channel signal when (H) is the reference, (K) shows the frequency characteristics of the bandpass filter, and (L) is shown in FIG. the output signal of the chopper circuit shown, shows the phase space in the QPSK signal when the selected equal to the center frequency f _o to the clock frequency f _C of the quadrature modulation circuit.

FIG. 16 shows a second example using the digital filter of the present invention.
FIG. 3 is a diagram showing a configuration of a digital processing type quadrature modulation circuit of FIG.

FIG. 17 is a diagram showing a configuration example of a chopper circuit of a second quadrature modulation circuit.

18 is a diagram showing a configuration example of each switch of the chopper circuit shown in FIG.

FIG. 19 is a diagram showing a configuration of a digital processing type multi-channel quadrature modulation circuit using the digital filter of the present invention.

FIG. 20 is a time chart explaining the operation of a multi-channel quadrature modulator. 20, (A) is the clock of the input baseband signal, (B) is the output signal of the digital filter, (C) is the gate signal of the chopper circuit, and (D) is the digital signal. Is a signal waveform obtained by cutting the output signal waveform of the analog-analog conversion circuit into pulses by a chopper circuit, (E) is another example of the gate signal of the chopper circuit, and (F) is the output signal of the chopper circuit. Yes, (G) is another example of the gate signal of the chopper circuit, and (H) is the output signal of the chopper circuit when the gate signal shown in (G) is input.

21 shows a phase of the output signal shown in FIG.

FIG. 22 is a diagram illustrating a configuration of a conventional orthogonal transform device.

23 is a diagram illustrating the configuration of the digital low-pass filter illustrated in FIG.

[Explanation of symbols]

1, 2, 3, 4, 50, 51, 55, 56, 60, 6
1,66,76 ... Digital filter, 10,40
..Selectors, 11, 41 ... Delay circuits, 12 ...
Coefficient generation circuit, 13 ... Multiplication circuit, 14, 32 ...
Adder circuits 21, 31, ... ROM, 52, 57, 62
... Separation circuit, 521 to 525 ... D flip-flop, 65, 70, 75 ... Quadrature modulation circuit, 67 ...
・ Digital / analog conversion circuit, 68, 71 ... Chopper circuit, 69 ... Band pass filter, 711
712 ... Switch, 713 ... NOT circuit

Claims (15)

[Claims] 1. A digital signal having a predetermined number of taps, each of which independently filters a plurality of digital format input signals, and outputs the filtering result in a time-division multiplexed format in a predetermined time slot corresponding to the number of input signals. A multiplexing unit for sequentially allocating each of the input signals to a predetermined time slot in a cycle corresponding to the number of input signals and time-division-multiplexing into a multiplexed signal; At least one delay means for sequentially giving a delay of a predetermined unit time obtained by multiplying the number of time slots by a predetermined time; and the multiplex means and the delay means, each of which is provided corresponding to the multiplex signal and the multiplex signal. The input signals of the same type output from each delay means are respectively multiplied by a predetermined coefficient, and the sum of the multiplication results is calculated. Digital filters with a multiplication and addition means for outputting the filtering result by. 2. The multiplication and addition means stores in advance a combination of the multiplexed signal and the numerical values output from the respective delay means, and the multiplication and addition results obtained based on the respective predetermined coefficients. 2. The digital filter according to claim 1, wherein the digital filter is configured by the storage means, and outputs a multiplication and addition result corresponding to a combination of the multiplexed signal and the numerical values output from each of the delay means as a filtering result. 3. The multiplying and adding means corresponds to a combination of numerical values output from the multiplexed signal and a part of each of the delay means in advance, and the multiplexed signal and a part of each of the delay means. A plurality of storage means for storing the multiplication and addition results obtained based on the respective predetermined coefficients, and multiplication of each of the storage means corresponding to a combination of the multiplexed signal and the numerical values output from the delay means. The digital filter according to claim 1, further comprising: an addition unit that calculates a sum of addition results and outputs the result as a filtering result. 4. The separation means for separating the filtering result of each of the multiplexed signals sequentially for each filtering result of the signals of the same type, according to any one of claims 1 to 3. Digital filter described. 5. A modulator that performs quadrature modulation by using a plurality of digital baseband signals having a predetermined phase relationship as a modulation signal, wherein the plurality of input signals are independently filtered, and the filtering result is obtained. A quadrature modulator having a filtering means for outputting in a time division multiplexed format in a predetermined time slot corresponding to the number of input signals. 6. A band limiting means for limiting the output signal of the converting means to a frequency having a predetermined relationship with the frequency of the time slot as a center frequency in a predetermined pass band centered on the center frequency. The quadrature modulator according to claim 5, wherein 7. The quadrature modulator according to claim 6, wherein the center frequency and the frequency of the time slot have the following relationship. [Number 1] _{f o = (1 + 2m)} nf C / 4 ··· (1) provided that, (1 + 2m) n / 4 is an integer, f _o is the center frequency, f _C of the band limiting means, said time slot The frequencies m and n are arbitrary positive integers. 8. The band limiting means is an analog band pass filter, and further comprises conversion means for converting the filtering result output from the filtering means into an analog signal and inputting it to the band limiting means. The quadrature modulator according to claim 6 or 7. 9. A nullification unit for passing only the output signal of the conversion unit corresponding to a predetermined time width of each time slot of the filtering result and invalidating the output signal other than the time width. The quadrature modulator according to claim 8, wherein 10. A digital invalidating unit that validates only a filtering result of a predetermined time width of each of the time slots among the filtering results and invalidates the filtering result other than the time width, 9. The quadrature modulator according to claim 8, wherein the conversion means performs digital / analog conversion on only an effective part of the filtering result. 11. The multiplexing means, wherein the filtering means sequentially allocates each of the input signals to a predetermined time slot in a cycle corresponding to the number of input signals and time-division-multiplexes the multiplexed signals into multiplexed signals. At least one delay means for sequentially giving a delay of a predetermined unit time obtained by multiplying the number of the predetermined time slots by a predetermined time to the signal, and provided corresponding to each of the multiplexing means and the delay means, 6. The multiplexed signal and each of the input signals of the same type output from each of the delay units are multiplied by a predetermined coefficient, and the sum of the multiplication results is calculated and output as a filtering result. 10. The quadrature modulator according to any one of 10 to 10. 12. The multiplication and addition means stores in advance a combination of numerical values output from the multiplexed signal and each of the delay means, and the multiplication and addition result obtained based on each of the predetermined coefficients. 12. The quadrature modulator according to claim 11, wherein the quadrature modulation device is configured by the storage means, and outputs a multiplication and addition result corresponding to a combination of the multiplexed signal and the numerical values output from each of the delay means, as a filtering result. . 13. The multiplying and adding means corresponds to a combination of numerical values output from the multiplexed signal and a part of each delay means in advance, and the multiplexed signal and a part of each delay means. A plurality of storage means for storing the multiplication and addition results obtained based on the respective predetermined coefficients, and multiplication of each of the storage means corresponding to a combination of the multiplexed signal and the numerical values output from the delay means. The quadrature modulator according to claim 11, further comprising: an addition unit that calculates a sum of addition results and outputs the result as a filtering result. 14. The quadrature modulator according to claim 5, wherein the input signals are two types of signals that are orthogonal to each other. 15. The input signal comprises two sets of two orthogonal signals.
The quadrature modulator according to any one of claims 5 to 13, wherein the two types of input signals have a predetermined phase relationship.