JPH0738000A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve writing efficiency in an EEPROM for writing electrical information using impact ionization. CONSTITUTION:The number of impact ionizations can be increased by matching a channel direction 6 of EEPROM with the orientation <001> utilizing that impact ionization probability is the highest in the orientation <001> of silicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a MOS type memory device for electrically writing data.

[0002]

2. Description of the Related Art A P-N junction is a basic structure of a semiconductor device. A phenomenon that occurs when a reverse voltage is applied to this P-N junction will be described below. Since applying a high reverse voltage gives high energy to carriers (electrons), these electrons form Si in the crystal lattice.
It can be broken by colliding with an atomic bond. This is called impact ionization (hereinafter referred to as impact ionization). When the bond is broken, an electron-hole pair is generated, and this state is shown in FIG. 5 using an energy band diagram. As shown in FIG. 5, the electrons 2 in the conduction band 1 and the electrons 4 in the valence band 3 are subjected to the Coulomb interaction, so that the conduction band 1
2 in the conduction band 1 transits to the low energy region of the conduction band 1, electrons 4 in the valence band 3 transit to the conduction band 1, and holes 5 are generated in the valence band 3. The electron-hole pair means an electron 4 transited to the conduction band 1 and a hole 5 generated in the valence band 3.

Electrons and holes generated by such impact ionization generate electron-hole pairs, and the generated electron-hole pairs generate further electron-hole pairs. A phenomenon in which a large number of electrons and holes are avalanche is called avalanche phenomenon.

By the way, semiconductor devices have been conventionally provided with MOS.
Of the crystal planes of a silicon single crystal, the interface state density that affects the electrical characteristics of a transistor is the minimum and the electron mobility is the maximum.
The element has been formed on the (100) plane. Also in the silicon (100) plane wafer, as shown in FIG. 6, the channel direction 6 and the orientation flag (hereinafter, referred to as orientation flat) 7 direction are determined to be <011>. This is because, when P-type MOSFETs were the mainstream, the channel direction 6 was aligned with the <011> direction, which maximizes hole mobility, aiming at high-speed signal response. Yes, the orientation of the orientation flat 7 was adjusted to suit it.

Further, in recent years, when miniaturizing MOSFETs, the electric field near the drain becomes extremely high. This high electric field gives high energy to the electrons flowing in the channel and the electrons flowing in the semiconductor substrate.
Of high electron-hole pairs. here,
In the <001> direction, it is known that electrons are most likely to obtain energy and have a high probability of impact ionization due to the nature of the band structure of silicon. For this reason, in the MOSFET formed with the channel in the <001> direction, high-energy hot electrons (electrons) are easily generated due to impact ionization, and they are injected into the gate oxide film beyond the barrier of the insulating film and thus MOSFET. Deteriorate the characteristics of. Due to such a problem, the conventional semiconductor device is <00.
The element has been formed by aligning the channel direction 6 and the orientation flat 7 in the <011> direction without forming a channel in the 1> direction due to the historical circumstances described above.

Next, a description will be given of a conventional nonvolatile memory, which is a MOS type semiconductor device in which a channel is formed in the <011> direction and which uses the avalanche phenomenon due to impact ionization for writing, in an EEPROM. Figure 7 is E
EPROM (Electrically Erasab)
le Programmable Read Qnly
It is sectional drawing which shows the structure of (Memory). In the figure, 8 is a semiconductor substrate (hereinafter referred to as a substrate), 9 is a floating gate made of, for example, polysilicon, 10 is a gate oxide film surrounding the floating gate 9, and 11 is a floating gate. A control gauge made of, for example, polysilicon formed on the gate 9 through a gate oxide film 10.
And 12 are floating gate 9 and gate oxide film 1
It is a gate structure consisting of 0 and control gate 11. 13 is a source region, 14 is a drain region, 15 is a channel region, 16 is a source electrode, 17 is a drain electrode,
Reference numeral 18 is a gate electrode, and 19 is a back gate electrode.

Next, the operation of the EEPROM will be described. When writing information, for example, 2 is applied to the gate electrode 18.
0 V and 40 V are applied to the drain electrode 17. Electron is
From the drain region 14 through the channel region 15 to the drain region 14, but some of those electrons are drain region 1.
A large number of electrons are generated by causing impact ionization at 4 and causing an avalanche phenomenon. Some of these electrons pass through the energy barrier between the substrate 8 and the gate oxide film 10 and are stored in the floating gate 9. Information is written by injecting charges into the floating gate 9.

Information can be erased by, for example, 6
By applying 0V voltage, the floating gate
The electric charge stored in the gate 9 is Fowler-Nord
It is moved to the control gate 11 by the heim tunnel phenomenon.

FIG. 8 shows the energy band operation of writing and erasing information in the EEPROM as described above.
Shown in. FIG. 8A shows an equilibrium state or a state where information is 0 when the flat band voltage is assumed to be 0V.
FIG. 8B shows a written state, in which negative charges are stored in the floating gate 9, which causes the threshold voltage to shift and the information to be 1. Figure 8 (c)
Indicates the erased state. The floating gate 9
The electric charge stored in is transferred to the control gate 11,
The information returns to 0.

Next, the electrical characteristics of the EEPROM will be described. FIG. 9 is a diagram showing the writing characteristics of the EEPROM. As shown in the figure, when a proper drain voltage is applied, the threshold voltage increases as the gate voltage increases. This is because the gate voltage assists in transporting electrons generated by the avalanche phenomenon from the substrate 8 to the floating gate 9. However, when the gate voltage exceeds a certain voltage, the threshold voltage starts decreasing. This is from floating gate 9 to control gate 1
This is because the electrons move to 1 and the accumulated charge decreases.

[0011]

As described above,
Writing information to the EEPROM utilizes impact ionization and an avalanche phenomenon that occurs repeatedly. Therefore, the number of times impact ionization occurs may be increased in order to improve writing efficiency. When the electric field strength increases, the number of high energy electrons increases as shown in FIG. 10, and when the energy of electrons increases, the impact ionization probability increases as shown in FIG. That is, increasing the electric field strength in the channel is effective in increasing the writing efficiency of the EEPROM, but as a method conventionally used, a method of shortening the length of the channel region 15, There are a method of thinning the oxide film 10 and a method of sharply changing the impurity concentration distribution from the channel region 15 to the drain region 14 to increase the electric field gradient near the drain region 14.

However, with the miniaturization, the processing technology such as etching and the transfer technology for patterning are approaching the physical limit as the semiconductor manufacturing technology, and the channel region 1
There is a limit to shortening the length of 5. Also for the gate oxide film 10, it is difficult to form an oxide film thinner than the current film thickness (about 5 nm) from the problems of reliability of the oxide film and controllability of the growth process. Further, the method of adjusting the impurity concentration distribution to increase the electric field gradient in the vicinity of the drain region 14 is also limited due to the problem of controllability of the impurity concentration distribution. <011 on silicon (100) wafer
A conventional EEPROM having a channel formed in the> direction cannot be expected to have high writing efficiency due to various limitations as described above.

The present invention has been made in order to solve the above problems and has improved EE in writing efficiency.
It is an object of the present invention to provide a MOS storage device such as a PROM that electrically writes information using impact ionization.

[0014]

A semiconductor device according to the present invention has a semiconductor substrate made of silicon single crystal, and
A semiconductor device which has a gate region, a drain region, and a gate structure, and writes information by storing charges in the gate structure by using impact ionization, in which the channel direction is the <001> direction of silicon. Is almost the same as.

Further, the semiconductor device according to the present invention is one in which elements are formed on a silicon wafer having orientation flats formed in the <001> direction.

[0016]

In the semiconductor device according to the present invention, the channel direction substantially coincides with the <001> direction of silicon. Here, the <001> direction of silicon is an equivalent direction in the crystal [001], [010], [100].
Represents the azimuth of.

Now, the number of times the impact ionization is caused depending on the traveling direction of electrons in a semiconductor is determined by the Monte Carlo simulator (T. Kunikiyo et al., 1993).
International Workshop
n VLSI Process and Device
Modeling, pp. 40-41, (1993)
(Present at) was calculated as shown in Fig. 4. Figure 4
Is an electric field of 500 kv / cm at time 0 <001>,
It shows the time dependence of the number of times that electrons cause impact ionization after each application in the <111> direction.

As shown in FIG. 4, 0.05 ps to 0.1 ps
At 5 ps (ps: 10 ^-12 seconds), impact ionization is most likely to occur in the <001> direction, and thereafter no significant difference is observed in the three directions. This is 0.05 ps to 0.1
This is because at 5 ps, so-called ballistic travel is performed in which electrons are not scattered so much and travel in the direction of the electric field, and as described above, the impact ionization probability is the largest in the <001> direction. After 0.2 ps, the electrons are scattered and do not necessarily face the electric field direction, so that the anisotropy becomes invisible.

In the present invention, the channel direction of the semiconductor memory device is directed to <001>. Since a large electric field gradient is formed between the drain region and the channel region, electrons rapidly gain energy from the electric field. At this time, the electrons travel ballistically for about 0.2 ps after entering the region having a large electric field gradient. Meanwhile, the impact ionization frequency is directly reflected by the impact ionization probability in the electric field direction. Further, this time is almost the same as the time for the electrons to pass through the edge of the drain region. Therefore, in the channel direction, the impact ionization probability is the highest <0.
01> increases the number of times of impact ionization as compared with the conventional semiconductor memory device, and improves the writing efficiency. In addition, even if the channel direction is deviated from the <001> direction by about ± 10 °, <011> and <111>
Since the influence of the <001> direction is stronger than that of the> direction,
It has the same effect. Therefore, in the present specification, <00
If the deviation from the 1> direction is within 10 °, it is assumed to be substantially the same as the <001> direction.

When elements are formed on a silicon wafer having orientation flats formed in the <001> direction with the channel direction facing <001>, one side of a rectangular chip is parallel to many orientations. Can be formed and is suitable for mass production.

[0021]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. In addition, the points that overlap with the conventional technology are
The description will be omitted as appropriate. FIG. 1 is a first embodiment of the present invention.
3 is a plan view of a (100) plane silicon wafer constituting the semiconductor device according to FIG. As shown in the figure, the orientation of the orientation flat 7 is the silicon wafer 2 formed in <011>.
0, a channel direction 6 is formed toward <001> to form an EEPROM. The structure and basic operation of this EEPROM are the same as those described in the prior art (see FIGS. 7 to 9). In order to increase the electric field gradient near the drain region 14, arsenic is implanted at 4 × 10 ¹⁵ / cm ² at 50 keV by, for example, an ion implantation method to form the drain region 14.

Since the channel region 15 and the drain region 14 are formed of high-concentration impurity layers of different types, a large electric field gradient can usually be formed between the two regions, but especially in a semiconductor device such as an EEPROM, the electric field gradient is large. It is designed to be large, and its appearance is shown in FIG. In the case of writing information, electrons reach the drain region 14 from the source region 13 through the channel region 15. When the electric field sharply changes in the vicinity of the drain region 14, the electrons rapidly gain energy from the electric field. At this time, as described above, the electrons travel ballistically for about 0.2 ps after entering the region with a large electric field gradient, and those with a large energy cause impact ionization, causing the avalanche phenomenon. Among the many electrons generated by this, high energy ones are stored in the floating gate 9 over the energy barrier between the substrate 8 and the gate oxide film 10.

While the electrons travel ballistically,
The impact ionization frequency directly reflects the impact ionization probability in the direction of the electric field. Further, this time substantially coincides with the time for which the electrons pass through the edge of the drain region 14.
Channel direction 6 has the highest impact ionization probability <
001> direction, the channel direction 6 is <011>
Direction, the number of times of impact ionization is increased, and the writing efficiency of the EEPROM is improved.

If the channel direction 6 is within ± 10 ° of the <001> direction, the other <011> and <011>
Since the influence of the <001> direction is stronger than that of the 111> direction, the same effect can be obtained.

Further, although the EEPROM has been described as an example in the above embodiment, the present invention is not limited to this as long as it is a MOS type memory device which writes information by using impact ionization.

Example 2. Next, a semiconductor device according to a second embodiment of the present invention will be described. FIG. 3 is a plan view of a (100) plane silicon wafer constituting a semiconductor device according to a second embodiment of the present invention as seen from above. As shown in the figure, the orientation of the orientation flat 7 is the silicon wafer 2 formed in <001>.
0, a channel direction 6 is formed toward <001> to form an EEPROM. As a result, one side of the rectangular chip 21 and the orientation flat are parallel to each other so that many chips can be formed, which is suitable for mass production, and the conventional semiconductor device in which both the orientation flat 7 and the channel direction 6 are <011>. The mask can be used as it is in the manufacturing process, which facilitates manufacturing.

[0027]

As described above, according to the present invention, in the semiconductor memory device in which information is written by using impact ionization, the channel direction coincides with the <001> direction, or substantially coincides with a width of ± 10 °. Since it was configured to
The number of times impact ionization occurs is increased and the writing efficiency is improved. Also, by setting the orientation of the orientation flat to be the <001> direction, it is possible to easily form a semiconductor memory device suitable for mass production.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the electric field strength of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a difference in impact ionization frequency due to a difference in traveling direction of electrons.

FIG. 5 is an energy band diagram for explaining impact ionization.

FIG. 6 is a plan view showing a conventional semiconductor device.

FIG. 7 is a cross-sectional view showing the structure of the EEPROM.

FIG. 8 is an energy band diagram for explaining the operation of the EEPROM.

FIG. 9 is a diagram showing write characteristics of an EEPROM.

FIG. 10 is a diagram showing an energy distribution of electrons according to electric field strength.

FIG. 11 is a diagram showing impact ionization probability due to electron energy.

[Explanation of symbols]

 6 Channel direction 7 Orientation flag 8 Semiconductor substrate 12 Gate structure 13 Source region 14 Drain region 15 Channel region 20 Silicon wafer

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[Procedure amendment]

[Submission date] October 29, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

By the way, semiconductor devices have been conventionally provided with MOS.
Of the crystal planes of a silicon single crystal, the interface state density that affects the electrical characteristics of a transistor is the minimum and the electron mobility is the maximum.
The element has been formed on the (100) plane. Also in the silicon (100) plane wafer, as shown in FIG. 6, the channel direction 6 and the orientation flag (hereinafter, referred to as orientation flat) 7 direction are determined to be <011>. This will set the orientation flap in the <011> direction.
Then, the cleavage plane is almost perpendicular to the (100) plane.
It is suitable for mass production because it is easy to handle mechanically because it comes out.
Similarly, the channel direction 6 was adapted to it.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

Further, in recent years, when miniaturizing MOSFETs, the electric field near the drain becomes extremely high. This high electric field gives high energy to the electrons flowing in the channel and the electrons flowing in the semiconductor substrate.
Of high electron-hole pairs. here,
In the <001> direction, it is known that electrons are most likely to obtain energy and have a high probability of impact ionization due to the nature of the band structure of silicon. For this reason, in the MOSFET formed with the channel in the <001> direction, high-energy hot electrons (electrons) are easily generated due to impact ionization, and they are injected into the gate oxide film beyond the barrier of the insulating film and thus MOSFET. Deteriorate the characteristics of. Due to such a problem, the conventional semiconductor device is <00.
1> without forming a channel in the direction, as described above
The device was formed by aligning the channel direction 6 and the orientation flat 7 with the <011> direction.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

[0014]

SUMMARY OF THE INVENTION The semiconductor device according to the invention, on a semi-conductor substrate, source - source region and the drain region and the gate - has the door structure, the gate charge with impact ionization - DOO A semiconductor device in which information is written by storing it in a structure, and the channel direction thereof is substantially the same as the <001> direction of a semiconductor crystal .

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

Further, the semiconductor device according to the present invention is one in which elements are formed on a semiconductor substrate in which an orientation flat is formed in the <001> direction.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

[0016]

In the semiconductor device according to the present invention, the channel direction is substantially aligned with the <001> direction of the semiconductor crystal . Here, the <001> direction of a semiconductor crystal is an equivalent direction in the crystal [001], [010], [10].
[0] is representatively represented.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

When an element is formed on a semiconductor substrate in which the orientation flat is formed in the <001> direction with the channel direction facing <001>, one side of the rectangular chip and the orientation flat are in parallel with each other. Chips can be formed and are suitable for mass production.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

[0021]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. In addition, the points that overlap with the conventional technology are
The description will be omitted as appropriate. FIG. 1 is a first embodiment of the present invention.
3 is a plan view of a (100) plane silicon wafer constituting the semiconductor device according to FIG. As a semiconductor substrate in which the orientation flat 7 is oriented <011> as shown in the figure
Channel direction 6 <001 on the silicon wafer 20 of
And an EEPROM formed toward>. This E
The structure and basic operation of the EPROM are the same as those described in the prior art (see FIGS. 7 to 9). In order to increase the electric field gradient in the vicinity of the drain region 14, arsenic is added at 4 × 10 ¹⁵ / cm ² at 50 keV by, for example, an ion implantation method.
Implantation is performed to form the drain region 14.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

If the channel direction 6 is within ± 10 ° of the <001> direction, the other <011> and <011>
Since the influence of the <001> direction is stronger than that of the 111> direction, the same effect can be obtained. Also, in the above embodiment,
A semiconductor substrate 8 made of gallium arsenide or the like,
Even if 20 is used, the same effect can be obtained.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Reference Signs] 6 Channel direction 7 Orientation flag 8 Semiconductor substrate 12 Gate structure 13 Source region 14 Drain region 15 Channel region 20 Silicon wafer as semiconductor substrate

Claims (2)

[Claims] 1. Writing information by having a source region, a drain region and a gate structure on a semiconductor substrate made of silicon single crystal, and storing charges in the gate structure by using impact ionization. In the semiconductor memory device for performing the above, the direction of the line connecting the source region and the drain region at the shortest distance (hereinafter referred to as the channel direction) is substantially the same as the <001> direction of silicon. Semiconductor device. 2. The orientation flag is <001>.
2. The semiconductor device according to claim 1, wherein elements are formed on a silicon wafer formed in the direction.