WO2009081290A1

WO2009081290A1 - A memory cell, a memory array and a method of programming a memory cell

Info

Publication number: WO2009081290A1
Application number: PCT/IB2008/053444
Authority: WO
Inventors: Nader Akil; Michiel Van Duuren
Original assignee: Nxp B.V.
Priority date: 2007-12-20
Filing date: 2008-08-27
Publication date: 2009-07-02

Abstract

A method of programming a charge-trapping memory transistor (100) is disclosed. The transistor enters a first logical state by applying a first potential to the drain (107) and a second potential to the control gate (102). This causes injection of channel hot carriers of a first conductivity type. In an n-channel transistor, the potentials are positive and the transistor attains a high threshold voltage by hot electron injection. The transistor enters a second logical state by applying a fourth potential to the drain and a fifth potential of opposite polarity to the control gate. This causes charge carrier injection into the trapping structure. In an n-channel transistor, the fourth potential is positive, the fifth negative and the transistor resumes a low threshold voltage by hot hole injection.

Description

A memory cell, a memory array and a method of programming a memory cell

FIELD OF THE INVENTION The invention relates to a memory cell.

Moreover, the invention relates to a memory array.

Beyond this, the invention relates to a method of programming a memory cell.

BACKGROUND OF THE INVENTION The storage of information on computer systems and in embedded chips for smartcards, etc. becomes more and more important. Particularly, flash memory arrays may be employed for this purpose.

SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) and charge trapping memories in general (for instance nanocrystals, SONOS with one or more layers made of a high k-material, etc.) are serious candidates for embedded and stand alone nonvolatile memories in the 45 nm CMOS generation and beyond, thanks to the ease of integration in the CMOS flow.

Erase of memory cells is performed conventionally by Fowler-Nordheim procedures, which involves high voltage values, for instance 12 V. This may involve the danger of deteriorating or even destroying sensitive integrated circuit members. Alternatively, high efforts are required during manufacture of a memory cell to provide protection structures for protecting sensitive integrated circuit members from being negatively influenced by high voltages. This is cumbersome and expensive. Furthermore, erase on the basis of Fowler- Nordheim procedures is relatively slow.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to provide a memory, which can be programmed efficiently.

In order to achieve the object defined above, a memory cell, a memory array, and a method of controlling a memory cell according to the independent claims are provided.

According to an exemplary embodiment of the invention, a method of controlling (for instance for programming or erasing) a memory cell to selectively assume (that is to be selectively brought to) a first logical state (for instance characterized by a first threshold voltage value of a memory transistor identified with a first logical value "1" or "0") or a second logical state (for instance characterized by a second threshold voltage value differing from the first threshold voltage value of the memory transistor identified with a second logical value "0" or "1" being inverse to the first logical value) is provided, the method comprising controlling the memory cell to assume the first logical state by applying a first electric potential to a first electric terminal of the memory cell to accelerate first charge carriers of a first type of conductivity (for instance electrons) and by applying a second electric potential to a second electric terminal of the memory cell to further accelerate the accelerated first charge carriers to thereby inject the first charge carriers in a charge trapping structure of the memory cell by channel hot carrier injection (for instance by channel hot electron injection), and controlling the memory cell to assume the second logical state by applying a fourth electric potential to the first electric terminal of the memory cell to accelerate second charge carriers of a second type of conductivity (for instance electrons) to thereby generate third charge carriers of a third type of conductivity (for instance holes) by impact ionisation of the accelerated second charge carriers and by applying a fifth electric potential to the second electric terminal of the memory cell to accelerate the third charge carriers to thereby inject the third charge carriers in the charge trapping structure of the memory cell.

According to another exemplary embodiment of the invention, a memory cell for storing information by selectively assuming a first logical state or a second logical state is provided, the memory cell comprising a first electric terminal, a second electric terminal, a charge trapping structure, and a programming unit adapted for controlling the memory cell to assume the first logical state by applying a first electric potential to the first electric terminal of the memory cell to accelerate first charge carriers of a first type of conductivity and by applying a second electric potential to the second electric terminal of the memory cell to further accelerate the accelerated first charge carriers to thereby inject the first charge carriers in the charge trapping structure of the memory cell by channel hot carrier injection, wherein the programming unit is further adapted for controlling the memory cell to assume the second logical state by applying a fourth electric potential to the first electric terminal of the memory cell to accelerate second charge carriers of a second type of conductivity to thereby generate third charge carriers of a third type of conductivity by impact ionisation of the accelerated second charge carriers and by applying a fifth electric potential to the second electric terminal of the memory cell to accelerate the third charge carriers to thereby inject the third charge carriers in the charge trapping structure of the memory cell. According to another exemplary embodiment of the invention, a memory array is provided, the memory array comprising a plurality of memory cells having the above mentioned features and formed in a (common) substrate. Such a memory array may comprise a plurality of matrix- like arranged memory cells which may be controlled individually using word lines and bit lines.

The term "memory cell" may particularly denote a physical structure (such as a layer sequence) which allows storing information in an electronic manner. An amount of information stored in a memory cell may be one (1) bit (which may be encoded, for instance, in the presence or absence of charge carriers in a dedicated structure, or in a "high" or a "low" value of a threshold voltage of a storage transistor) or may be more than one (1) bit (which may be encoded, for instance, in the amount of stored charge and/or the type of the charge carriers, that is to say positively or negatively charged charge carriers).

The term "substrate" may denote any suitable material, such as a semiconductor, glass, plastic, etc. According to an exemplary embodiment, the term "substrate" may be used to define generally the elements for layers that underlie and/or overlie a layer or portions of interest. Also, the substrate may be any other base on which a layer is formed, for example a semiconductor wafer such as a silicon wafer or silicon chip. However, a substrate may also have an electrical function, in the context of the generations of electrons or holes. The term "charge storage structure" or "charge trapping structure" may particularly denote a structure that is specifically adapted to allow introducing electric charge in this structure by tunneling or other motion schemes. The charge storage structure may be adapted in a manner that this charge is stored and remains stored within the structure for a sufficiently long time. Examples for appropriate charge storage structures are a nitride layer of an ONO layer sequence, nanocrystals, etc. Also electrically conductive charge storage structures such as a floating gate may fall under the scope of embodiments of the invention. The term "source/drain region" may particularly denote a source region or a drain region. Since the functionality of a source region and a drain region may depend on the operation mode of a memory transistor, for instance voltages applied thereto, the term source/drain region may denote a structure which can act as a source region or as a drain region.

The term "programming" may particularly denote selectively injecting charge carriers in a charge trapping structure in a manner to allow the memory cell in the programmed state to store the information of at least one bit. In other words, after programming, the information is stored in a readable manner in the charge trapping structure. Programming may be a procedure, which is performed individually for each memory cell of a memory array. The term "erasing" may particularly denote a procedure, which may be performed individually or in common for a plurality of memory cells at the same time and which removes any information stored in the memory cells. After an erasing procedure, a memory cell is reset in a state in which it does not include stored information and is ready for a new programming procedure. The term "charge carriers" may particularly denote electrically positively charged particles or quasi-particles in a solid substrate (such as holes) or electrically negatively charged particles (such as electrons).

The term "type of conductivity" may denote that positive or negative mobile charge carriers carry current. One type of conductivity is therefore a current carried by positively charged charge carriers; another type of conductivity is therefore a current carried by negatively charged charge carriers.

The term "channel hot carrier injection" may particularly denote a process by which hot charge carriers (such as electrons or holes) are accelerated for instance between two source/drain regions or in a channel region and are then injected into a charge storage structure by applying an appropriate voltage to a gate. When the hot charge carriers are electrons, the procedure may be denoted as "channel hot electron injection". When the hot charge carriers are holes, the procedure may be denoted as "channel hot hole injection". The term "impact ionisation" may particularly denote a phenomenon that accelerated charge carriers (particularly electrons) having sufficient energy may interact with the material of a substrate (for instance a silicon substrate such as a wafer or an electronic chip) so that electron-hole pairs are generated. Depending on the voltage applied to the second electric terminal, one charge type of the generated pairs (for instance holes) can be accelerated towards a charge trapping structure and may be accumulated in the charge trapping structure. According to an exemplary embodiment of the invention, channel hot carrier injection (particularly channel hot electron injection) may be used as a programming (or erase) mechanism for programming information in (or erasing information from) one or a plurality of memory cells of the type having a charge trapping structure between gate and channel, wherein the presence or absence of charge carriers in the charge trapping structure or the polarity of charge carriers in the charge trapping structure has an influence on the conductivity characteristic of the channel region of the memory cell, thereby encoding stored information of one or more bits. According to an exemplary embodiment, a memory cell is thus programmed by accelerating charge carriers between two source/drain regions by applying appropriate electric potentials to or a voltage between the source/drain regions. This accelerates charge carriers such as electrons along the channel. Simultaneously, a further electric potential may be applied to the gate so that the charge carriers accelerated for instance in a direction along the channel may be deflected towards the gate under the influence of a further electric force, thereby having the possibility to traverse a gate insulation layer and be injected and trapped in a charge trapping structure. By performing such a procedure in one, several or all memory cells of a memory array, the memory cell(s) may be brought to a defined state. Hence, one state of a memory cell may be defined by channel hot carrier injection, which can be performed using moderate electric potentials. According to an exemplary embodiment of the invention, such a channel hot carrier injection programming procedure may be combined synergistically with a programming scheme that is based on impact ionization, which can also be performed using moderate electric potentials.

For programming based on impact ionisation, primary charge carriers (for instance electrons) may be accelerated by applying an electric potential to a dedicated terminal, particularly between two source/drain regions of a memory transistor. When a further electrical potential of appropriate polarity is then applied to another dedicated terminal, particularly the gate terminal of the memory transistor, secondary charge carriers (for instance holes) generated by impact ionisation may tunnel even through a relatively thick gate insulating layer into a charge trapping structure such as a silicon nitride layer of an ONO

(silicon oxide-silicon nitride-silicon oxide) layer sequence. Information to be stored in such a memory cell may be encoded in the presence or absence, in the amount and/or in the charge type of the electrically charged particles trapped in the charge-trapping layer.

By programming a memory cell by channel hot electron injection to assume a first threshold voltage which differs from a second threshold voltage adjustable by impact ionisation, clearly distinguishable states of the memory cell may be set with relatively small electric potentials (for instance not exceeding about 5 V), thereby preventing a memory cell from being damaged by high voltages, and making high voltage protection measures dispensable. Thus, a corresponding memory cell or memory array may be manufactured with low cost.

Programmed information can be read out by applying a sampling voltage to the memory transistor (and/or by applying a sampling voltage to an access transistor), and the amount of the flowing current (between source and drain) then depends on the previous programming scheme. Since the hot hole injection procedure triggered by impact ionisation as well as the channel hot electron injection procedure allows the use of a thick gate insulating layer of the memory transistor, the data retention time may be significantly increased using embodiments of the invention. According to an exemplary embodiment of the invention, channel hot electrons injection (CHEI) may be combined with punch-through assisted hot holes (PAHH) injection for ultra-low cost multi-time programmable non-volatile memories. Such an architecture may allow to obtain a programming scheme for thick bottom oxide SONOS, wherein the programming may be done with hot holes generated with low voltages (~5 V), while erasing does not require conventional high voltage Fowler Nordheim injection (-+12V). According to an exemplary embodiment of the invention, both program and erase mechanisms may be done with low voltages (~5 V) to avoid high voltage processing to save masks and enable ultra-low cost embedded non- volatile memory in advanced CMOS generations.

According to an exemplary embodiment of the invention, it is possible to combine a low voltage PAHH mechanism which may bring the threshold voltage V_T of a memory cell to a low state with another low voltage mechanism that may bring the threshold voltage V_T of a memory cell to a high state in order to perform both program and erase operations with low voltages (~5V). Channel hot electron injection (CHEI) can be operated with low drain and gate voltages (~5V) and when combined with PAHH, there is no need for high voltage protection processing which may save masks. The potential of 5 V can also be handled with transistors having the so termed "GO2" oxides (~5nm in cmos45nm). Those transistors are able to handle the 5 V for a sufficiently long time of at least few seconds or minutes. Since PAHH and CHEI are fast programming mechanisms (~10-100μs), multi-time program actions can be done before the breakdown of the GO2 oxide. According to an exemplary embodiment of the invention, a method to program and erase a non- volatile memory device is provided, wherein the program and erase method is suitable for SONOS devices, preferably with thick tunnel oxide, to improve the retention, but it may be used for any other non-volatile memories like floating gate, nano-crystal, or any other charge trapping memories. The lowering of the threshold voltage V_T of the memory may be done with a PAHH mechanism, and the threshold voltage V_T of the memory may be increased by using a CHEI mechanism. Since the program and erase method according to an exemplary embodiment does not require high voltages, no special high voltage process is needed anymore and the memory can be embedded in CMOS baseline with minimum amount of masks and process steps to enable ultra low cost multi-time programmable embedded non volatile memories. A preferred embodiment may use 2T SONOS in NOR architecture with the program and erase method described above. However, all IT or 2T cell architectures can be used with the described program/erase method. Such a method can be used as well for any other memory architecture (for instance AND, etc.).

Next, further exemplary embodiments of the method will be explained. However, these embodiments also apply to the memory cell and to the memory array.

During the method of programming a memory cell, a polarity of the first potential may be identical to a polarity of the second electric potential. This may allow attracting the charge carriers having a certain type of conductivity by the first electric terminal and by the second electric terminal simultaneously. When the electrons travel towards the first electric terminal, they may be deflected perpendicular to this propagation direction by the attracting potential of the second electric terminal thereby defining a trajectory of the charge carriers. The first electric terminal may be a first source/drain region, particularly may be a drain region, of a memory transistor of the memory cell. Such a memory transistor may be a field effect transistor having two source/drain regions, a channel region between the two source/drain regions and a gate region which is separated from the channel region by a gate insulating layer and the charge trapping layer. The second electric terminal may be a gate region of the memory transistor of the memory cell. Therefore, the gate may be biased to provide an attracting electric force for the accelerated charge carriers.

According to an exemplary embodiment, the charge carriers used for activating the first logical state are negatively charged particles, particularly are electrons so that the memory cell is programmed by channel hot electron injection (CHE). When the charge carriers are positively charged particles, particularly are holes, the memory cell may be programmed by channel hot hole injection.

The first electric potential may be a positive electric potential, particularly may be a positive electric potential having an absolute value in a range between 2 V and 6 V, more particularly of less than or equal to 5 V. Thus, by using the channel hot carrier injection method for programming (or erasing), the required potentials may be significantly reduced as comparison to a conventional Fowler-Nordheim procedure, thereby protecting the sensitive integrated circuit members of a memory product. Furthermore, any protection measures for the transistor or circuit components may be omitted, when only such moderate voltages are used for programming.

The second electric potential may be a positive electric potential, particularly may be a positive electric potential having an absolute value in a range between 3 V and 10 V, more particularly may be a positive electric potential having an absolute value of less than or equal to 5 V. Therefore, not only the voltage between source and drains may be moderate, but also the biasing voltage of the control gate, further contributing to a simple construction of the transistor, since any protection mechanisms or measures to protect the transistor circuit against high potentials may be omitted. The second electric potential may be applied in such a manner that the charge carriers, particularly the electrons, are injected in the charge trapping structure after tunnelling through an electrically insulating structure of the memory cell. Thus, the accelerated electrons may traverse the gate dielectric by tunnelling.

The electrically insulating structure (which may be denoted as a gate insulating structure in a configuration using a memory transistor) of the memory cell may have a thickness between 3 nm and 8 nm for silicon dioxide (the thickness can be different for other materials such as high k materials: here, the thickness may be even larger to obtain the same "electrical thickness"). By having a thickness of at least 3 nm, the retention time of the memory cell may be kept high so that information can be stored reliably for a long time in the memory cell.

During the method, it is possible to apply a third electric potential to a third electric terminal of the memory cell to accelerate the charge carriers between the first electric terminal and the third electric terminal. The third electric terminal may be a second source/drain region, particularly a source region. The third electric potential may be about 0 V or may be a floating potential.

The first logic state may correspond to a first value of the threshold voltage V_T of a memory transistor of the memory cell and the second logic state may correspond to a second value of the threshold voltage V_T of the memory transistor of the memory cell, wherein the first threshold voltage may be higher than the second threshold voltage. The first threshold voltage may have a positive polarity, whereas the second threshold voltage may have a negative polarity (see Fig. 7 and Fig 8).

It goes without saying that the applied first and second electric potentials may be switched off when the fourth and fifth electric potentials are applied to the corresponding terminals.

For activating the second logic state, a voltage may be applied between the first terminal assigned to the drain region, and the source region may be kept, for instance, at a reference potential such as the ground potential. Then, the electrons as the second charge carriers may flow between the source and the drain region and may be accelerated rapidly by the applied electric voltage. Being heavily accelerated, energy of these electrons may be transferred to a material of the substrate to thereby generate electron-hole pairs. The holes of these pairs may then be attracted by a voltage applied to the gate of the memory transistor as the second electric terminal, thereby allowing the hot holes to transmit even a thick electrically insulating barrier, to enter the oxide and to be trapped in the charge storage structure, for instance a silicon nitride layer of an ONO layer sequence.

The second charge carriers may be negatively charged particles such as electrons and the third charge carriers may be positively charged particles such as holes in a solid-state substrate. The forth electric potential may be a positive electric potential (with respect to a ground potential), particularly may be a positive electric potential having an absolute value of less than or equal to 5 V. Thus, a relatively moderate voltage may be sufficient to accelerate the electrons in a sufficient manner to provide for impact ionisation.

The fifth electric potential may be a negative electric potential (with respect to a ground potential), particularly may be a negative electric potential having an absolute value of less than or equal to 5 V. The negative electric potential may be applied to attract and accumulate positively charged particles such as hot holes in the charge trapping layer. Therefore, a relatively low energy programming may be made possible.

The fifth electric potential may be applied in such a manner that the third charge carriers are injected in the charge trapping structure after tunneling through an electrically insulating structure of the memory cell. Such a tunneling may involve hot hole injection as an efficient programming procedure.

The charge trapping structure may be made of an electrically insulating material such as a silicon nitride layer, a silicon nitride layer of an ONO (silicon oxide-silicon nitride- silicon oxide) layer sequence, an ONO layer sequence comprising a high-k material, or a nanocrystal structure. The charge trapping structure may also be made of an electrically conductive material such as a floating gate. A floating gate may be an electrically conductive polysilicon structure surrounded by an electrical insulation, wherein the charges are trapped within the floating gate.

The method may comprise operating an additional access transistor of the memory cell as a current limiting element for programming the memory cell, particularly for limiting a value of an electric current flowing through a memory transistor of the memory cell. Thus, the access transistor may be operated in a manner to limit the amplitudes of the electric signals to which the memory transistor is exposed. This may allow to obtain definable parameters for programming the memory cell, allowing for reducible programming results.

The memory cell may be a non-volatile memory cell. In other words, the memory cell may be a memory cell, which is capable of storing information for a sufficiently long time of days or years without the need for a constant supply of electric energy to maintain the information stored.

The method may comprise applying a sixth electric potential to a third electric terminal of the memory cell to assist acceleration of the second charge carriers between the first electric terminal and the third electric terminal (for instance for an acceleration in a channel region). Thus, a current flow of accelerated electrons may be accomplished between a source region and a drain region, to induce electron-hole pairs in the channel deeply buried within the substrate, and the holes may then be "sucked off' in an electric manner by the attracting potential applied to the gate terminal. This allows for a very efficient programming scheme. It is recalled that the third electric terminal may be a second source/drain region, particularly a source region, of the memory transistor of the memory cell.

When a length of a gate stack of a memory transistor of a memory cell is sufficiently small, for instance less or equal to 150 nm, the quality of the programming procedure remains high, and a high integration density may be made possible. When CHEI is used (localized injection into the nitride), it is presently believed that the holes generated with PAHHI are not injected uniformly into the nitride but more towards the highest gate field region which is the position of the region filled with electrons.

Furthermore, the memory cell may be erased by (for instance after a previous programming sequence) applying appropriate potentials to the electric terminals of the memory cell.

A plurality of memory cells of a memory array may be programmed or erased simultaneously which may allow for a fast and efficient operation.

A memory transistor of the memory cell may be a punching transistor, which allows to use a punching effect for programming. Such a punching transistor may have a conductive channel region even in the absence of an externally applied gate voltage.

For any method step during manufacture of a (monolithically integrated) memory cell according to an exemplary embodiment of the invention, any conventional procedure as known from semiconductor technology may be implemented. Forming layers or components may include deposition techniques such as CVD (chemical vapour deposition), PECVD (plasma enhanced chemical vapour deposition), ALD (atomic layer deposition), or sputtering. Removing layers or components may include etching techniques such as wet etching, vapour etching, etc., as well as patterning techniques such as optical lithography, UV lithography, electron beam lithography, etc. Embodiments of the invention are not bound to specific materials, so that many different materials may be used. For conductive structures, it may be possible to use metallization structures, suicide structures or polysilicon structures. For semiconductor regions or components, crystalline silicon may be used. For insulating portions, silicon oxide or silicon nitride may be used. The structure may be formed on and/or in a purely crystalline silicon wafer or on and/or in an SOI wafer (Silicon On Insulator).

Any process technologies like CMOS, BIPOLAR, BICMOS may be implemented.

The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail hereinafter with reference to examples of embodiment but to which the invention is not limited.

Fig. 1 illustrates a memory cell according to an exemplary embodiment of the invention.

Fig. 2 illustrates a memory cell according to an exemplary embodiment of the invention during a first programming procedure.

Fig. 3 illustrates the memory cell of Fig. 2 during a second programming procedure.

Fig. 4 illustrates program (PAHH) and erase (FN) curves (average V_T of 128 bits) for a 4 nm tunnel oxide memory cell, wherein all program curves start at V_T = 2.7 V, and all erase curves start at V_T = -3 V.

Fig. 5 and Fig. 6 show a schematic diagram of a 2T SONOS NOR array configuration, and a two-dimensional cross-section of a 2T SONOS memory cell operated according to an exemplary embodiment of the invention. Fig. 7 illustrates program and erase curves of SONOS mini arrays (128 bits) with 6/6/6 nm ONO according to an exemplary embodiment of the invention, wherein CHEI is used to bring the threshold voltage V_T to the high state and PAHH is used to bring the threshold voltage V_T to the low state, wherein the starting of V_T of the CHEI curve is -1.3 V, and for the PAHH curve is +6.4 V. Fig. 8 shows the endurance of a 2T SONOS mini array (128 bits) with 6/6/6 nm ONO according to an exemplary embodiment of the invention using CHEI to bring the V_T to the high state and PAHH to bring the V_T to the low state, wherein the cell dimensions are LcG = 100 nm, and L_AG = 260 nm and W = 120 nm.

DESCRIPTION OF EMBODIMENTS

The illustration in the drawing is schematical. In different drawings, similar or identical elements are provided with the same reference signs.

In the following, referring to Fig. 1, a memory cell 100 according to an exemplary embodiment of the invention will be explained. The memory cell 100 comprises a first electric terminal 101 serving as a first source/drain terminal or source terminal, a second electrical terminal 102 serving as a gate terminal, a third electric terminal 107 serving as a second source/drain terminal or drain terminal, a charge trapping structure 103 configured as a silicon nitride layer and a control unit 104 programmed for or capable of controlling both an erasure procedure and a programming procedure. The control unit 104 may be a monolithically integrated circuit or may be a voltage control device provided externally of a silicon substrate 105 of the memory cell.

For forming the memory device 100, a first source/drain region 111 is implanted in the silicon substrate 105 and is electrically coupled to the source terminal 101, and a second source/drain region 112 is implanted in the silicon substrate 105 and is electrically coupled to the drain terminal 107, wherein the first source/drain region 111 and the second source/drain region 112 are formed as doped regions. For example, the channel 113 of the field effect transistor 110 may be an p-type channel, whereas the source/drain regions 111, 112 may be n-doped regions. A gate stack 120 is provided comprising the silicon oxide layer 106, the silicon nitride layer 103, an electrically insulating layer 114 and the gate layer 115. A length "L" of the gate stack 120 may be less than or equal to 150 nm.

Next, it will be explained how the control unit 104 may program information in the memory cell 100 by performing a defined channel hot electron injection procedure. With such a procedure (which may also be applied simultaneously to some or all memory cells of a memory array), a defined first logical state may be assumed by the memory cell 100, so that after the programming procedure the programmed memory cell 100 enduringly or permanently remains in this first logical state. Thus, when sampling the memory content by applying a read voltage to the gate terminal 102 and a test voltage between the source/drain terminals 101, 107, a current value between the source/drain terminals 101, 107 is indicative of the first logical state which may be identified as a value "1".

For programming the memory 100 to assume the first logical state, the control unit 104 is adapted for applying a first electric potential to the drain terminal 107 to accelerate electrons in a channel region 113 to thereby generate negatively charged accelerated electrons in the substrate 105. The control unit 104 is further adapted for simultaneously applying a second electric potential to the gate terminal 102 to attract the accelerated electrons towards the gate terminal 102 to thereby inject the electrons in the charge trapping structure 103 after transmission through a gate insulating layer 106. Instead of simultaneously applying the above potentials, it is possible that the gate and drain are not applied simultaneously but with a certain shift in the pulse duration, like first generate the inversion region (electrons in the channel) by rising the gate voltage, and then start to accelerate the electrons by rising the drain voltage.

For instance, the first electric potential may be +5V. The second electric potential may be +5V as well. By applying these voltages, the accelerated electrons may be injected in the charge trapping structure 103 after tunnelling through the gate oxide layer 106 made of silicon oxide material. The thickness "d" of the gate oxide layer 106 may be more than 3 nm, for instance may be 5 nm, according to the described embodiment.

During this programming procedure, a third electric potential may be applied to the source terminal 101 of the memory cell 100 to accelerate the electrons between the two source/drain terminals 101 and 107.

For programming the memory cell 100 to bring it into a second logical state (which is complementary or inverse to the first logical value), the control unit 104 is adapted for applying a forth electric potential to the drain terminal 107 to accelerate electrons in the channel region 113 to thereby generate positively charged holes by impact ionisation of the accelerated electrons in the substrate 105. The control unit 104 is further adapted for (simultaneously or subsequently) applying a fifth electric potential to the gate terminal 102 to accelerate the generated holes to thereby inject the positively charged holes in the charge trapping structure 103 after transmission through the gate insulating layer 106.

For instance, the forth electric potential may be +5V. The fifth electric potential may be -5V. By applying these voltages, the generated hot holes may be injected in the charge trapping structure 103 after tunnelling through the gate oxide layer 106. For programming, a sixth electric potential may be applied to a source terminal 101 to accelerate the electrons between the two source/drain terminals 101 and 107.

As a consequence of the described impact ionisation procedure for inserting holes in the charge trapping structure 103, a defined second logical state may be assumed by the memory cell 100, so that after the programming procedure the programmed memory cell 100 enduringly or permanently remains in this second logical state. Thus, when sampling the memory content by applying a read voltage to the gate terminal 102 and a test voltage between the source/drain terminals 101, 107, a current value between the source/drain terminals 101, 107 is indicative of the second logical state which may be identified as a value "0".

Fig. 2 and Fig. 3 show a memory cell 200 according to an exemplary embodiment of the invention which has a similar construction as the memory cell 100 described above referring to Fig. 1.

In the configuration of Fig. 2, the first source/drain region 111 is brought to a potential of 0 V and the second source/drain region 112 is brought to a potential of +5 V. Consequently, electrons 202 close to the first source/drain region 111 are accelerated under the attracting electric force of the potential of +5 V applied to the second source/drain region 112 so that the electrons 202 are forced to follow a trajectory 204. Apart from the attracting force of the second source/drain terminal 112, the electron 202 is also influenced by the attracting positive potential applied to the control gate 115. Therefore, the trajectory of the electron 202 when moving along the channel 113 is curved upwardly and the accelerated electron 202 may traverse the gate insulating layer 106 and may be trapped in the charge trapping layer 103 so that negative charge is accumulated there. When performing the procedure of channel hot electron injection as shown in Fig. 2, the charge trapping layer 103 may be brought to a defined negative electrical potential.

By taking such a procedure, the threshold voltage V_T of all memory cells 200 programmed with such a procedure are brought to the same value, thereby enduring an efficient and non volatile storage of information.

Another programming mechanism according to an exemplary embodiment of the invention involves hot holes generated by impact ionisation events of electrons flowing from the source to the drain (or in opposite direction) deep below the interface as shown in Fig. 3.

Fig. 3 therefore illustrates the memory cell 200 which schematically shows hot holes 301 generated by impact ionisation (schematically illustrated with reference numeral 302) of an electron 303 propagating from source 111 to drain 112 deep below the interface of the punching SONOS transistors 200. The programming scheme illustrated schematically in Fig. 3 can be achieved when a punching control gate 115 device at high drain 111 to source 112 voltage (Va_s) is used.

Summarizing, the programming scheme illustrated in Fig. 2 may be applied to store an information identified with a logical value of "1", and the programming scheme illustrated in Fig. 3 may be applied to store an information identified with a logical value of "0", or vice versa.

In Fig. 2, the electrons 202 to be accelerated from the source 111 are closer to the surface compared to the electrons 303 to be accelerated in Fig. 3, because they are attracted by the positive gate voltage in Fig. 2. Electrons 303 will flow deep below the surface due to the presence of a negative gate voltage.

In the following, some further recognitions of the present inventors will be summarized based on which exemplary embodiments of the invention have been developed. A programming mechanism called punch-through assisted hot holes (PAHH) injection may be used to program a thick bottom oxide SONOS. The programming with

PAHH (as illustrated in Fig. 3) may be done to bring the threshold voltage V_T of the SONOS to a low state in a selective way. The gate and drain voltages used in PAHH may be in the order of 5 V. Erasing may be conventionally done in a non-selective way by Fowler Nordheim electron injection to bring the threshold voltage V_T of all cells to the high state (see Fig. 4).

Fig. 4 illustrates a diagram 400 having an abscissa 402 along which a time is plotted. Along an ordinate 404, a threshold voltage V_T is plotted in Volt. Fig. 4 illustrates programming by PAHH, and erasure by Fowler Nordheim tunnelling, that is to say a conventional erasure approach.

For erasing in accordance with Fig. 4, a high positive voltage (-+12V) is needed to have Fowler Nordheim electron injection. Although PAHH requires only 5V to program thick bottom oxide SONOS, it is still necessary to generate and to handle the high erase voltage (+12V). Therefore, a high voltage (HV) process is still needed (~3 to 5 extra masks on top of the CMOS process). For ultra low cost MTP, this is not acceptable and the number of masks should be reduced to the strict minimum.

In view of these considerations, exemplary embodiments of the invention operate a memory without the need of high voltage processing to reduce the cost. Also, a fast erasing mechanism (Fowler Nordheim is rather slow -100ms) is provided which is needed especially for EEPROM applications where the memory is not erased by sector, like in flash memories, but by bit or page.

According to an exemplary embodiment of the invention, PAHH may be used for a 2T SONOS where an access gate (AG) transistor is present next to every SONOS transistor (see Fig. 5 and Fig. 6). Fig. 5 schematically illustrates the layout of a matrix-like arrangement of memory cells 600 as shown in Fig. 6, each having an access transistor 610 as well as a storage transistor 620. The access transistor 610 is an oxide transistor, whereas the storage transistor 620 is a SONOS or ONO transistor.

For the construction of the two transistors 610, 620, reference is made to Fig. 6.

In addition to the already above-discussed components, the access transistor 610 comprises a further source/drain region 625, sidewall spacers 630 and an access gate 635. The SONOS transistor 620 also has sidewall spacers 640.

Coming back to Fig. 5, bit lines 510 are provided to supply control signals to the transistor 610, 620, or to sense signals. Via control gate lines 515, control voltages are applyable to the control gate 115 of the memory transistor 620. Via access gate lines 520, control signals may be applied to the access gate 635 of the access transistor 610.

The 2T SONOS system 500, 600 is designed in NOR architecture. The program and erase conditions for a 2T SONOS 500, 600 according to an exemplary embodiment of the invention are presented in Table 1. In both program and erase actions, the cells are selected one by one or in a small block (difficult to program many cells in parallel due to the considerable current needed, ~20μA/cell for PAHH and -200 μA/cell for CHE) which makes the combination of PAHH and CHE suitable for EEPROM. Since both mechanisms are used to program or erase cell by cell, it has no deeper sense to say which one is the program and which one is the erase mechanism. In Table 1 , a high V_T state and a low V_T state are mentioned instead of program or erase.

In Table 1, WL stands for word line, and BL stands for bit line.

Table 1 : voltage requirements for programming and erasing of a flash memory array using 2T NOR configuration according to an embodiment of the present invention.

The program and erase curves using the programming conditions of Table 1 for a 2T SONOS mini array (128bits) are shown in Fig. 7.

Fig. 7 shows a diagram 700 having an abscissa 702 along which the time is plotted. Along an ordinate 704 of the diagram 700, a threshold voltage value V_T is plotted in Volt. A first curve 706 relates to programming using channel hot electron, whereas a second curve 708 relates to programming information using PAHH. As shown in Fig. 7, the maximum voltage used is 5.5V in both CHEI and

PAHH. A large V_T window (~6V) can be obtained with lOOμs program and erase time.

CHEI is a localized injection, but for a small control gate length, the region of trapped electrons in the nitride becomes significant. Also the generation of secondary electrons in the channel by impact ionization events may wider the distribution of trapped electron in the nitride. As shown in Fig. 8, CHEI can be combined with PAHH to yield acceptable endurance for MTP memories.

Fig. 8 shows a diagram 800 having an abscissa 802 along which a number of programming/erasure cycles are plotted and has an ordinate 804 along which a threshold voltage is plotted in Volt. A first curve 806 relates to programming information using a CHEI procedure, whereas a second curve 808 relates to a programming scheme using PAHH.

According to an exemplary embodiment, the control gate needs not be connected to a bond pad but to a decoder (series of transistors that are correctly selected when a cell is addressed). This means that in order to erase one cell, it may be advantageous to know the address of this cell and open multiple transistors before the erase/program voltage can be passed to the control gate of the specified cell. If the erase/program voltage is high (like 12 V), high voltage transistors are needed to handle the high erase/program voltage or something else like dividing the voltage and cascading transistors, etc.

Conventionally, this would be the case because ~12V would be needed for erase. According to an exemplary embodiment, the program and erase can be done with low control gate voltage (~5V), therefore the handling of this voltage can be done without any problem on chip.

According to an exemplary embodiment, punch through assisted hot hole programming may be combined with CHEI or CHISEL which can lead an efficient programming scheme for SONOS and the program/erase voltages can be very well controlled on chip, so that there is no need for high voltage transistors.

Finally, it should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of software or hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A method of controlling a memory cell (100) to selectively assume a first logical state or a second logical state, the method comprising controlling the memory cell (100) to assume the first logical state by applying a first electric potential to a first electric terminal (107) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity and by applying a second electric potential to a second electric terminal (102) of the memory cell (100) to further accelerate the accelerated first charge carriers to thereby inject the first charge carriers in a charge trapping structure (103) of the memory cell (100) by channel hot carrier injection; and controlling the memory cell (100) to assume the second logical state by applying a fourth electric potential to the first electric terminal (107) of the memory cell (100) to accelerate second charge carriers of a second type of conductivity to thereby generate third charge carriers of a third type of conductivity by impact ionisation of the accelerated second charge carriers and by applying a fifth electric potential to the second electric terminal (102) of the memory cell (100) to accelerate the third charge carriers to thereby inject the third charge carriers in the charge trapping structure (103) of the memory cell (100).

2. The method according to claim 1, wherein a polarity of the first electric potential is identical to a polarity of the second electric potential.

3. The method according to claim 1, wherein the first electric terminal (107) is a first source/drain region, particularly is a drain region, of a memory transistor of the memory cell (100).

4. The method according to claim 1, wherein the second electric terminal (102) is a gate region of a memory transistor of the memory cell (100).

5. The method according to claim 1, wherein the first charge carriers are negatively charged particles, particularly are electrons, and the memory cell (100) is programmed by channel hot electron injection.

6. The method according to claim 1, wherein the first electric potential is a positive electric potential, particularly is a positive electric potential having an absolute value in a range between 2 V and 6 V, more particularly of less than or equal to 5 V.

7. The method according to claim 1, wherein the second electric potential is a positive electric potential, particularly is a positive electric potential having an absolute value in a range between 3 V and 10 V, more particularly is a positive electric potential having an absolute value of less than or equal to 5 V.

8. The method according to claim 1, wherein the second electric potential is applied in such a manner that the first charge carriers are injected in the charge trapping structure (103) after tunnelling through an electrically insulating structure (106) of the memory cell (100).

9. The method according to claim 8, wherein the electrically insulating structure (106) of the memory cell (100) has a thickness of at least 3 nm, particularly has a thickness in a range between 3 nm and 8 nm.

10. The method according to claim 1, wherein the charge trapping structure (103) is electrically insulating, particularly comprises one of the group consisting of a silicon nitride layer, a silicon nitride layer of an ONO layer sequence, an ONO layer sequence comprising a high-k material, and a nanocrystal structure.

11. The method according to claim 1 , comprising operating an access transistor

(610) of the memory cell (600) as a current source for providing a current for programming the memory cell (600), particularly for limiting a current flowing through a memory transistor (620) of the memory cell (600).

12. The method according to claim 1, wherein the memory cell (100) is a nonvolatile memory cell.

13. The method according to claim 1, comprising applying a third electric potential to a third electric terminal (101) of the memory cell (100) to accelerate the first charge carriers between the first electric terminal (107) and the third electric terminal (101).

14. The method according to claim 13, wherein the third electric terminal (107) is a second source/drain region, particularly is a source region, of a memory transistor of the memory cell (100).

15. The method according to claim 1, wherein the first logical state corresponds to a first threshold voltage of a memory transistor of the memory cell (100) and the second logical state corresponds to a second threshold voltage of the memory transistor of the memory cell (100), wherein the first threshold voltage is higher than the second threshold voltage.

16. The method according to claim 1, wherein the first type of conductivity and the second type of conductivity are identical and are different from the third type of conductivity.

17. The method according to claim 1, wherein a polarity of the forth electric potential is opposite to a polarity of the fifth electric potential.

18. The method according to claim 1, wherein the second charge carriers are negatively charged particles, particularly are electrons.

19. The method according to claim 1, wherein the third charge carriers are positively charged particles, particularly are holes.

20. The method according to claim 1, wherein the forth electric potential is a positive electric potential, particularly is a positive electric potential having an absolute value in a range between 2 V and 6 V, more particularly of less than or equal to 5 V.

21. The method according to claim 1 , wherein the fifth electric potential is a negative electric potential, particularly is a negative electric potential having an absolute value in a range between 3 V and 10 V, more particularly is a negative electric potential having an absolute value of less than or equal to 5 V.

22. The method according to claim 1, wherein the fifth electric potential is applied in such a manner that the third charge carriers are injected in the charge trapping structure (103) after tunnelling through an electrically insulating structure (106) of the memory cell (100).

23. The method according to claim 1, comprising applying a sixth electric potential to the third electric terminal (101) of the memory cell to accelerate the second charge carriers between the first electric terminal (107) and the third electric terminal (101).

24. A memory cell (100) for storing information by selectively assuming a first logical state or a second logical state, the memory cell (100) comprising a first electric terminal (107); a second electric terminal (102); a charge trapping structure (103); a programming unit (104) adapted for controlling the memory cell (100) to assume the first logical state by applying a first electric potential to the first electric terminal (107) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity and by applying a second electric potential to the second electric terminal (102) of the memory cell (100) to further accelerate the accelerated first charge carriers to thereby inject the first charge carriers in the charge trapping structure (103) of the memory cell (100) by channel hot carrier injection; wherein the programming unit (104) is further adapted for controlling the memory cell (100) to assume the second logical state by applying a fourth electric potential to the first electric terminal (107) of the memory cell (100) to accelerate second charge carriers of a second type of conductivity to thereby generate third charge carriers of a third type of conductivity by impact ionisation of the accelerated second charge carriers and by applying a fifth electric potential to the second electric terminal (102) of the memory cell (100) to accelerate the third charge carriers to thereby inject the third charge carriers in the charge trapping structure (103) of the memory cell (100).

25. A memory array (500), the memory array (500) comprising a plurality of memory cells (100) according to claim 24 formed in a common substrate (105).