JPH0737383A - Voltage controller of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To avoid the potential and large consumption of an electricity due to a regulator placed between a reference power source and memory array by comparing a reference voltage with a voltage on a node and controlling a driving transistor based on the result of this comparison. CONSTITUTION: Although a voltage VARY is zero at the beginning when the power source is applied, a voltage VAR fed to a transistor M3 exceeds a voltage VARY fed to a transistor M4, whereby the M3 is turned OFF and the M4 is turned ON. The M4 is also turned ON with a transistor M9 connecting an external voltage to the VARY as well. An array feeding voltage is charged toward the external voltage in this way. When the voltage VARY approaches the VAR, the state is changed with a comparator, whereby the M3 and M4 become OFF and the M9 is turned OFF. When the array feeding voltage begins to lower, the comparator is re-triggered to boost the array feeding voltage through the M9. The VAR is used to set the trigger point of the comparator, and the low impedance or the high current driving capability of the controlled array feeding power source is unnecessitated for this.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to an integrated circuit device formed in a semiconductor substrate, such as a memory device such as a dynamic random access memory.

[0002]

2. Description of the Related Art Advances in dynamic random access memory (DRAM) type very large scale integrated circuit (VLSI) semiconductor devices are well known. Recently, in the semiconductor industry, US Pat. No. 4,054 to Rao was issued.
16K type DRAM (as described in US Pat. No. 5,444)
(As described in US Pat. No. 4,658,377 to McElroy)
1MB type DRAM has been steadily progressing, and 4MB type DRAM has also arrived. A 16 MB DRAM in which more than 16 million memory cells and associated circuits are integrated on a single memory chip is the next generation DRAM scheduled for production.

At present, designers are faced with a number of challenges in designing a 16 MB DRAM type VLSI semiconductor memory device.

One problem of interest is, for example, the power consumption problem, which is the power consumed by a chip circuit controlling an external power supply that supplies power to internal circuits such as memory arrays and array peripheral circuits. It also includes. The problem is exacerbated when a large number of circuit blocks must be powered by an internal control power supply that differs from the nominal power supply of the device.

[0005]

SUMMARY OF THE INVENTION According to one aspect of the present invention: a method for controlling the voltage supplied to a node in a semiconductor device having a voltage generator on the same chip: By the drive transistor for filling,
Connecting the node to an external voltage source, generating a reference voltage, comparing the reference voltage with a voltage on the node, and controlling a drive transistor according to the result of the comparison. can get.

Preferably, the node is connected to the memory array of the semiconductor memory device. Alternatively, the node is connected to a peripheral circuit of the semiconductor memory device.

According to another aspect of the present invention, there is provided a circuit for implementing the method described above, which circuit is integrated with the semiconductor device.

Preferably, a circuit for controlling a voltage in a semiconductor memory device having a voltage generator on the same chip includes: a drive transistor connected to an external voltage source and a memory; and a reference voltage generator on the same chip. Having an input connected to the output and an input connected to an external voltage source, having an output connected to the drive transistor, comparing the external voltage source and the output of the reference voltage generator, and thereby via the drive transistor. A comparator adapted to control the voltage supplied to the device memory array.

Preferably, the circuit for driving the peripheral circuit of the semiconductor memory device having a voltage reference generator on the same chip for generating the internal reference voltage also: for charging the peripheral circuit by an external voltage source. A pass transistor, a comparator coupled to the pass transistor, the trip point of which is set by the output of a voltage reference generator and the charge supplied to the peripheral circuitry. I'm out.

In a preferred form of the invention, a circuit for a memory device integrated on a single semiconductor substrate is: a memory array, a support circuit for reading information from and writing information to the memory array. A voltage generator for receiving an external voltage and generating an internal reference voltage for supplying power to the memory array and the support circuit; connected to the memory array; connected to the external voltage and an internal reference voltage source; A circuit adapted to use an internal reference voltage to control the amount of charge that is charged and provided by the source.

Preferably said circuit of the invention comprises: a transistor for driving a memory array, having one terminal connected to an external voltage, another terminal connected to ground, and a gate, and one comparison input. A comparator coupled to an internal voltage, another comparison input to an external voltage, and an output coupled to the gate of the transistor,
A comparator adapted to compare an external voltage with an internal voltage and bias the gate of the transistor with the result of the comparison.

As part of this application, an example control circuit for controlling the voltage to the memory is disclosed. The circuit has a drive transistor connected between an external voltage source and the memory, and has an input connected to a reference voltage and another input connected to the memory array to control the gate of the drive transistor. Has a comparator that has become. A method for controlling voltage to a memory array in a semiconductor memory device having a voltage generator on the same chip is also disclosed. The method includes the steps of connecting a memory array to an external voltage source via a drive transistor, generating a reference voltage, and comparing the reference voltage with a voltage to the memory array. The drive transistor is controlled by the result of the comparison.

Other objects, advantages and features of the invention will be apparent to those skilled in the art from the following detailed description of the embodiments of the invention taken by way of example with reference to the drawings.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of an embodiment of the present invention and a memory chip including the present invention will be described here.

FIG. 1 shows a 16 megabit dynamic random access memory chip called a 16 MB DRAM. The chip size is about 325 x 660 mm. The chip is divided into four memory array quadrants. Each memory array quadrant contains 4 megabits. A 4 MB memory array quadrant contains 16 memory blocks. Each memory block contains 256 kilobits. Column decoders are arranged along the vertical axis of the chips adjacent to their corresponding memory array quadrants. Row decoders are arranged along the horizontal axis of the chips adjacent to their corresponding memory array quadrants. Peripheral circuits, including devices such as I / O buffers and timing and control circuits, are centrally located along both the horizontal and vertical axes of the chip.
The bonding pad is centrally located along the horizontal axis of the chip.

FIG. 2 is a plan view showing mounting / pin output of this device. The chip is bonded in the center,
Encapsulated in a thin resin J-shaped package with a small outline. Among other features, this DRAM
Has the feature of being programmable by bonding to either an X1 or X4 device. Pin configurations for both X1 and X4 operating modes are shown.

FIG. 3 is a view showing a three-dimensional appearance of a chip in which a sealing resin is transparent and encapsulated. The pin configuration shown corresponds to the X4 option. This TSOJ package is a central bonding (LO
CCB type lead over chip
tip). Basically, the chip is located under the lead finger. A polyimide tape connects the chip to the lead finger. Gold wire is wire bonded from the lead fingers to the central bond pad of the chip.

FIG. 4 is an external view of a package type assembly, and FIG. 5 is a sectional view of the mounted device. FIG. 6 is a diagram showing the names and sequences of bonding pads.
Both sequences are shown for the X1 and X4 options. EXT BLR is an in-house (in-ho
It is a pad only for use). Brackets such as those shown for bond pads 4 and 25 indicate that this is a bond pad option.

The general characteristics of the 16 MB DRAM of FIG. 1 are as follows. The device typically receives an external VDD of 5 volts. An internal voltage regulator on the same chip supplies 3.3V to the memory array and 4.0V to the peripheral circuitry to reduce power consumption and channel hot carrier effects. The substrate is biased at -2 volts. This configuration is programmable X1 / X4 by bonding
Is. X1 or X4 options are
It can be selected by placing a bonding wire between the bonding pad 25 (FIG. 6) and VSS for the X1 device and omitting this bonding wire for the X4 device. The resulting pinouts for the 10 options are shown in FIG. Bonding wires can be provided between the bonding pads 25 and the leadframe VSS bus 3 (FIG. 3).

Enhanced page mode (enha
A sized page mode) is the preferred option, with a metal mask programmable option for bit-wise write (data mask) operations.

The preferred option for the refresh scheme is 4096 cycles at 64 ms. But this D
The RAM is programmable for 2048 cycle refresh by bonding. Option selection can be accomplished in a manner similar to that used for X1 or X4 option selection. The associated bond pad is 4 and is bonded to VSS for 2K refresh, otherwise the 4K refresh option is implemented.

DRAM has a number of test design features. Test mode entry 1 is through an address keyless WCBR for 16X internal parallel testing with mode data comparison. Test mode entry 2 is a WCBR with an address key and overvoltage only after that (8 volts on A11). Exiting the test mode occurs by any refresh cycle (CBR or RAS only). Test mode entry 1 is an industry standard 16X parallel test. This test is similar to that used in 1 MB and 4 MB DRAMs, but 16 bits are compared simultaneously instead of 8 bits. Valid address keys are A0, A1, A2, A6. Test mode entry 2 contains a number of tests. 32X parallel test with data comparison and 1 with data comparison
6X parallel test included. Different hexadecimal addresses are key for different parallel tests. Storage cell stress test and VDD margin test
Allow connection from external VDD to internal VARY and VPERI device power lines via P-channel device. Other tests include redundant signatures
Test, low redundancy roll call
Includes tests, column redundancy roll call test, word line leak detection test, clear concurrency test, reset to normal mode. The DRAM also includes a test validation method that indicates whether it remains in test mode.

Although not shown in FIG. 1 for clarity, the DRAM has redundancy features for defect erasure. It has 4 redundant rows per 256K memory block. These four rows can be used simultaneously. There are 3 decoders per redundant row and 11 row addresses per redundant row decoder. Fuses are used for row redundancy, averaging 10 for a single repair.
One fuse blows. Row redundancy uses a two-step programmable scheme to allow for efficient correction. There are 12 redundant columns per quadrant and 4 decoders per redundant column. There are 8 column addresses and 3 load ares per decoder. The total number of fuses for a column repair is approximately 10 blown fuses per single repair. Column redundancy also allows more efficient modifications,
It uses a two-step programmable scheme.

FIG. 7 is a plan view of the arrangement of the capacitor cells. The bit line is poly 3 (TiSi 2) polycide. The bit line reference is not used. Three bit lines are twisted together to suppress noise. The power line voltage is about 3.3 volts. The word lines are poly 2 segmented. They are bound by metal 2 every 64 bits. The memory cell is of the modified trench capacitor type and is disclosed in US Pat. No. 5,017,5
06 and European Patent Application No. 0410288.

Another suitable memory cell is of the stacked trench type disclosed in US Pat. No. 4,978,634.

In FIG. 7, the size of each part is such that the bit line pitch is 1.6 μm, the double word line pitch is 3.0 μm, and the cell size is about 4.8 μm ² .
It has been obtained using the 6 μm technology. The trench opening is about 1.1 μm and the trench depth is about 6.0 μm. The dielectric is a nitride / oxide with a thickness of about 65Å. Field plate separation is used. The transistor has a thin gate. FIG. 8 is a cross-sectional view of the modified trench capacitor cell, and FIG. 9 is a side view of the trench capacitor cell.

In FIG. 10, P-channel transistor M9 and N-channel transistor M10 are connected in series and are biased between VDD and VSSRG, respectively. The gate of P-channel transistor M9 is connected to the series connection between P-channel transistor M2 and N-channel transistor M4. The gate of N-channel transistor M10 is connected to the series connection between P-channel transistor M11 and N-channel transistor M6. The series connection between transistors M9 and M10 is connected to the output VPR. A capacitor CC has one terminal connected to the gate of N-channel transistor M3 (which connects to VPR) and the other terminal connected to VSSRG. The substrate terminals of P-channel transistors M8 and M11 are connected to node N9.

FIG. 11 shows a voltage array driver circuit VARY.
Indicates DRV. P-channel transistor M1 and N-channel transistor M3 are connected in series between VDD and node N3, respectively. P-channel transistor M
2 and N-channel transistor M4 are connected in series between VDD and node N3, respectively. The gates of P-channel transistors M1 and M2 are connected together
3 connected in series. The gate of M3 is connected to node VARYO. The gate of M4 is V
Connected to AR. N-channel transistors M5 and M5B are connected in parallel between node N3 and VSSRG. The gate of M5 is connected to VRCTLAO. The gate of M5B is connected to the common terminal of switch X2. The A terminal of switch X2 is connected to VSSRG. The B terminal of the switch X2 is connected to VRCTLAO.

In the voltage array driver circuit of FIG. 11, a P-channel transistor M6, a P-channel transistor M7 and an N-channel transistor M8 are connected in series between VDD and VSSRG, respectively.
The gate of transistor M6 is connected to VRCTLAO. The gates of M7 and M8 are together TLSCS
Connected to LH. The series connection between M2 and M4 is node N6.

In FIG. 11, VDD is connected to the B terminal of switch X4. The A terminal of switch X4 is connected to node N6. The common terminal of switch X4 is P
It is connected to the gate of the channel transistor M9B. Transistor M9B is connected between VDD and output VARY. The B terminal of the switch X3 is connected to VDD. The A terminal of switch X3 is connected to node N6. The common terminal of the switch X3 is connected to the gate of the P-channel transistor M9C. Transistor M9C is connected between VDD and output VARY. A P-channel transistor M9 and an N-channel transistor M10 are connected in series between VDD and VSSRG, respectively. The gate of the transistor M9 is connected to the node N6. N-channel transistor M1
The 0 gate is connected to VRCTLAO. The series connection between M9 and M10 is connected to the output VARY.

The voltage array driver circuit VARY shown in FIG.
In DRV, P-channel transistor M11 connects output VARY to node VARYO. The gate of P-channel transistor M11 is connected to VSSRG. Switch X1 is connected to the source and drain of transistor M11. One terminal of the resistor VARYRES is connected to the output VARY. Resistance VA
The other terminal of RYRES is connected to one terminal of the capacitor C1. The other terminal of capacitor C1 is connected to VSS. All P-channel board connections are tied to VDD in FIG.

FIG. 12 shows the voltage peripheral driver circuit VPERD.
RV is shown. P-channel transistor M1 and N-channel transistor M3 are connected in series between VDD and node N3, respectively. P-channel transistor M2
And N-channel transistor M4 are respectively connected in series between VDD and node N3. The gates of P-channel transistors M1 and M2 are connected together to form M1 and M3.
Is connected to the series connection between. The gate of M3 is connected to node VPERIO. The gate of M4 is V
It is connected to PR. N-channel transistors M5 and M5B are connected in parallel between node N3 and VSSRG. The gate of M5 is connected to VRCTLP. The gate of M5B is connected to the common terminal of switch X2. The A terminal of switch X2 is connected to VSSRG. The B terminal of switch X2 is connected to VRCTLP.

In the voltage peripheral driver circuit of FIG.
P-channel transistor M6, P-channel transistor M7, and N-channel transistor M8 are VDD and V
It is connected in series with the SSRG. The gate of transistor M6 is connected to VRCTLP. The gates of M7 and M8 are connected together to TLSSCSLH. The series connection between M7 and M8 is connected to the series connection between M2 and M4 and node N6.

In FIG. 12, VDD is connected to the B terminal of switch X4. The A terminal of switch X4 is connected to node N6. The common terminal of switch X4 is P
It is connected to the gate of the channel transistor M9B. Transistor M9B is connected between VDD and VPERI. The B terminal of the switch X3 is connected to VDD. The A terminal of switch X3 is connected to node N6. The common terminal of the switch X3 is connected to the gate of the P-channel transistor M9C. The transistor M9C is connected between the external VDD and the output VPERI. A P-channel transistor M9 and an N-channel transistor M10 are connected in series between VDD and VSSRG, respectively. The gate of the transistor M9 is connected to the node N6. The gate of N-channel transistor M10 is connected to VRCTLP. M9
The series connection between M and M10 is connected to the output VPERI.

In the voltage peripheral driver circuit of FIG.
P-channel transistor M11 connects the VPERI output to node VPERIO. The gate of P-channel transistor M11 is connected to VSSRG. Switch X1 is connected to the source and drain of transistor M11. One terminal of the resistor VPERRES is connected to the output VPERI. The other terminal of the resistor VPERRES is connected to one terminal of the capacitor C1. The other terminal of capacitor C1 is connected to VSS. All P-channel board connections are tied to VDD in FIG.

VARYDRV--Voltage Array Driver VPERDRV--Voltage Peripheral Driver--Schematics in FIGS. 11 and 12 These are the main drivers for the device. 4 V
There is ARYDRV. They provide an array voltage of 3.3 volts to the array sense amplifier. Two of them support quadrants Q0 and Q1, the other two Q2
And support Q3. Each of these drivers has 2
Drives the power supply to either the left or right octet of one quadrant. For VPERDRV,
There are two of them. They are for various peripheral circuits.

These drivers are composed of CMOS differential amplifiers having a class A stage driver. The circuit is connected as a comparator and a unity gain buffer with feedback from its output to its input terminal.

The modification of this circuit from the conventional circuit is M5.
And M10 are not only used as a source-coupled pair and a mere current source in the output stage, but are also used to control driver enable or disable. The signal used to implement this control is VRCT for VARYDRV.
LAO and VRCTLP for VPERDRV
Is. Thus, this control drives only the required drivers. If the driver stays active, the Class A output stage will always draw current to GND, which will increase the standby current.

In the DFT, storage cell stress mode, the active TLSCLSH signal separates the first stage, source coupled pair of the comparator from its second stage, the output stage. At the same time, it causes M9 to switch on completely and the driver output VARY or
ERI is forced to an external voltage.

During the analysis of the comparator, the metal level CUT P
The OINT can be disconnected. By doing so, it opens the feedback loop for AC signals. Thus, the AC characteristics of the comparator (bandwidth and gain)
Can be analyzed in an open loop. R1 and C1 act as dampers for the output VARY or VPERI.

VARYDRVS-Voltage Array Driver Standby VPERDRVS-Voltage Peripheral Driver Standby-Schematic Diagrams in FIGS. 13 and 14 These circuits have small transistor dimensions,
Same as the main driver except all control is in the current source transistors M5 and M10. It is the DFT, TLSCS that controls the output stage
It does not have a separate circuit for the LH signal. This D
FT control is included in the M5 and M10 stages. In this DFT mode (storage cell stress),
The driver has been disabled. Therefore, only the main driver is used to supply the external voltage to the device.

As with the main driver, the feedback loop can be broken. This allows both open loop gain and open loop bandwidth to be determined.

Each of these circuits is on one device.
They are used to supply leakage current to the device.

An important feature of the configuration described here is that it avoids potential high power consumption by a regulator located intermediate the reference power supply and the memory array of the memory device. Instead, the array receives an external voltage VDD
The voltage is directly supplied by (E) and the array supply nodes are allowed to change towards the supply voltage. A comparator that detects both the array supply voltage and the reference voltage is connected to ensure that the bond charge is stopped before the full supply voltage is reached. If the voltage drops, the comparator is re-driven to charge.

Referring to FIG. 11, the control signal VRCTL.
AO switches on transistor MS to enable the comparator consisting of M1, M2, M3, M4. The memory array load is VARYRES and C1
Represented by. VARY is used to indicate the array power supply. VAR is a reference voltage supplied from the circuit of FIG. 10 and taken out from VDD (E).

Considering the power-on sequence, VA
RY will initially be zero. At some point during power up,
The signal VRCTLAO enables the comparator. (M3
VAR (supplied to M4) is VARY (supplied to M4)
Should be exceeded, M3 is off and M4 is on. M4 is also turned on by M9 connecting VEXT (E) to VARY. Thus, the array supply voltage is charged towards VEXT. VARY is VA
When approaching R, the comparator changes state, causing M3 and M4
Turns off. Thus, M9 is turned off. When the array supply voltage begins to drop, the comparator retriggers to boost the array supply voltage via M9. VAR
Is used to set the trigger point of the comparator, which does not require low impedance or high current drive capability of the controlled array supply.

The circuits described herein are particularly, but not exclusively, suitable for memory arrays. First of all, the array is ultimately a capacitive load, which itself helps regulate the voltage and store the charge. Furthermore, a stable power supply is not required at all times, eg when the power supply is inactive or not accessed. In fact, timing control can be provided via VRCTLAO and / or TLSCSCH to charge the array prior to access, so that the supply voltage is stable between accesses. Thus, as a variation on this, M9 is unpowered during array access. Instead of retriggering the capacitor when the supply voltage drops, a similar smaller topping up circuit can be used, especially when the device is active. Such a circuit is shown in FIG. 13 and FIG.
4 is shown. FIG. 12 shows a circuit VPERDRV, which is a driver peripheral circuit for an array of decoders, sense amplifiers and the like. It is similar to the circuit described above, but uses different control signals and different reference voltages.

With respect to the above description, the following items will be further disclosed. (1) A method of controlling a voltage supplied to a node in a semiconductor device having a voltage generator on the same chip, wherein the node is supplied with an external voltage via a driving transistor for filling the node with an external voltage. Connecting to a source, generating a reference voltage, comparing the reference voltage to the voltage on the node, and controlling the drive transistor with the result of the comparing step.

(2) The method according to the first item, wherein the node is connected to a memory array of a semiconductor memory device.

(3) The method according to the first item, wherein the node is connected to a peripheral circuit of the semiconductor memory device.

(4) A circuit integrated with the semiconductor device, for executing any of the methods of the first to third aspects.

(5) A circuit for controlling a voltage in a semiconductor memory device having a voltage reference generator on the same chip according to item 4, which is a driving transistor connected to an external voltage source and the memory array, One input is connected to the output of the same-chip reference generator, another one input is connected to an external voltage source, and the output is connected to a drive transistor, comparing the external voltage source with the output of the reference generator, A circuit adapted to control the voltage supplied to the memory array of the device via the drive transistor.

(6) A circuit for driving a peripheral circuit of a semiconductor memory device having a voltage reference generator for generating an internal reference voltage on the same chip according to the fourth item, wherein the peripheral circuit is connected from an external voltage source. A pass transistor for charging the pass transistor, connected to the pass transistor, the trip point of which is set by the output of the voltage reference generator and the charge supplied to the peripheral circuit to control the pass transistor. Circuit including a container.

(7) A circuit for a memory device integrated on a single semiconductor substrate according to item 4, which is for memory array, for reading information from the memory array, and for writing information to the memory array. A support circuit, a voltage generator for receiving an external voltage and generating an internal reference voltage to supply power to the memory array and the support circuit, connected to the memory array, connected to the external voltage,
A circuit including a circuit which is connected to the internal reference voltage, charges the memory from an external voltage source, and controls the amount of charges supplied using the internal reference voltage.

(8) In the circuit of the seventh item, one terminal is connected to an external voltage and another terminal is connected to the ground.
A transistor having a gate for driving the memory array, one comparison input is connected to an internal voltage, another comparison input is connected to an external voltage, an output is connected to the gate of the transistor, and the external voltage is connected to the internal voltage. And a comparator adapted to bias the gate of the transistor with the result of the comparison.

(9) A circuit for controlling the voltage to the memory is disclosed. The circuit has a drive transistor connected between the external voltage source and the memory, and has one input connected to the reference generator and another input connected to the memory array to control the gate of the drive transistor. Including the comparator that became. A method of controlling voltage to a memory array in a semiconductor memory device having a voltage generator on the same chip is also disclosed. This method
The steps include connecting the memory array to an external voltage source via a drive transistor, generating a reference voltage, and comparing the reference voltage with the voltage to the memory array.
The drive transistor is controlled by the result of this comparison.

[Brief description of drawings]

FIG. 1 is a block system level diagram showing a 16MB dynamic random access memory chip employing an embodiment of the present invention.

FIG. 2 is a plan view showing a pin configuration of a mounted memory chip.

FIG. 3 is an external view showing a three-dimensional structure of a mounted memory chip in which a sealing material is transparent.

FIG. 4 is an external view of the assembly of FIG.

5 is a sectional view of FIG.

FIG. 6 is a plan view showing a bonding pad configuration of a memory chip.

FIG. 7 is a plan view showing a portion of a memory array.

FIG. 8 is a cross-sectional view of a portion of a memory array.

9 is a side view of the cross section of FIG.

FIG. 10 is a circuit diagram of VPERBUF.

FIG. 11 is a circuit diagram of VARYDRV.

FIG. 12 is a circuit diagram of VPERDRV.

FIG. 13 is a circuit diagram of VARYDRVS.

FIG. 14 is a circuit diagram of VPERDRVS.

[Explanation of symbols]

 N node X switch M transistor VARYDRV voltage array driver VPERDRV voltage peripheral driver

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/04 21/822 8832-4M H01L 27/04 B (72) Inventor Narasimhan Yenger USA Texas Plano, Early Morne 4425

Claims (2)

[Claims] 1. A method of controlling a voltage supplied to a node in a semiconductor device having a voltage generator on the same chip, the node being connected via a drive transistor for charging the node with an external voltage. Connecting to an external voltage source, generating a reference voltage, comparing the reference voltage with a voltage on the node, and controlling the drive transistor with the result of the comparing step. . 2. A circuit integrated with the semiconductor device according to claim 1, for carrying out the method according to claim 1.