JPH0736807A - Communication control method - Google Patents

Abstract

PURPOSE:To prevent the performance of a system from being reduced by adding length information to the head of communication data, and when the communication data are received, reading out the length information and judging information volume by a processor and then executing direct memory access(DMA) transfer to a succeeding storage part. CONSTITUTION:When a communication control circuit 72 receives receiving data, an interruption signal to a processor is generated from an interruption generating part at the reception of the initial byte (RX INT) and length information in a buffer is read out (RX READ). At the 2nd byte, the interruption generating part generates an interruption (RX INT) to read out the receiving data (RX READ). The number of transfer bytes is set up (DMA Enable) in a counter of a DMA control circuit 71 and succeeding data are DMA-transferred to a main storage device in the circuit 71. Since information volume is judged from length information to execute DMA transfer, the DMA transfer can be completed within a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control method for transferring received communication data to a next storage unit such as a memory.

[0002]

2. Description of the Related Art Generally, transmission / reception data transfer in communication control includes two methods: a method of executing by a program interrupt and a method of executing by utilizing DMA (Direct Memory Access) control. First, in data transfer by program interruption, a processor that executes a communication program directly controls a communication control unit that transmits and receives data. For example, when data is received from an external device, the communication control unit performing the reception sends an interrupt signal to the processor, and the processor causes the received data to be transferred from the communication control unit to the next data storage unit. Control is performed so that data is transferred. That is, the data transfer by the program interrupt is a method in which the processor directly transfers the data.

On the other hand, a method of transferring data by utilizing DMA control is a method of transferring data by a DMA control circuit, which will be described below. FIG. 2 is a block diagram of an information processing system mainly including a communication control unit for explaining such a communication control method. The system shown is CP
U (processor) 10, communication control unit 20, main storage device 3
0, bus 40, external device 50, and communication line 60 are shown.

The processor 10 is a central processing unit that performs various controls such as communication control. The communication control unit 20 is a device that controls transmission / reception of communication data between the external device 40 and the main storage device 30 or the like according to an instruction from the processor 10, and includes a DMA control circuit 21 and a communication control circuit 22. Has been done. The DMA control circuit 21 has a function of performing DMA transfer control, and the communication control circuit 22 includes an external device 50.
It has a function of receiving communication data from the buffer in the buffer and performing DMA transfer.

The main storage device 30 stores programs executed by the processor 10 and the like, and also has a communication control circuit 22.
The communication data temporarily stored in the buffer is received via the bus 40, and constitutes the next storage unit of the communication data for storing this. Further, the bus 40 is a system bus for connecting the processor 10, the communication control unit 20, and the main storage device 30, and performing data transfer and the like among them.
The external device 50 is composed of a personal computer, a modem, or the like, and has a function of transmitting communication data to the communication control circuit 22 via the communication line 60 and receiving communication data from the communication control circuit 22. In addition, communication line 6
Reference numeral 0 is a data transfer path that connects the external device 50 and the communication control unit 20, and is configured to transfer serial data.

Next, the communication control operation in the information processing system thus configured will be described. When the processor 10 that executes the communication program sets the communication control circuit 22 of the communication control unit 20 to a data transferable state and a data transfer request occurs in this state, the communication control circuit 22
Sends the data transfer request signal REQ-2 to the DMA control circuit 2
Send to 1.

The DMA control circuit 21 receives the data transfer request signal REQ-2 and sends the data transfer request signal REQ-1 to the processor 10. Processor 1
0 is a response signal ACK-1 when DMA transfer is possible.
The DMA control circuit 21 returns the response signal ACK-
1 causes the communication control circuit 22 to send a response signal ACK-
Returns 2. With such a data transfer handshake, the communication control circuit 22 receives parallel data from the data transfer source via the bus 40 in the case of data transmission, sends this as serial data to the external device 50, and receives it. If there is, the data from the external device 50 is transferred to the bus 4
It is sent to the data transfer destination via 0.

[0008]

By the way, today,
Communication control with a plurality of external devices 50, that is, multiplexing of communication control is performed. In such a case, the communication control units 20 are provided in the multiplexed number, and each communication control unit 20 controls the communication under its control.
However, in the case where a plurality of communication control units 20 are provided in this way, considering the above program transfer, the load on the processor 10 is heavy and communication processing overhead occurs. As a result, communication control is performed. Since it interferes with input / output processing other than the above, the performance of the entire device has deteriorated.

On the other hand, in the method by the DMA transfer, there is no means for judging how much the amount of data from the other party is while the receiving operation is being executed, so that the DMA transfer has a wasteful margin time. However, even with this method, it was difficult to multiplex the communication control units.

That is, normally, the data from the external device 50 is received by the start-stop synchronization method, and in this case, the end of the transfer is unknown by the general communication protocol. Therefore, in the conventional communication control method, the DMA transfer time is set in advance for each system so that the received data can be reliably received, and the DMA transfer is performed during this set time. Therefore, normally, there is an unreserved margin time between the set time and the actual data transfer time. Since the bus 40 is occupied during the time when such DMA transfer is performed, when the communication control unit 20 is multiplexed, while one communication control unit 20 is performing the DMA transfer, another communication control is performed. Access sources other than the unit 20 and communication control cannot perform processing. As a result, the performance of the system is deteriorated, and it is difficult to multiplex the communication control units as described above.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object of the present invention is to provide a communication control method capable of preventing deterioration of the system performance when the communication control units are multiplexed. And

[0012]

According to the communication control method of the first invention, length information indicating the information amount of the communication data is added to the beginning of the communication data, and when the communication data is received,
First, the processor reads the length information, determines the information amount of the communication data, and thereafter, based on the determined information amount, transfers the communication data to the next storage unit by direct memory access. It is what

According to the communication control method of the second invention, length information indicating the information amount of the communication data is added to the head of the communication data, and when the communication data is received, the communication including the length information data. All of the data is transferred from the receiving unit to the next storage unit by direct memory access, and an interrupt generation circuit for generating an interrupt to the processor when the length information data is stored in the next storage unit is provided. When an interrupt is generated from the generation circuit, the processor reads the length information data from the next storage unit and, from the information amount of the communication data, from the time when the interrupt occurs to the time when the direct memory access transfer of the communication data ends. The transfer time of the communication data is calculated, and the end of the direct memory access transfer of the communication data is determined based on the transfer time. It is intended to.

In the communication control method of the third invention, in the second invention, when the transfer time calculated from the length information has elapsed,
The processor collates the information amount of the transfer data read from the length information with the information amount actually transferred, and the information amount actually transferred is less than the information amount of the transfer data read from the length information. In this case, the transfer time corresponding to the shortage is calculated, and the transfer data for the shortage is transferred again by the direct memory access with this transfer time.

[0015]

In the communication control method of the first invention, when communication data is received from an external device, the received data is temporarily stored in the buffer of the communication control circuit. Then, an interrupt is generated at the first byte of the received data, for example,
As a result, the processor transfers data by interruption, determines the information amount of the received communication data, and sets the value in the counter of the DMA control circuit. After that, the communication control circuit DMA-transfers the received communication data, and when the counter reaches a predetermined value, it is determined that the transfer is completed.

Further, in the communication control method of the second invention, when the communication data is received from the external device, the received data is temporarily stored in the buffer of the communication control circuit as in the first invention. Then, the received data is DMA-transferred from the beginning and stored in the next storage unit such as the main storage device. An interrupt is generated from the interrupt generation circuit at the time when the length information is transferred. As a result, the processor accesses the next storage, reads the length information, and activates the soft timer. Then, the transfer time is calculated based on the length information, and this transfer time is measured by the soft timer. When the predetermined transfer time has elapsed, the processor determines that the DMA transfer of the received communication data is completed.

In the communication control method of the third invention, when the predetermined transfer time by the soft timer in the second invention has elapsed, the processor determines the information amount determined from the length information,
Check the amount of information actually transferred. Then, if the amount of information actually transferred is insufficient in this collation, the transfer time corresponding to the insufficient amount is calculated, and DMA transfer of the insufficient communication data is performed again based on this transfer time.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sequence chart for explaining the communication control method of the present invention. Prior to this explanation, an information processing system to which the communication control method of the present invention is applied will be described.

FIG. 3 is a block diagram of the information processing system. The system shown in the figure has a CPU (processor) 1
0, the main storage device 30, the bus 40, the external device 50, the communication line 60, and the communication control unit 70 are shown. Since the configurations of the processor 10 to the communication line 60 are the same as the conventional ones,
The description here is omitted. The communication control unit 70 is composed of a DMA control circuit 71 and a communication control circuit 72 as in the conventional case. In addition, the DMA control circuit 71 includes a DMA
A counter 71a for counting the transfer amount is provided, and the communication control circuit 72 generates a buffer 72a for receiving data from the external device 50 and an interrupt when receiving length information in received data described later. The interrupt generating unit 72b is provided.

Next, the format of received data, which is a premise of the communication control method of this embodiment, will be described. FIG. 4 shows the reception format. That is, in the present embodiment, the data received from the external device 50 has a protocol in which the first two bytes are length information indicating the amount of information of the received data. Incidentally, the length information actually indicates the number of bytes of a value obtained by subtracting 2 bytes of the length information from all the received data. In this embodiment, the received data has such a protocol, and the operation of the information processing apparatus when receiving such data will be described below with reference to FIG.

First, the processor 10 sets the DMA control circuit 71. This setting is an initial setting operation of the system, and indicates a process of setting the DMA transfer mode or the transfer mode by interruption. here,
The DMA mode is set for the DMA control circuit 71.
However, here, the request signal output from the DMA control circuit 71 is set to be masked, and the DMA request to the processor 10 is prohibited. The reason is to prevent the DMA control circuit 71 from malfunctioning due to noise or the like, and as a result, the DMA request is not started.

Next, the processor 10 controls the communication control circuit 72.
Set. This setting is also the initial setting of the system, and the mode setting is set to the DMA mode here as well.
Further, the processor 10 enables the communication control circuit 72 (RX Enable in FIG. 1), and when the received data is stored in the buffer 72a, the interrupt generation unit 7
It is set so that an interrupt is generated for the first 2 bytes from 2b and a request signal is generated for the DMA control circuit 71 after the 3rd byte.

With such settings, the communication control circuit 72
When receiving the received data, an interrupt signal is generated from the interrupt generator 72b to the processor 10 (RX INT) at the first 1-byte reception, and the processor 10 stores the received signal in the buffer 72a based on this interrupt. Read the length information (RX READ). Then, also in the next second byte, the interrupt generation unit 72b generates an interrupt (RX INT), which causes the processor 10 to read the received data (RX) in the same manner as in the above case.
READ). The reason why the 2-byte length information is processed byte by byte is that the processing of the processor 10 is performed byte by byte.

Then, the processor 10 reads the read 2
Since the amount of data after that is known from the byte length information, the number of bytes to be transferred is set in the counter 71a of the DMA control circuit 71. After that, the processor 10
The DMA request prohibition of the MA control circuit 71 is released (D
MA Enable), the DMA control circuit 71 returns a response signal (ACK RX) to the request signal (REQ RX) from the communication control circuit 72, and DMA-transfers subsequent data to the main storage device 30. .

Further, the counter 71 of the DMA control circuit 71
Based on the request signal from the communication control circuit 72, a counts down from the set count value, and when the count value becomes “0”, generates a counter interrupt to the communication control circuit 72 (counter
IPT). The communication control circuit 72 ends the DMA data transfer by this counter interrupt, and the interrupt generation unit 72b
Causes the processor 10 to generate a DMA transfer end interrupt (INT). As a result, the processor 10
Sets the communication control circuit 72 to a reception prohibited state (R
X Disable), the DMA control circuit 71 is also set to the DMA operation disabled state (DMA Disable).
ble).

As described above, in the first embodiment, the information amount of the received data is determined from the length information included at the beginning of the received data, and the subsequent data is DMA-transferred based on the information amount. Since it is set to DMA of the received data
The transfer can be completed in the shortest time without wasting extra time. As a result, the bus occupation time for the DMA transfer can be shortened, so that the communication control unit 70 can be easily multiplexed.

Next, a second embodiment will be described. Figure 5
It is a block diagram of an information processing system for implementing the communication control method of a 2nd example. The system shown is a CPU
The configuration of the (processor) 10, the main storage device 30, the bus 40, the external device 50, the communication line 60, and the communication control unit 80 is shown. The configurations of the processor 10 to the communication line 60 are the same as those of the first embodiment and the conventional example. Since it is the same, the description here is omitted.

The communication control unit 80 includes a DMA control circuit 81.
And a communication control circuit 82 and an interrupt generation circuit 83. Further, the DMA control circuit 81 is provided with a counter 81a for counting the DMA transfer amount,
The communication control circuit 82 is provided with a buffer 82a for receiving data from the external device 50. The interrupt generation circuit 83 has a function of generating an interrupt to the processor 10 when the length information located at the head of the received data is transferred to the main storage device 30. Also in this second embodiment, the communication protocol is set so that the length information is located in the first 2 bytes of the received data. Since this is the same as in the first embodiment, here The description of is omitted.

Further, the processor 10 is provided with a soft timer 10a for performing a timer operation when the interrupt from the interrupt generation circuit 83 is accepted. The soft timer 10a is composed of a program and the like.

Next, a communication control method in the above system will be described. FIG. 6 is a sequence chart thereof.
First, also in the present embodiment, as shown in FIG. 4, the reception data has the first two bytes as length information indicating the data amount.

When receiving such data, the processor 10 sets the DMA control circuit 81 in the DMA mode, and further sets the maximum count number that can be set in the counter 81a. Then, the DMA control circuit 81 and the communication control circuit 82 are enabled. After that, the communication control circuit 82 sends a request signal to the DMA control circuit 81 (REQ RX), and the DMA control circuit 81
When a response signal is returned from (ACK RX), the DMA transfer from the buffer 82a to the main memory device 30 is started.

Then, when 2 bytes, which is the length information of the received data, is transferred, the value of the counter 81a causes the DM
The A control circuit 81 instructs the interrupt generation circuit 83 to generate an interrupt signal, and the interrupt generation circuit 83
Based on this, an interrupt signal (IN
T) is transmitted. Even at this point, the received data DM
A transfer continues. Based on this interrupt signal, the processor 10 reads the length information of the received data which is transferred by accessing the main memory device 30, determines the amount of data to be transferred thereafter based on the data content, and determines the amount of this data. Then, the time until the end of the transfer is calculated based on the transfer rate and the soft timer 10a is set and activated at this time.

When the set time of the soft timer 10a has elapsed (step S1), the processor 10 determines that the DMA transfer is completed, and the counter 81 of the DMA control circuit 81 is determined.
The value of a is read, and the value shown is subtracted from the value set before transfer to calculate the number of bytes actually transferred (step S2). Then, the value of the calculation result and the value of the first length information are compared (step S3), and if they match, it is considered that the data transfer has ended, and the reception operation is ended. That is, the reception operation of the communication control circuit 82 is prohibited (RX Disable), and the DMA control circuit 8
The DMA mode is canceled for 1.

On the other hand, in step S3, when the number of bytes calculated from the length information and the number of bytes in the counter 81a are insufficient, the processor 10 performs the DMA transfer again (step S4). That is, the above operation is repeated. Then, returning to step S2, the actual number of transfer bytes is calculated again, and this operation is repeated until the data match.

As described above, in the second embodiment, all the received data are DMA-transferred, the transfer time is calculated while the transfer is performed, and the transfer end is determined based on the calculated transfer time. Therefore, for example, when an interrupt to the processor 10 occurs, it can be applied to a system in which the interrupt process is not executed in real time. That is, even if the interrupt processing is slightly delayed, the transfer processing of the received data is being performed during that time, so that the time until the transfer is completed is not affected.

In each of the above embodiments, the first 2 bytes of the received data is used as the length information, but the present invention is not limited to this value, and any value that can represent the data amount of the received data can be used.
The number of bytes is not particularly limited. In the second embodiment, the soft timer 10a is used to measure the transfer time.
However, the timer is not limited to this timer, and any timer can be applied as long as it can judge the passage of the transfer time. Furthermore, in each of the above-described embodiments, the case where the main storage device 30 is used as the next storage unit has been described, but in addition to this, the same effect can be obtained even with various transfer destinations such as an external storage device.

[0037]

As described above, according to the communication control method of the first invention, when the length information indicating the information amount of the communication data is added to the head of the communication data and the communication data is received. The data transfer is performed by interrupting the length information, the amount of information to be transferred is determined, and thereafter, the DMA transfer is performed based on the determined information amount. Therefore, the transfer of the received data should be performed in the shortest time. Therefore, the burden on the processor can be minimized. as a result,
Multiplexing of the communication control unit can be easily realized.

According to the communication control method of the second invention, the length information of the communication data is added to the beginning of the communication data, and when this communication data is received, all the data are DMA-transferred to the next storage unit. At the same time, an interrupt is issued when the length information is transferred, the processor reads the length information from the next storage unit based on the interrupt, calculates the transfer time from the information amount, and terminates the data transfer based on this transfer time. Since the determination is made, as in the first aspect of the invention, the load on the processor can be reduced, the communication control unit can be easily multiplexed, and the interrupt processing is not performed in real time. Is also applicable.

According to the communication control method of the third invention, in the second invention, the processor compares the information amount judged from the length information with the information amount actually transferred, and the information amount actually transferred is determined. When the shortage occurs, the transfer time corresponding to the shortage is calculated, and the shortage DMA transfer is performed again. Therefore, in addition to the effect of the second aspect of the invention, the transfer time is calculated within the transfer time calculated for some reason. Even if the data transfer is not completed, the data transfer can be surely performed.

[Brief description of drawings]

FIG. 1 is a sequence chart of a first embodiment of a communication control method of the present invention.

FIG. 2 is a block diagram of a main part of an information processing system for implementing a conventional communication control method.

FIG. 3 is a block diagram of a main part of an information processing system for implementing the first embodiment of the communication control method of the present invention.

FIG. 4 is an explanatory diagram showing a reception format of communication data in the communication control method of the present invention.

FIG. 5 is a block diagram of an essential part of an information processing system for implementing a second embodiment of the communication control method of the present invention.

FIG. 6 is a sequence chart of a second embodiment of the communication control method of the present invention.

[Explanation of symbols]

 10 Processor (CPU) 10a Soft Timer 71, 81 DMA Control Circuit 72, 82 Communication Control Circuit 83 Interrupt Generation Circuit

Claims (3)

[Claims] 1. When length information indicating the amount of information of the communication data is added to the beginning of the communication data and the communication data is received, first, the processor reads the length information and A communication control method characterized in that the amount of information is determined, and thereafter, based on the determined amount of information, the communication data is transferred to the next storage unit by direct memory access. 2. When the length information indicating the information amount of the communication data is added to the beginning of the communication data and the communication data is received, all of the communication data including the length information data is received by the receiving unit. Direct memory access transfer to the next storage unit, and an interrupt generation circuit for generating an interrupt to the processor when the length information data is stored in the next storage unit, and an interrupt is generated from the interrupt generation circuit. In this case, the processor reads the length information data from the next storage unit and calculates the transfer time from the occurrence of the interrupt to the end of the direct memory access transfer of the communication data from the information amount of the communication data, A communication control method characterized by determining the end of direct memory access transfer of the communication data based on the transfer time. 3. When the transfer time calculated from the length information has elapsed, the processor compares the information amount of transfer data read from the length information with the actually transferred information amount, and the length information If the amount of information actually transferred is less than the amount of information of the transfer data read from, the transfer time corresponding to that amount is calculated, and the transfer data for the insufficient amount is transferred again using this transfer time. The communication control method according to claim 2, wherein: