JPH0736692A - Each bit settable register - Google Patents

Abstract

PURPOSE:To provide a register which is capable of setting the value of '1' or '0' for each bit without increasing the size of a program when the control program of an MPU is described and without lowering execution speed. CONSTITUTION:This register is provided with one or plural designated bits C7 preliminarily designating either one operation of the setting or release of each signal line of plural signal lines d0 to d6, a means 1 detecting that the preliminarily fixed setting code '1' is written in the designated bit C7, a means 2 detecting that the preliminarily fixed release code '0' is written in the designated bit C7, a discrimination means 4 discriminating which signal line of the plural signal lines d0 to d6 the operation of the setting or the release is performed for is instructed or not and an output means 5 outputting the designated value to the designated signal line of to plural signal lines d0 to d6 by performing the setting or the release of the signal line in accordance with the results of the detections 1 and 2 of the setting or the release and the result of the discrimination 4 of the presence or absence of the instruction of the setting or the release each signal line d0 to d6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microprocessor M.
By writing significant "1" or "0" values to multiple data bits at the same address in the sense that PU can write in one write operation, each signal line of the same multiple signal lines (data bits) (Bit) ON setting or OF
The present invention relates to a register that can be set for each bit of a device that controls the release of F independently of each other. As the register, only write operation by MPU is possible, efficient description of control program and high-speed execution It is hoped that this will be possible.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional configuration example in the case of controlling a plurality of signal lines via a register using an MPU. In the figure, a ROM is a read-only memory device that stores a program in which a control procedure is described in the control language (machine language) of the MPU. The RAM is a readable / writable memory element for temporarily storing data and the like generated during the process of data processing by the MPU according to the description of the program. The MPU sequentially reads the description of the program in the ROM, and according to the procedure described therein, processes the data, generates the data, and turns on / off the output signal line to the external controlled circuit according to the result. This is a data processing unit. The IC means that it has a plurality of signal lines d _{0 to} d ₆ connected to an external circuit, and the MPU provides significant registers to registers at specific addresses b _{0 to} b ₆ provided in the IC via a data bus. By writing a value of "1" or "0", the MPU can turn on / off any signal line. Conventionally, the register in the IC, for example, as shown in the configuration example of FIG. 4, the predetermined specific address b ₀ ~
When the MPU performs a write operation on b ₆ , the value of the data bus at that time (the value at that moment of b _{0 to} b ₆ ) is
Held in the latch of the flip-flop FF, and the signal line d ₀ ~
It was configured to output as d ₆ . Once the writing of data to registers in the address b ₀ ~b ₆ is performed until the write operation then the same address b ₀ ~b ₆ is performed, prior to the signal line d ₀ to d ₆ The "1" or "0" state of is retained. Further, as shown in the conventional example of FIG. 3, the output of the signal line d ₀ to d ₆ for a specific address b ₀ ~b ₆ of MPU (
The output Q) of the D-type FF is read and detected, and the switch SW is controlled to temporarily set the value "1" or "0" set in the signal lines d _{0 to} d ₆ to the MPU later. In some cases, the registers at addresses b _{0 to} b ₆ can be read.

[0003]

As in the conventional example shown in FIGS. 3 and 4, the output signal line d _{0 of which the} register is 7 bits (7 lines) is used.
Consider the case of controlling ~ d ₆ . These seven signal lines d ₀
When using ~ d ₆ as independent control signals,
It is necessary to turn on / off each signal line (bit) independently of the setting states of other signal lines (bits). (That is,
Along with writing "1/0" to a certain bit,
"1 / O" must not change. Therefore, in the prior art, in the configuration example of FIG. 4, the MPU once sets the seven signal lines d _{0 to} d ₆ to a certain state so that the MPU can perform such an operation. After that, if only a certain specific signal line, for example, the signal line d ₀ is switched from OFF (“0”) to ON (“1”), the remaining other signal lines d _{1 to} d ₆ are changed. At that time, if the state of the other signal lines d _{1 to} d ₆ is changed to the signal line d ₀ unless the register for the addresses b _{0 to} b ₆ is set after knowing what the state is like. It changes and ends by changing. Therefore, when setting the value of "1" or "0" to d ₀ to d ₆ 7 signal lines is a set value, every stored in the address on the predetermined RAM, then again signal Any one of the lines d _{0 to} d ₆
ON ("1") or OFF for one or more signal lines
When it becomes necessary to control ("0"), first read the preset value on the RAM that was stored and stored previously, and for the bit corresponding to the specific signal line to turn ON or OFF. ,
Although not shown, by performing the calculation of the logical sum or logical product, bits corresponding to the other signal line that should not be changed, since the same as the previous setting value, a write operation to the register address b ₀ ~b ₆ (Setting) is required. At the same time as setting this register, it is necessary to update and set the already set value stored in the previous address on the RAM. Therefore, in order to perform the setting operation with the configuration of FIG. 4, (1) perform the operation of reading the preset value from the memory RAM before setting the signal line. (2)
Perform a logical operation to obtain the read preset value and the new setting state. (3) When setting the signal line, write the set value into the memory RAM and place it. (Four)
It is necessary to secure a RAM area of the same size as the necessary register size. The above (1), (2), and (3) increase the program size and decrease the execution speed at the time of execution.
The above (4) has a drawback that it increases the required memory amount. Next, in the configuration example of FIG. 3, since the register is configured to be readable and writable, the MPU needs to store a copy of the set value using the RAM as in the example of FIG. However, (1) Prior to setting the signal line, read the preset value from the register output (D type FF output Q). (2) Perform a logical operation to obtain the read preset value and the new setting state. (3) It is necessary to provide a read pulse detection circuit and a switch SW in the register configuration for reading. Above (1), (2)
Has the drawback of increasing the program size and lowering the execution speed at the time of execution, and (3) above has the drawback of increasing the circuit scale of the IC that constitutes the register.

A program in the case of the conventional method shown in FIG.
The description of the system is MOV A, DATA REG BK (memo
Read the current value set above), AND A, # 1
(Perform necessary logical operations), MOV DATA RE
G, A (set in the data register), MOV DATA
REG BK, A (hold the setting value in the memory)
Become. In addition, the program description for the conventional method of FIG.
The description is MOV A, DATA REG (data register
Read the current value of), AND A, # 1 (required logical operation
), MOV DATA REG, A (data register
Set to a star).

An object of the present invention is to prevent an increase in the scale of an IC to be accommodated even when a large number of registers are mounted for controlling a large number of signal lines, and an increase in the program size when writing a control program for an MPU. The execution speed does not decrease,
It is to realize a register that can set a value of "1" or "0" for each bit.

[0006]

The basic configuration of the register of the present invention for achieving this object will be described with reference to the principle diagram of FIG.
ON of the signal lines of the plurality of data bits on the same address can be written at once in the write operation by MPU (b ₀ ~b ₆₎ is the same plurality of signal lines through the placed register (d ₀ ~d ₆₎ In a register that can be set for each bit of a device that independently controls the setting or cancellation of OFF, setting or canceling one of the setting or cancellation of each signal line of the plurality of signal lines (d _{0 to} d ₆ ). One or a plurality of designated bits (C ₇ ) for designating the operation in advance and a preset code for the designated bits (C ₇ ).
And ( "1") means for detecting that has been written (1), means for detecting that the predetermined release code to the specified bit (C ₇₎ ( "0") is written as (2) Identification means (4) for identifying whether or not it is instructed to which of the plurality of signal lines (d _{0 to} d ₆ ) the setting or cancellation operation is to be performed
And the result of detection (1, 2) of the setting or cancellation and each signal line (d ₀ ~
d ₆ ) According to the result of identification (4) of the presence or absence of the setting or cancellation instruction for each, set the specified value to the specified signal line among the plurality of signal lines (d _{0 to} d ₆ ). And an output means (5) for releasing and outputting.

[0007]

[Action] In the register of the present invention, one newly provided or specified bit C ₇ is predetermined plurality of signal lines of the register output settings for each signal line _{(d 0 ~d 6) "1} " Whether to release or "0" is determined in advance. Then, the setting detection means (1) detects that the setting code "1" is written in the designated bit C ₇ that determines the setting / release, and the release detection means (2) detects the setting bit C. _It is detected that the release code "0" is written in ₇ .
Then, the identifying means (4) sets / sets each signal line (d _{0 to} d ₆ ).
Identify whether or not there is a cancellation instruction. And the output means (5)
The result of detection (1, 2) of the setting or cancellation and each signal line (d _{0 to} d ₆ )
Set or cancel the value specified for the specified signal line among the multiple signal lines (d _{0 to} d ₆ ) according to the result of identification (4) of the presence or absence of the setting or cancellation instruction for each. Output. Therefore, the register of the present invention does not require the ON / OFF processing of the "1/0" write processing that involves the logical operation by the control program of the MPU as in the conventional example, and does not require a plurality of signal lines.
Each signal line (d _{0 to} d ₆ ) is independent of other signal lines by "1 /
It is possible to perform ON / OFF processing of the write processing of 0 ".

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle diagram of FIG. 1 shows the basic structure of the register of the present invention as it is, and FIG. 2 shows an example of the circuit structure of the embodiment. In FIG. 1, the C ₇ bit of the register of the present invention is “setting“ 1 ”/ release of 7 signal lines (7 bit output data) of output, d _{0 to} d ₆ of each signal line (bit). "0""a designated bit that controls, when the designated bit C ₇ is" 1 ", performs an operation of" setting "of the signal line d ₀ to d _6, designated bits C ₇ is" 0 "
At the time of, the operation of "release" is performed. Also, b _{0 to} b ₆ is 7 bi
a bit "generic data" t, when the "0" is written, for example, b ₁ of a certain bit therein do not give a change to output bits d ₁ applicable, to b ₁ "1" When is written, the corresponding bit d ₁ of the output is changed to “1 (set)” or “0 (release)” by setting “1” of the designated bit C ₇ of “set / release”. When “set” is instructed repeatedly for the bit b ₁ which is already “1 (set)”, the bit b ₁ is not changed as a result. The same applies to the duplication of "0 (release)". In FIG. 2, the output circuit from which the register of the present invention outputs a value ("1" or "0") is a typical "RS (reset set) flip-flop FF". The registers b _{0 to} b ₆ and C ₇ of the present invention have "setting / setting".
The output of the designated bit C ₇ of `` release '' is detected by the detection circuit.
When was the "setting" 1 "" is output as the detection output of the specified bit C ₇ becomes "1". If the output of the designated bit C ₇ is “released“ 0 ”” by the inverting circuit INV of the detection circuit, the designated bit C ₇
The inverted output of the output of is "1". The "identifying means for detecting the presence / absence of a significant write instruction" provided for each "general-purpose data" bits b _{0 to} b ₆ has a "1" as the output or inverted output signal and a "general-purpose data bit d ₀
Bits b ₁ corresponding to the example data bit d ₁ in the to d ₆ "
Is "1", "1" is given to the set terminal S or reset terminal R of RS-FF of the output circuit of the data bit d ₁ , and the output Q of the RS-FF is set to "1". (Set) or 0 (cancel).

[0009]

As described above, according to the register of the present invention, the output terminal of each bit of the general-purpose I / O which requires setting of mutually independent values ("1" or "0"), When controlling with registers arranged at the same address in the sense that data can be written in a single write operation, the MPU can set / cancel each bit without increasing the circuit scale of the accommodated IC.
It becomes possible to perform the control program at high speed, reduce the program size, and eventually provide hardware that makes it easy to create a program, without performing logical operation processing such as Is obtained.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a register that can be set for each bit of the present invention.

FIG. 2 is a circuit configuration diagram of a register according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a circuit configuration example of a register according to a conventional technique.

FIG. 4 is a diagram of another circuit configuration example of a register according to the related art.

FIG. 5 is a diagram illustrating a configuration example of a control circuit when controlling a plurality of signal lines via a conventional register.

[Explanation of symbols]

b _{0 to} b ₆ are general-purpose data bits (7 bits) written by the MPU, C ₇ is a “setting / releasing” designation bit, d _{0 to} d ₆ are output signal lines (7 lines), and output data bits (7 b
it), is a detection circuit that detects that the designated bit C ₇ is the setting code "1", is a detection circuit that detects that the designated bit C ₇ is a release code "0", is the output of the designated bit C ₇ ,
Is an identification circuit for detecting the presence / absence of designation of “setting / cancellation” for each written data bit b _{0 to} b ₆ , and is an output circuit of the register.

Claims (1)

[Claims] 1. Each signal of the same plurality of signal lines (d _{0 to} d ₆ ) through a register in which a plurality of bits (b _{0 to} b ₆ ) are arranged at the same address and which can be written by a single write operation by the MPU. In a register that can be set for each bit of a device that independently controls ON / OFF of lines, setting or canceling each signal line of the plurality of signal lines (d _{0 to} d ₆ ). One or a plurality of designated bits (C ₇ ) for designating one of the operations in advance, and a means for detecting that a predetermined setting code ("1") is written in the designated bit (C ₇ ) ( 1), the designated bits and (means for detecting that the predetermined release code to C ₇₎ ( "0") is written (2), the plurality of signal lines (d ₀ to d
Identification means for identifying which signal line in ₆ ) is instructed to perform the setting or cancellation operation
(4), the result of detection (1, 2) of the setting or cancellation and each signal line
accordance with the result of (d ₀ to d ₆₎ for each of the setting or the presence of release of the order identification (4), specified in the designated signal lines in the plurality of signal lines (d ₀ to d ₆₎ A register which can be set for each bit, comprising an output means (5) for setting or releasing a value and outputting the value.