JPH0736666A - Digital signal processor - Google Patents

Abstract

PURPOSE:To avoid the arithmetic error due to overflow by scaling a first and second digital data by prescribed scale amount corresponding to the maximum value and the arithmetic contents and inputting the data in an arithmetic unit. CONSTITUTION:In a scaling part 3.3, the digital data of each bus line 1.2 is inputted via an IMDCT(Imversed Modified Discrete Cosine Transformer) transforming device 6.6 and a scaling operation is performed based on the scale amount stored in a storage part 5. Namely, a scaling part 3 preliminarily performs a bit shift for the digital data before a calculation on the side of an LSB(Least Significant Bit) in order to avoid an overflow when the digital data for which the IMDCT is performed in the IMDCT transforming device 6 has a possibility of overflowing. This scaled data to be calculated is inputted in the IMDCT transforming device 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DSP (Digital Signal Processor) having a fixed data length, which is used in an arithmetic unit incorporated in a digital audio device such as a mini disk to calculate and integrate digital data. The present invention relates to a digital signal processing device used.

[0002]

2. Description of the Related Art Conventionally, in a mini disk for recording and reproducing an audio signal by a magneto-optical method, digital data which is a PCM (Pulse Code Modulation) signal obtained by digitizing an audio signal is converted into two band division filters (Quadrature Mirror). Filter: Hereinafter referred to as QMF)
Is used to divide into digital data representing audio signals in three bands, and these digital data are data-compressed and recorded.

After that, in the mini disc, each digital data representing the audio signals in the above three bands is converted from a time axis to a frequency axis by MDCT (Modified Discrete Cosine).
Data is recorded on a magneto-optical disk by converting it into a spectrum signal by using a transformer or the like and compressing the data.

In reproducing such a mini disc, the recorded spectrum signal of each band is read out from the mini disc and subjected to inverse conversion, that is, IMDCT (Imversed).
Modified Discrete Cosine Transformer) After conversion, etc., respective digital data representing audio signals in three bands are obtained, and then the respective digital data are band-integrated into PCM signals representing audio signals.
The signal is converted into an audio signal and reproduced as sound.

In the above IMDCT conversion, integrated digital data is obtained by operating using a DSP having a fixed data length of, for example, 24 bits, and the operation shown in the following equation (1) is obtained. Is done.

[0006]

[Equation 1]

However, X (k) represents an input spectrum signal, M represents the number of data in block units for IMDCT conversion, and y (n) represents IMDCT converted digital data. Also, 0 ≦ n <2M.

When the above formula (1) is calculated, the formula (1) can be calculated in order by dividing it into the following four processing steps [a] to [d]. That is, [a] u (k) definition: u (k) is defined as follows: When 0 ≦ k <M / 2 u (k) = X (2k) ...... (2 _-1 ) M / 2 When ≦ k <M u (k) = -X (2M-1-2k) (2 _-2 ) Further, Z (L) is defined as follows Z (L) = {u (2L) + Iu (2L + 1)} W _M ^L (3) where 0 ≦ L <M / 2 W _M ^L = exp (-i · 2πL / M) The above W _M ^L represents a rotation operator and is a vector Is an operator that rotates the input complex number represented by by 2πL / M clockwise on the complex plane. Further, i is an imaginary unit.

[B] FFT (Fast Fourier Transform)
: Perform fast Fourier transform of Z (L)

[0010]

[Equation 2]

However, 0 ≦ n <M / 2 [U] u (n) definition: u (n) is defined as follows: u (n) = a ₀ * Real (Z (n)) + a ₁ * Real (Z (M / 2-1-n)) ＋ a ₂ * Img (Z (n)) ＋ a ₃ * Img (Z (M / 2-1-n)) …… (5 _-1 ) u (M- 1-n) = a ₂ * Real (Z (n))-a ₃ * Real (Z (M / 2-1-n))-a ₀ * Img (Z (n)) + a ₁ * Img (Z ( M / 2-1-n)) ...... (5 -2) where, 0 ≦ n <M / 2 a 0 = (C 8M 2k + 1 -S 8M 5 (2k + 1)) / 2 a 1 = ( C _8M ^{2k + 1} + S _8M ^{5 (2k + 1)} ) / 2 a ₂ = (S _8M ^{2k + 1} + C _8M ^{5 (2k + 1)} ) / 2 a ₃ = (-S _8M ^{2k + 1} + C _8M ^{5 ( 2k + 1)} ) / 2 C _q ^p = cos (2π ^p / q) S _q ^p = sin (2π ^p / q) [D] post processing: Calculate y (n) as follows: 0 ≦ n <M / When 2 y (n) = u (n + M / 2) ...... (6 _-1 ) M / 2 ≤ n <3 M / 2 y (n) = -u (3M / 2-1-n) ...... (6 _-2 ) When 3M / 2 ≤ n <2M y (n) = -u (n-3M / 2) ...... (6 _-3 ) Use the formula (1) above [a] to [d]. ], And calculate in order , IMDC using a DSP
The T transform is calculated.

[0012]

However, the above-mentioned conventional structure has a problem that the following calculation error occurs when the digital data is calculated using the fixed length DSP.

That is, in the above mini disc, the data values of the digital data to be operated are standardized so as to be distributed between -1 and 1, and the data length to be quantized is 24 bits or 16 bits. A bit has been adopted. However, in this specification, in order to simplify the notation of the description, description will be given with a data length of 8 bits. Generally, in hexadecimal notation (hereinafter referred to as hex), the first bit is used as a sign bit, 0 represents a positive number, 1 represents a negative number, and digital data d (0 ≦ d <1) is represented by 7 It is displayed in bits, and its maximum value is displayed as 7F in hexadecimal. Here, in order to explain the reason why the calculation error occurs, a calculation example using the following equations (7) and (8) will be described.

72 (hex) +2 (hex) = 74 (hex) ... (7) 72 (hex) +11 (hex) = 83 (hex) ........ (8) In the case of the formula (7), after calculation Digital data of 74 (hex)
Since it can be displayed with 7 bits, there is no problem, but in the case of formula (8), the digital data 83 (hex) after calculation is
Since it is larger than 7F (hex), it cannot be displayed with 7 bits. That is, when the data length is 7 bits, overflow occurs and the first bit that is the sign bit becomes 1. Therefore, although the positive numbers are added together, the digital data after calculation becomes a negative number in the 2's complement display. , The calculation result will be inaccurate.

Therefore, when there is a possibility that the digital data after calculation may overflow,
The digital data before calculation (hereinafter, referred to as data to be calculated) is bit-shifted to the LSB (Least Significant Bit) side (hereinafter, referred to as right side) respectively, and then the calculation is performed to avoid overflow. That is,
A so-called rightward scaling operation (hereinafter referred to as scaling) is performed.

For example, when the addition is performed once as in the above equation (8), the number of bits of the digital data after the calculation may increase by one, so that it is the data to be calculated. Overflow can be avoided by prescaling 72 (hex) and 11 (hex) by 1 bit.

However, if the margin bit is provided by 1 bit by scaling in this way, the operated data is displayed in 6 bits, so that the accuracy of the operation is inevitably lowered and the operation error increases. Therefore, in order to minimize the calculation error, it is necessary to minimize the number of margin bits for avoiding overflow.

Here, in performing the IMDCT conversion, in order to avoid an overflow, in the above-mentioned four processing steps [A] to [E], it is determined how many extra bits are needed. . However, in order to obtain the number of bits of the margin bits, it is necessary to obtain a multiplication factor for the digital data after the operation with respect to the operated data.

First, in the processing step [A] described above, the magnification of digital data after calculation with respect to the data to be calculated (hereinafter simply referred to as magnification) is obtained. Formula (2 _-1 ) above
Since (2 _-2 ) simply rearranges the data to be calculated, no scaling is necessary. On the other hand, the left-hand side of equation (3), i.e., Z (L) is a right-hand side of u (2L) and u (2L + 1) is maximum, and by rotating the operator ^{_{W M L u (2L) +}} iu (2L + 1)
Is the maximum when overlaps the real axis or the imaginary axis on the complex plane, and the magnification at that time is √2.

Next, the magnification is calculated for the processing step [a] above. That is, the fast algorithm is applied to the above equation (4) to perform the log ₂ (M / 2) stage butterfly operation. For example, if the number of data M in equation (4) is 32, log ₂ (32 /
Since 2) = 4, the number of FFT stages in the butterfly operation is four. The above butterfly operation is an operation to obtain output complex numbers D and E by multiplying the input complex numbers A and B by a multiplication operation between two terms, and the following equation (9 _-1 )
_-Represented by (9 _-2 ).

D = A + B * W ^b ...... (9 ₋₁ ) E = A−B * W ^b …… (9 ₋₂ ) However, the above rotation operator W ^b is the number of data M in the formula (4).
, Which is an operator that rotates an input complex number represented by a vector clockwise by 2πb / M on the complex plane.

Here, in the above butterfly operation,
It is known that b = 0 in the first stage of the FFT, b = 0, 4 in the second stage, and b = 2 in the third and subsequent stages. Therefore, FF
In the first stage of T, the input complex number B is set to 0 on the complex plane.
Only rotate clockwise (that is, do not rotate). In the second stage of FFT, when b = 4, the input complex number B
Is rotated clockwise by π / 2 on the complex plane, while the input complex number B is not rotated when b = 0. Further, in the third and subsequent stages of the FFT, the input complex number B is rotated clockwise by π / 4 on the complex plane.

As is clear from the relationship between the input complex numbers A and B and the output complex numbers D and E in the first, second, and third stages of the FFT, the first, second, and Third
The magnifications after the steps are 2 times, 2 times, and 1 + √2 times in this order.

Then, the magnification is calculated for the processing step [c] above. In the above formulas ( _5-1 ) and ( _5-2 ),
The maximum value of | a ₀ | + | a ₁ | + | a ₂ | + | a ₃ | is 2
Therefore, the magnification of u (x) with respect to Z (x) is 2 times at maximum.

Next, the magnification is calculated for the processing step [d] above. The above formula ( _6-1 ) ・ ( _6-2 ) ・ ( _6-3 )
Does not require scaling, because the data to be calculated is simply rearranged, and the scaling factor is 1.

Next, the size of the digital data after IMDCT conversion with respect to the size of the data to be calculated is calculated from the magnifications obtained in the respective processing steps [A] to [D]. For example, if the number of data M in equation (4) is 32,
When all of the above magnifications are integrated, √2 * 2 * 2 * (1 + √2) ² * 2 * 1 ≈ 65.94, and the size of the digital data after IMDCT conversion is the size of the calculated data. The maximum is about 66 times. Since 2 ⁶ <65.94 <2 ⁷ , the maximum number of spare bits for avoiding overflow is 7 bits.

However, the margin bit is set to 7 in this way.
If bits are provided, for example, when 16 bits are used for the data length, the first bit is used as a sign bit, so 16-7-1 = 8, and the digital data d (0
≤d <1) must be represented by 8 bits.

Therefore, when a fixed-length DSP is used for calculation, if the number of margin bits is determined only by the size of the digital data after IMDCT conversion with respect to the size of the data to be calculated, the number of bits of the digital data d is determined. Therefore, there is a problem in that the calculation error becomes large because of the small number.

Although it is conceivable to use a DSP having a variable data length in order to reduce the above-mentioned calculation error, a variable length DSP is more expensive than a fixed length DSP. This causes another problem that the cost of the digital signal processing device is increased.

The present invention has been made in view of the above problems, and an object thereof is a fixed-length D which can reduce the cost.
An object of the present invention is to provide a digital signal processing device capable of reducing calculation error by using SP.

[0031]

In order to solve the above-mentioned problems, a digital signal processing device according to the invention of claim 1
Digitized and standardized first and second digital data are input, and the first and second digital data are calculated by calculating the data length with a fixed length,
In a digital signal processing device provided with an arithmetic unit that integrates and outputs third digital data, the first and second digital data are scaled by a predetermined scale corresponding to the maximum value of the digital data and the content of the calculation. It is characterized in that a scaling means is provided for scaling by an amount and inputting to the arithmetic unit.

In order to solve the above-mentioned problems, a digital signal processing apparatus according to a second aspect of the present invention is the digital signal processing apparatus according to the first aspect, further comprising storage means for storing the scale amount in advance. It is characterized by being.

According to a third aspect of the present invention, there is provided a digital signal processing apparatus according to the second aspect, wherein the scale amount stored in the storage means is the first scale. And the maximum value of the second digital data, and the maximum value of the third digital data.

[0034]

According to the structure of claim 1, the first and second
The digital data is scaled by the scaling means by a predetermined scale amount corresponding to the maximum value of the digital data and the content of the computation, and then input to the computing unit.

Therefore, it is possible to avoid the overflow that occurs in the third digital data obtained by calculating and integrating the first and second digital data with the arithmetic unit.
Moreover, since the first and second digital data are scaled by a predetermined scale amount, it is possible to suppress a decrease in the number of bits of the digital data.

As a result, the above-mentioned configuration can avoid the calculation error resulting from the overflow and reduce the calculation error resulting from the decrease in the number of bits of the digital data. Can be reduced. Therefore, it is possible to obtain an operation result that is closer to the true value than before by using an arithmetic unit having a fixed data length. Further, since the error of the calculation result can be reduced by using the arithmetic unit having the fixed data length, it is not necessary to use the variable length arithmetic unit to reduce the arithmetic error, and the variable length arithmetic unit is used. It is possible to avoid the cost increase.

According to the second aspect of the present invention, the scale amount for scaling the first and second digital data is stored in the storage means in advance.

Therefore, when scaling the first and second digital data by the scaling means, it is not necessary to perform an operation for obtaining the scale amount. As a result, the number of calculations for obtaining the calculation result can be reduced, so that the calculation time can be shortened and the cost increase can be avoided.

According to the third aspect of the present invention, the scale amount stored in the storage means is set based on the maximum values of the first and second digital data and the maximum value of the third digital data. .

As a result, since the optimum scale amount corresponding to the first and second digital data can be stored in the storage means, the error of the obtained calculation result can be further reduced.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention is shown in FIGS.
The explanation is based on the following.

The digital signal processing device according to the present invention is
For example, like a mini disk that records and reproduces an audio signal by a magneto-optical method, it is divided into a plurality of band data, and each band data is MDCT (Modified Discrete Cosi).
IMDCT (Imversed Modified)
Discrete Cosine Transformer) Used when converting.

As shown in FIG. 1, the digital signal processing device is a bus line 1.2, a scaling unit 3.3, a scale amount determination unit 4, a storage unit 5, an IMDCT converter 6.6, and a band integrated filter. QMF (Quadrature Mirror Fi
lter) 7 and bus line 8. Digital data (first and second digital data) indicating audio signals of different bands are respectively provided on the bus lines 1 and 2.
Is entered.

Each data value x of the digital data input to each of the above bus lines 1 and 2 is defined by the mini disk standard, and is set in the range of 2 ^-5 <x <2 ¹⁶ Each data value x is represented by, for example, 24 bits or 16 bits. The leading bit is used as a sign bit. Incidentally, as the display of the negative number, one's complement display or two's complement display can also be used.

Digital data of each bus line 1 and 2 is input to the above-mentioned scaling unit (scaling means) 3 3 via the IMDCT converter 6 6. These scaling units 3 and 3 are based on the scale amount stored in the storage unit 5, so-called scaling operation (hereinafter,
An operation called "scaling" is performed. That is,
The scaling unit 3 uses the IMDCT converter 6 for IMDCT
When the converted digital data has a possibility of causing an overflow, in order to avoid the overflow, the digital data before the operation (hereinafter referred to as the operated data) is LSB (Least Significant Bit) in advance.
Scaling for bit shifting to the side (hereinafter, referred to as the right side) is performed. Also, the scaling unit 3
The processed data scaled in is input to the IMDCT converter 6.

Digital data of the bus lines 1 and 2 is input to the IMDCT converters 6 and 6, respectively. These IM
The DCT converters 6 and 6 IM the above digital data
DCT transform and output to QMF7.

Each of the IMDCT converters 6 and 6 is provided in the QMF 7.
Is input with the IMDCT-converted digital data. The QMF 7 calculates each digital data and band-integrates it, and outputs the digital data showing the audio signal of the entire band to the bus line 8. The digital data (third digital data) output to the bus line 8 is PCM (Pulse Co
de Modulation) signal, which is made into 16-bit digital data according to the standard of the mini disk. The IMDCT converters 6 and 6 and the QMF 7 constitute a computing unit.

The storage unit (storage means) 5 is a ROM (Read O
nly Memory) and RAM (Random Access Memory), and is connected to the scale amount determination unit 4. The storage unit 5 stores a scale amount obtained in advance for each processing stage described below.

The scale amount determining unit 4 is a scaling unit 3.
・ Connected to 3. The scale amount determination unit 4 is
When performing scaling in the scaling units 3 and 3, how many bits should be read out from the storage unit 5 for the size of the data to be operated and the optimum scale amount corresponding to each processing stage. To decide.

In the above structure, the IMDCT converter 6 has a data length D set to a fixed length of, for example, 24 bits.
In SP (Digital Signal Processor), the calculation shown in the following equation (1) is performed.

[0051]

[Equation 3]

Here, X (k) represents an input spectrum signal, M represents the number of data in block units for IMDCT conversion, and y (n) represents IMDCT-converted digital data. Also, 0 ≦ n <2M.

When calculating the above equation (1), the calculation shown in FIG.
As shown in, the equation (1) can be calculated in order by dividing it into four processing steps [A] to [E]. That is, [a] u (k) definition: u (k) is defined as follows: When 0 ≦ k <M / 2 u (k) = X (2k) ...... (2 _-1 ) M / 2 When ≦ k <M u (k) = -X (2M-1-2k) (2 _-2 ) Further, Z (L) is defined as follows Z (L) = {u (2L) + Iu (2L + 1)} W _M ^L (3) where 0 ≦ L <M / 2 W _M ^L = exp (-i · 2πL / M) The above W _M ^L represents a rotation operator and is a vector Is an operator that rotates the input complex number represented by by 2πL / M clockwise on the complex plane. Further, i is an imaginary unit.

[B] FFT (Fast Fourier Transform)
: Perform fast Fourier transform of Z (L)

[0055]

[Equation 4]

However, 0 ≦ n <M / 2 [C] u (n) definition: u (n) is defined as follows: u (n) = a ₀ * Real (Z (n)) + a ₁ * Real (Z (M / 2-1-n)) ＋ a ₂ * Img (Z (n)) ＋ a ₃ * Img (Z (M / 2-1-n)) …… (5 _-1 ) u (M- 1-n) = a ₂ * Real (Z (n))-a ₃ * Real (Z (M / 2-1-n))-a ₀ * Img (Z (n)) + a ₁ * Img (Z ( M / 2-1-n)) ...... (5 -2) where, 0 ≦ n <M / 2 a 0 = (C 8M 2k + 1 -S 8M 5 (2k + 1)) / 2 a 1 = ( C _8M ^{2k + 1} + S _8M ^{5 (2k + 1)} ) / 2 a ₂ = (S _8M ^{2k + 1} + C _8M ^{5 (2k + 1)} ) / 2 a ₃ = (-S _8M ^{2k + 1} + C _8M ^{5 ( 2k + 1)) / 2 C} q p = cos (2πp / q) S q p = sin (2πp / q) [d] post Processing: y (n) is calculated as follows: 0 ≦ n <M / When 2 y (n) = u (n + M / 2) ...... (6 _-1 ) M / 2 ≤ n <3 M / 2 y (n) = -u (3M / 2-1-n) ...... (6 _-2 ) When 3M / 2 ≤ n <2M y (n) = -u (n-3M / 2) ...... (6 _-3 ) Use the formula (1) above [a] to [d]. ] In order to calculate in order by dividing into four processing steps Ri, IMDC using a DSP
The T transform is calculated.

Next, how to obtain the scale amount to be stored in the storage unit 5 in advance will be described as follows. First, it is necessary to find a multiplication factor for the digital data after calculation with respect to the data to be calculated.

First, in the above processing step [A], the scaling factor of digital data after computation with respect to the data to be computed (hereinafter referred to simply as scaling factor) is determined. Formula (2 _-1 ) above
Since (2 _-2 ) simply rearranges the data to be calculated, no scaling is necessary. On the other hand, as is clear from the complex plane shown in FIG. 3, the left side of equation (3), that is, Z
(L) has the maximum u (2L) and u (2L + 1) on the right side, and
The rotation operator W _M ^L maximizes u (2L) + iu (2L + 1) when it overlaps the real axis or the imaginary axis on the complex plane, and the magnification at that time is √2.

Next, the magnification is obtained for the processing step [a] above. That is, the fast algorithm is applied to the above equation (4) to perform the log ₂ (M / 2) stage butterfly operation. For example, if the number of data M in equation (4) is 32, log ₂ (32 /
Since 2) = 4, the number of FFT stages in the butterfly operation is four. Note that the above butterfly operation is as shown in FIG.
As shown in (4), the output complex numbers D and E are obtained by multiplying the input complex numbers A and B between the two terms, and the signal flow is expressed by the following equations (9 ₋₁ ) · (9 _-2 )
It is represented by.

D = A + B * W ^b ...... (9 _-1 ) E = A-B * W ^b ...... (9 _-2 ) However, the above rotation operator W ^b is the number of data M in the formula (4).
, Which is an operator that rotates an input complex number represented by a vector clockwise by 2πb / M on the complex plane.

Here, in the above butterfly operation,
It is known that b = 0 in the first stage of the FFT, b = 0, 4 in the second stage, and b = 2 in the third and subsequent stages. Therefore, FF
In the first stage of T, the input complex number B is set to 0 on the complex plane.
Only rotate clockwise (that is, do not rotate). In the second stage of FFT, when b = 4, the input complex number B
Is rotated clockwise by π / 2 on the complex plane, while the input complex number B is not rotated when b = 0. Further, in the third and subsequent stages of the FFT, the input complex number B is rotated clockwise by π / 4 on the complex plane.

The relationships between the input complex numbers A and B and the output complex numbers D and E in the first, second and third stages of the above FFT are shown in this order in FIGS. 5, 6 and 7. As is apparent from the complex planes shown in FIGS. 5 to 7, the magnifications in the first, second, and third stages of the FFT are 2 times, 2 times, and 1 + √2 times in this order.

Subsequently, the magnification is calculated for the processing step [c] above. In the above formulas ( _5-1 ) and ( _5-2 ),
The maximum value of | a ₀ | + | a ₁ | + | a ₂ | + | a ₃ | is 2
Therefore, the magnification of u (x) with respect to Z (x) is 2 times at maximum.

Then, the magnification is calculated for the processing step [d] above. The above formula ( _6-1 ) ・ ( _6-2 ) ・ ( _6-3 )
Does not require scaling, because the data to be calculated is simply rearranged, and the scaling factor is 1.

Next, the size of the digital data after IMDCT conversion with respect to the size of the data to be calculated is calculated from the magnifications obtained in the respective processing steps [A] to [D]. For example, if the number of data M in equation (4) is 32,
When all of the above magnifications are integrated, √2 * 2 * 2 * (1 + √2) ² * 2 * 1 ≈ 65.94, and the size of the digital data after IMDCT conversion is the size of the calculated data. The maximum is about 66 times. Table 1 shows the magnifications obtained for each of the processing steps [a] to [d] above.

[0066]

[Table 1]

Next, the ratio of the operated data to the digital data after the operation is obtained. However, it is not necessary to obtain the above ratio in the above processing step [A] for the reason described later.

The ratio of the data to be processed with respect to the digital data after the calculation (hereinafter, simply referred to as the ratio) in the processing step [a] is calculated. The above formula (9 _-1 )
From ( _9-2 ), A = (D + E) / 2 ... ( _10-1 ) B = (D-E) * W- ^b / 2 ... ( _10-2 ) is obtained. Therefore, as is apparent from the complex plane shown in FIG. 8, in the first and second stages of the FFT, b = 0, D
= -E, input complex number B for output complex number D, E
Is the maximum, and its value is 1. The ratio of the input complex number A at that time is zero. Further, as is clear from the complex plane shown in FIG. 9, in the third and subsequent stages of the FFT, when b = 2 and D = −E, the ratio of the input complex number B to the output complex numbers D and E becomes maximum, and its value Is √2. The ratio of the input complex number A at that time is zero.

Next, the ratio is calculated for the processing step [c] above. In the above formulas ( _5-1 ) and ( _5-2 ),
When n = M / 2-1-n, the following equations (11 _-1 ) · (11 _-2 ) are obtained.

U (M / 2-1-n) = a ₁ * Real (Z (n)) + a ₀ * Real (Z (M / 2-1-n)) + a ₃ * Img (Z (n)) + A ₂ * Img (Z (M / 2-1-n)) ...... (11 _-1 ) u (M / 2 + n) = -a ₃ * Real (Z (n)) + a ₂ * Real (Z ( M / 2-1-n)) + a ₁ * Img (Z (n))-a ₀ * Img (Z (M / 2-1-n)) (11 _-2 ) where 0≤n <M / 2 The above four expressions (5 _-1 ) ・ (5 _-2 ) ・ (11 _-1 ) ・ (11
_-2 ) gives the following equation (12).

[0071]

[Equation 5]

When this equation (12) is transformed, the following equation (1)
3) is obtained.

[0073]

[Equation 6]

However, K = a ₀ ² + a ₁ ² + a ₂ ² + a ₃ ² = 1 and the maximum value of | a ₀ | + | a ₁ | + | a ₂ | + | a ₃ | , U (x) to Z (x) has a maximum ratio of 2.

Next, the ratio is calculated for the processing step [d] above. The above formula ( _6-1 ) ・ ( _6-2 ) ・ ( _6-3 )
Since the operand data is simply rearranged, the ratio is 1. Table 2 shows the ratios obtained for each of the above processing steps [A] to [D].

[0076]

[Table 2]

Next, [a]-
The size of the data to be operated and the optimum scale amount corresponding to each processing step are determined based on each magnification and each ratio in the four processing steps [D] and the following three conditions. The above conditions are as follows: Each data value x of the digital data input to the bus lines 1 and 2 is defined by the standard of the mini disk, and is set in the range of 2 ^-5 <x <2 ¹⁶ There is. Therefore, the data value x of the digital data input to the bus lines 1 and 2 is 2 ¹⁶ at maximum.

Condition: Each data value of the digital data output from the IMDCT converter 6 is specified by the mini disk standard, and is a maximum of 2 ¹⁵ .

Conditions: From the above conditions and conditions, and the above magnifications and ratios, there is a maximum value in the data value of digital data at each processing stage in IMDCT conversion.

From the above-mentioned three conditions and the respective magnifications and the respective ratios, the envelope curve representing the maximum value at each processing stage when the data value of the digital data input to the IMDCT converter 6 is 2 ^16. Ask for. Next, how to obtain the envelope curve representing the maximum value will be described below with reference to the graphs of FIGS. 10 and 11.

In the graphs of FIGS. 10 and 11, the points on the upper line surrounding each processing stage name indicate the maximum value input to that processing stage, and the points on the lower line surrounding each processing stage name. Indicates the maximum value output from the processing stage.

First, it will be described how the maximum value (hereinafter referred to as the maximum data value) of the data value of the digital data input to the IMDCT converter 6 changes based on each of the above magnifications and each ratio. To do.

In FIG. 10, a polygonal line g is a polygonal line representing a change in the maximum data value as seen from the input side of the IMDCT converter 6. For example, the maximum data value input in the processing stage [A] is 2 ¹⁶ , and the magnification in the processing stage [A] is √2.
Since it is doubled, the maximum value of the data output from the processing stage [A] is 2 ¹⁶ * √2 = 2 ^16.5 .

On the other hand, the polygonal line h is a polygonal line representing the change in the maximum data value seen from the output side of the IMDCT converter 6, and I
The maximum data value after MDCT conversion is set to 2 ¹⁵ . However, since each of the above-mentioned ratios is a value obtained by calculating the size of the data to be calculated with respect to the digital data after the calculation, the reciprocal of the ratio (for example, the reciprocal of √2 is 1 / √2) is used on the graph. expressed.

Since the data maximum value viewed from the input side of the IMDCT converter 6 and the data maximum value viewed from the output side of the IMDCT converter 6 must match with each other, the first step in the processing step [a] above is performed. In the step, the polygonal line g and the polygonal line h intersect. Then, by obtaining the envelopes of the polygonal line g and the polygonal line h, the envelope of the maximum data value input to the IMDCT converter 6 is obtained as shown in FIG. As described above, since the polygonal line g and the polygonal line h intersect at the first stage of the above-mentioned processing step (a), it is not necessary to obtain the ratio for the above-mentioned processing step (a). Become.

Then, from the envelope of the data maximum value thus obtained, the optimum scale amount when the data maximum value input to the IMDCT converter 6 is 2 ¹⁶ can be determined.

Next, a method of determining the scale amount from the envelope of the maximum data value will be described below with reference to FIG. In the following description, the data length of the operand data is set to 24 bits and the decimal point position is LSB (Least Significant Bit), as shown in FIG.
), It is the 6th bit.

First, as an initial shift, the most significant 1 is placed in the bit next to the sign bit (the 22nd bit from the LSB).
, The operand data is scaled to the left. For example, when the maximum data value is 2 ¹⁴ , the operand data is scaled to the left by 2 bits. this,
By so-called left scaling, the data bits can be effectively used and the calculation accuracy can be improved. If the maximum data value is 2 ¹⁶ ,
There is no need for scaling because a bit next to the sign bit is already set to 1.

Next, in the processing stage [A] described above, FIG.
As is clear from the graph of No. 1, the maximum value of the data after processing is √2 times the maximum value of the data before processing.
From this, in order to avoid the overflow of digital data in the IMDCT converter 6, it is only necessary to scale the operand data by 1 bit to the right. That is, the scale amount before the processing step [A] is determined to be 1.

Subsequently, in the first stage of the processing step [a], the maximum data value after processing is √2 times the maximum data value before processing. However, as is clear from the graph in the figure, the maximum data value after the above first-stage processing is √2 * √2 = 2 times the maximum data value before the processing step [A]. And, since the operand data has already been scaled to the right by one bit before the processing step [A], it is not necessary to scale it here. That is, the scale amount before the first stage of the processing stage [a] is determined to be 0.

Further, in the second stage of the processing stage [A], the maximum data value after the processing is at most one time the maximum data value before the processing. Therefore, the scale amount before the second stage of the processing stage [a] is determined to be 0.

Similarly, as is apparent from the graph of FIG. 11, the data maximum value after the fourth step of the processing stage [a] is the data maximum value before the third step (that is, after the second step). The maximum value is (1 / √2) * (1 / √2) = 1/2. Therefore, in order to effectively utilize the data bits, it is sufficient to scale the digital data after the fourth stage, that is, the digital data before the processing step [C], by one bit to the left. That is, the scale amount before the third step and the fourth step before the processing step [a] is 0, [c]
The scale amount before the processing step of is determined to be -1.

In the processing stage [C], the maximum value of the data after the processing is 1/2 the maximum value of the data before the processing.
Doubled. Further, in the processing stage [D], the maximum value of data after processing is at most 1 time the maximum value of data before processing. Therefore, the scale amount before the processing step [d] is -1.
Is decided.

As described above, it is possible to determine the optimum scale amount in each processing step [a] to [d] in the IMDCT conversion from the envelope of the maximum data value.

The envelope of the data maximum value when the data maximum value input to the IMDCT converter 6 is 2 ¹⁵ obtained in the same manner as above is shown in FIG. 12 and when the data maximum value is 2 ¹⁴ . FIG. 13 shows an envelope curve, FIG. 14 shows an envelope curve when the maximum data value is 2 ¹³ , FIG. 15 shows an envelope curve when the maximum data value is 2 ¹² and when the maximum data value is 2 ^11. FIG. 16 shows the envelope curve of FIG. 16, the envelope curve when the maximum data value is 2 ¹⁰ is shown in FIG. 17, and the envelope curve when the maximum data value is 2 ⁹ is shown in FIG. Incidentally, as mentioned in the above conditions, the maximum data value input to the IMDCT converter 6 is 2 ^-5 a minimum. However, if the data maximum is 2 ⁸ or less, the envelope has a data maximum of 2 ⁹
It has the same shape as the envelope curve. Therefore, the illustration of the envelope when the maximum data value is 2 ⁸ to 2 ⁻⁵ is omitted.

Table 3 summarizes the optimum scale amounts determined in the same manner as above in each of the processing steps [a] to [d] when the maximum data value is 2 ¹⁶ to 2 ^-5. Indicate.

[0097]

[Table 3]

As shown in FIG. 1, each of the above scale amounts is stored in advance in the storage unit 5, and the scale amount determination unit 4
Reads out from the storage unit 5 an optimum scale amount corresponding to the maximum data value of the data to be input to the scaling unit 3.3 and each processing step [A] to [D]. Then, the scaling units 3 and 3 perform scaling based on the scale amount stored in the storage unit 5.

As described above, in the digital signal processing device having the above-described configuration, the scaling unit 3.3 sets the data to be processed into the data maximum value of this data to be processed and the contents of the calculation at each processing stage in the IMDCT conversion. After scaling by a corresponding predetermined scale amount, it is input to the IMDCT converter 6.

Therefore, it is possible to avoid the overflow that occurs in the processed data obtained by calculating and integrating the data to be calculated by the IMDCT converters 6 and 6.
Moreover, since the data to be calculated is scaled by a predetermined scale amount, it is possible to suppress a decrease in the number of bits of the digital data. As a result, the above-mentioned configuration can avoid the calculation error resulting from the overflow and reduce the calculation error resulting from the decrease in the number of bits of the digital data, thus reducing the error in the obtained calculation result. be able to. Therefore, it is possible to obtain a calculation result that is closer to the true value than before by using a DSP having a fixed data length. Further, since the error of the calculation result can be reduced by using the DSP having the fixed data length, it is not necessary to use the variable length DSP to reduce the calculation error, and the cost of using the variable length DSP is reduced. It is possible to avoid up.

Further, in the digital signal processing device having the above configuration, the storage unit 5 stores in advance a scale amount for scaling the data to be operated.

Therefore, when scaling the data to be calculated in the scaling unit 3.3, it is not necessary to perform the calculation for obtaining the scale amount. As a result, the number of calculations for obtaining the calculation result can be reduced, so that the calculation time can be shortened and the cost increase can be avoided.

Further, in the digital signal processing device having the above-mentioned configuration, the scale amount stored in the storage unit 5 is set based on the maximum data value of the processed data and the maximum data value of the processed data. There is.

As a result, the optimum scale amount corresponding to the data to be calculated can be stored in the storage unit 5,
The error of the obtained calculation result can be further reduced.

[0105]

As described above, the digital signal processing device according to the first aspect of the present invention sets the first and second digital data to a predetermined scale corresponding to the maximum value of the digital data and the content of the calculation. This is a configuration in which there is provided scaling means for scaling only the amount and inputting it to the arithmetic unit.

Therefore, it is possible to avoid the overflow that occurs in the third digital data obtained by calculating and integrating the first and second digital data with the arithmetic unit.
Moreover, since the first and second digital data are scaled by a predetermined scale amount, it is possible to suppress a decrease in the number of bits of the digital data. As a result, the above-mentioned configuration can avoid the calculation error resulting from the overflow and reduce the calculation error resulting from the decrease in the number of bits of the digital data, thus reducing the error in the obtained calculation result. be able to. Therefore,
It is possible to obtain an operation result that is closer to a true value than ever with an arithmetic unit having a fixed data length. Further, since the error of the calculation result can be reduced by using the arithmetic unit having the fixed data length, it is not necessary to use the variable length arithmetic unit to reduce the arithmetic error,
There is also an effect that it is possible to avoid an increase in cost due to using a variable-length arithmetic unit.

As described above, the digital signal processing apparatus according to the second aspect of the present invention is configured to include the storage means for storing the scale amount in advance.

Therefore, when scaling the first and second digital data by the scaling means, it is not necessary to perform an operation for obtaining the scale amount. As a result, the number of calculations for obtaining the calculation result can be reduced, so that the calculation time can be shortened and the cost increase can be avoided.

In the digital signal processing device according to the third aspect of the present invention, as described above, the scale amount stored in the storage means is the maximum value of the first and second digital data and the third digital data. The configuration is set based on the maximum value.

As a result, the optimum scale amount corresponding to the first and second digital data can be stored in the storage means, so that the error of the obtained calculation result can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating each processing step of IMDCT conversion executed by an IMDCT converter of the digital signal processing device.

FIG. 3 is a graph showing a complex plane for explaining the operation contents of a rotation operator.

FIG. 4 is an explanatory diagram illustrating the operation contents of a butterfly operation.

FIG. 5 is a graph showing a complex plane for explaining operation contents of butterfly operation.

FIG. 6 is a graph showing a complex plane for explaining operation contents of butterfly operation.

FIG. 7 is a graph showing a complex plane for explaining operation contents of butterfly operation.

FIG. 8 is a graph showing a complex plane for explaining the calculation contents of a butterfly calculation.

FIG. 9 is a graph showing a complex plane for explaining the calculation contents of butterfly calculation.

FIG. 10 is a graph showing changes in the maximum data value at each processing stage of IMDCT conversion.

FIG. 11 is a graph showing an envelope of the maximum data value at each processing stage of the IMDCT conversion when the maximum data value of the data to be calculated is 2 ¹⁶ .

FIG. 12 is a graph showing the envelope of the data maximum value at each processing stage of the IMDCT conversion when the data maximum value of the data to be calculated is 2 ¹⁵ .

FIG. 13 is a graph showing the envelope of the data maximum value at each processing stage of the IMDCT conversion when the data maximum value of the data to be calculated is 2 ¹⁴ .

FIG. 14 is a graph showing an envelope of the maximum data value at each processing stage of the IMDCT conversion when the maximum data value of the data to be calculated is 2 ¹³ .

FIG. 15 is a graph showing an envelope of the maximum data value at each processing stage of the IMDCT conversion when the maximum data value of the data to be calculated is 2 ¹² .

FIG. 16 is a graph showing an envelope of the maximum data value at each processing stage of IMDCT conversion when the maximum data value of the data to be calculated is 2 ¹¹ .

FIG. 17 is a graph showing an envelope of the maximum data value at each processing stage of the IMDCT conversion when the maximum data value of the data to be calculated is 2 ¹⁰ .

FIG. 18 is a graph showing the envelope of the data maximum value at each processing stage of the IMDCT conversion when the data maximum value of the data to be calculated is 2 ⁹ .

FIG. 19 is an explanatory diagram illustrating scaling of data to be calculated.

[Explanation of symbols]

 1 Bus Line 2 Bus Line 3 Scaling Unit (Scaling Means) 4 Scale Amount Determining Unit 5 Storage Unit (Storage Means) 6 IMDCT Converter (Calculator) 7 QMF (Calculator)

Claims (3)

[Claims] 1. Digitized and standardized first and second digital data are input, and the first and second digital data are calculated and integrated by calculating a data length with a fixed length. In a digital signal processing device provided with an arithmetic unit that outputs third digital data, the first and second digital data are scaled by a predetermined scale amount corresponding to the maximum value of the digital data and the content of the arithmetic operation. A digital signal processing device, characterized in that scaling means is provided for inputting to the arithmetic unit. 2. The digital signal processing apparatus according to claim 1, further comprising a storage unit that stores the scale amount in advance. 3. The scale amount stored in the storage means is set based on the maximum values of the first and second digital data and the maximum value of the third digital data. 2. The digital signal processing device according to 2.