JPH08130478A - Sub-band dividing arithmetic circuit - Google Patents

Abstract

PURPOSE: To accelerate arithmetic processing speed by reducing an arithmetic load by applying the butterfly arithmetic of high-speed Fourier transform (FET) to input signal sub-band dividing processing. CONSTITUTION: Source data x1 ' of an audio signal are inputted to a window arithmetic part 1, window arithmetic is performed based on a specified expression, and an audio signal y1 ' at every time is provided. The signal y1 ' is inputted to a convolusion arithmetic part 2, convolution arithmetic is performed in each cycle 128 based on a specified expression, and a preprocessing arithmetic signal Y1 is provided. The signal Y1 is inputted to a butterfly arithmetic part 3 and inputted to a phase correcting part 4 after the butterfly arithmetic as the basic arithmetic of FFT(fast Fourier transformation) is executed. The correcting part 4 corrects the deviation of a phase by performing rotary arithmetic and outputs sub-band information S1 . In this case, when performing the arithmetic at the arithmetic part 3 and the correcting part 4, the function values of sine and cosine previously stored in sine and cosine function ROM 6 and 7 are respectively used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subband division arithmetic circuit.

[0002]

2. Description of the Related Art In recent years, the development of compression coding techniques for image signals and audio signals has been remarkable. One of the compression coding techniques is subband coding using subband division. This is a method in which an image signal and an audio signal are frequency-analyzed and divided into a plurality of band signals having different frequencies, and the allocation of the number of bits is changed according to the characteristics of the signal for each band signal and the coding is performed. .

As an application example of subband coding of a voice signal, MPEG (Moving Picture Image Coding Experts)
Group) layers I and II have been put to practical use. this is,
By applying the human auditory characteristics calculated from the input speech signal to the subband coding, the original speech signal can be compressed and coded while maintaining its quality.

FIG. 10 shows an example of the configuration of a conventional subband division arithmetic circuit for performing subband division on a digital audio signal. In FIG. 10, the original data X _{i ′} of the audio signal indicates each sample value extracted at each time from the audio signal that is temporally continuous.
For example, if the number of samples to be taken out is 512,
The subscript i'takes a value from 0 to 511.

The original data X _{i ′} is subjected to predetermined preprocessing by the windowing calculation unit 1 and the folding calculation unit 51 before the subband division calculation unit 52 performs the subband division calculation. That is, in the windowing calculation unit 1, a windowing calculation is performed on the original data X _{i ′} based on the following (Equation 1) to obtain the audio signal y _{i ′ at} each time.

[0006]

[Equation 1]

As shown in (Equation 1), the windowing operation is performed by multiplying the input original data X _{i ′} by the window function C _{i ′} . At that time, the window function C _{i For '} , the one stored in advance in the window function ROM 5 is used.

The windowing operation is performed in this way, because the audio signals extracted at each time are not always continuous at the end points of the respective sections, so that the end points of the section are set to a predetermined level. This is to reduce the occurrence of noise in the analysis result by suppressing discontinuity points by making them converge.

Next, the voice signal y _{i ′} for each time obtained as described above is input to the folding calculation unit 51 and subjected to the folding calculation based on the following (Equation 2). In addition, i and k in (Formula 2) are 0 to 6 respectively.
It takes a value of 3, 0 to 7. In this way, by performing the folding calculation for each cycle 64, the preprocessing calculation signal Y _i is obtained.

[0010]

[Equation 2]

The pre-processing operation signal Y _i obtained by the folding operation section 51 is then sub-band division operation section 52.
And is subjected to sub-band division calculation. The subband division calculation unit 52 is specifically configured as shown in FIG. Note that, here, as an example, a configuration in the case of being divided into 32 subbands is shown.

As is apparent from FIG. 11, the sub-band division operation is performed based on the following (formula 3). In addition,
I in (Equation 3) is a parameter in the time axis direction, and takes a value of 0 to 63 as described above. Further, j is a parameter indicating a subband number, and takes a value of 0 to 31.

[0013]

(Equation 3)

As described above, the subband division calculation unit 52 performs the calculation based on (Equation 3) to obtain the subband information S _j divided into 32 frequency bands. The value of cos ((2j + 1) (i-16) π / 64) in
The one stored in advance in the cosine function ROM 53 is used. The value 64 in this equation is M
It is peculiar to the PEG standard, and in other subband coding systems, a peculiar value is used for each.

[0015]

As described above, in the conventional sub-band division arithmetic circuit to which MPEG is applied, for example, the windowing arithmetic unit 1 performs multiplication processing based on (Equation 1) and the folding arithmetic unit 51. The sub-band division processing is performed by performing the addition processing based on (Expression 2) and the multiplication and addition processing based on (Expression 3) by sub-band division calculation unit 52. Table 1 summarizes the number of times these multiplications and additions are performed.

[0016]

[Table 1]

As described above, in the conventional sub-band division arithmetic circuit, many multiplications and additions must be performed. For this reason, there is a problem that the calculation load for performing the sub-band division becomes large. In particular, since the multiplication process has a larger calculation load than the addition process, the large number of times of multiplication is not preferable for the calculation. In addition, as described above, since the number of times multiplications and additions are performed is large, there is a problem in that the processing time increases accordingly.

The present invention has been made to solve such a problem, and an object of the present invention is to reduce the calculation load in the subband division processing.

[0019]

A sub-band division arithmetic circuit of the present invention is a sub-band division arithmetic circuit for frequency-analyzing an input signal to divide it into a plurality of sub-bands having different frequencies. It is characterized in that the butterfly operation of the fast Fourier transform is applied to the band division processing.

Another feature of the present invention is that, in a sub-band division arithmetic circuit for frequency-analyzing an input signal and dividing it into a plurality of sub-bands having different frequencies, the input frequency-analysis source signal is Sub-band information by applying a windowing operation means for performing windowing operation, folding operation means for performing folding operation on the signal output from the windowing operation means, and butterfly operation on the signal output from the folding operation means. To obtain a multi-stage connected butterfly operation means, the phase of the sub-band information output from the butterfly operation means, the phase of the sub-band information obtained when performing a normal frequency analysis without applying the butterfly operation And a phase correction calculation means for making a correction so as to compensate for the deviation.

Another feature of the present invention is that in a sub-band division arithmetic circuit for frequency-analyzing an input signal and dividing it into a plurality of sub-bands having different frequencies,
Windowing calculation means for performing windowing calculation on the input frequency analysis source signal, folding calculation means for performing folding calculation on the signal output from the windowing calculation means, and signal output from the folding calculation means And butterfly calculation means connected in multiple stages to obtain sub-band information by applying butterfly calculation to the sub-band obtained when normal frequency analysis is performed without applying the butterfly calculation. It is characterized in that it includes an offset amount correcting means for correcting an offset amount corresponding to a phase shift of information.

Another feature of the present invention resides in an operation for controlling so as to omit a part of the butterfly operation corresponding to a portion having regularity in the bit-reverse order array of the result obtained after the butterfly operation. A control means is provided.

Another feature of the present invention resides in a determination means for determining whether or not the input voice signal of the frequency analysis source is a signal having only a real part, and the determination means makes the real part in the voice signal. Arithmetic control means for controlling so as to omit the butterfly operation performed based on the imaginary part of the audio signal when it is determined that only the voice signal is included.

Another feature of the present invention is that the designating means designates either the real part or the imaginary part of the subband information obtained after the butterfly operation, and the real part or the imaginary part by the designating means. When any one of the units is designated, an arithmetic control unit for controlling so as to omit the butterfly operation for obtaining the information of the other not designated is further provided.

Another feature of the present invention is that when part of the butterfly operation is omitted, when the regularity of the bit-reverse order array obtained after the butterfly operation deteriorates, all the butterfly operations are executed. It is what

[0026]

Since the present invention comprises the above technical means, it is possible to perform subband division effectively utilizing the similarity between the basic equation of the conventional subband division operation and the basic equation of FFT (Fast Fourier Transform). , The calculation load for sub-band division is smaller than before.

According to another feature of the present invention, since the offset amount correcting means is provided, the phase shift is previously corrected before the butterfly operation is performed, and the butterfly operation is performed on the corrected signal. Therefore, it becomes unnecessary to perform the calculation of the phase correction after the butterfly calculation.

Further, according to another feature of the present invention, since the arithmetic control means is provided, it becomes unnecessary to perform the unnecessary arithmetic operation which is performed when the butterfly arithmetic operation is simply applied. By this, for example, the regularity of the bit-reverse order array is checked, it is determined whether the analysis source signal includes only the real part, or one of the real part or the imaginary part of the subband information obtained as a solution Depending on whether or not is specified, it is possible to omit some of the butterfly operations that correspond to regular parts, omit butterfly operations that are performed based on the imaginary part of the input signal, It is possible to omit the butterfly operation corresponding to the unspecified one of the real part and the imaginary part of the information.

Further, according to another feature of the present invention, all butterflies are executed without omitting the part which deteriorates the regularity of the array in the reverse bit order. Therefore, the regularity is deteriorated and the operation is rather complicated. It is possible to prevent the inconvenience of becoming.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As described in the prior art, in sub-band coding, video and audio signals are frequency analyzed and divided into a plurality of sub-bands having different frequencies, and the characteristics of the band signal for each sub-band. It is a method of encoding by changing the allocation of the number of bits according to the importance.

By the way, there is FFT (Fast Fourier Transform) as one method for analyzing what kind of frequency component is included in a video or audio signal. This FFT is
By repeating a basic calculation called a butterfly calculation, the amount of calculation of DFT (Discrete Fourier Transform) can be reduced.

The sub-band division arithmetic circuit of the present embodiment can reduce the load of the arithmetic operation performed in the sub-band division processing by applying the butterfly operation of the FFT to the sub-band division processing. Is.

That is, the general formula of FFT is represented by the following (Formula 4), and W _i in this (Formula 4) is represented by (Formula 5). As is clear from a comparison between (Equation 4) and (Equation 5) and (Equation 3) described above, the cosine function shown in (Equation 5) is a modification of the cosine function in (Equation 3). You can think of it as having been done. Therefore, in this embodiment, paying attention to this point, the sub-band division can be performed by applying the FFT butterfly operation.

[0034]

[Equation 4]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a functional configuration of a subband division arithmetic circuit according to the first embodiment. It should be noted that the sub-band division arithmetic circuit shown in FIG. 1 is configured by applying a compression encoding technique according to layers I and II of the MPEG audio standard, and the same blocks as the blocks shown in FIG. Is attached.

In FIG. 1, the original data X _{i '} (i' = 0 to 511) of the audio signal taken out at each time is input to the windowing calculation unit 1 and is added to the above-mentioned (Equation 1). Based on the windowing calculation, the audio signal y _{i ′} for each time is obtained. The window function C _{i ′} stored in advance in the window function ROM 5 is used in this windowing operation, as described in the conventional example. By this windowing calculation, the end points of the audio signal of each section taken out at each time are converged to a predetermined level, and the discontinuous points of the audio signal are suppressed.

Next, the voice signal y _{i 'at} each time point obtained by the windowing operation as described above is input to the folding operation unit 2 and subjected to the folding operation based on the following (Equation 6). It Note that i and k in (Equation 6) have values of 0 to 127 and 0 to 3, respectively. Thus, cycle 1
By executing the folding operation for each 28, the preprocessing operation signal Y _i is obtained.

[0038]

(Equation 5)

The pre-processing operation signal Y _i obtained by the folding operation unit 2 is next input to the butterfly operation unit 3 and subjected to the butterfly operation which is the basic operation of FFT. In general, when performing a Fourier transform with a period N, it is necessary to perform (log ₂ N) stages of radix-2 butterfly operation as shown in FIG. That is, when the cycle is 128, it is necessary to perform 7 rounds of butterfly computation, but in the present embodiment, by performing the radix-4 butterfly computation in the second and third stages, as shown in FIG. In addition, a total of 5 stages of butterfly calculations are performed. Therefore, the first shown in FIG.
The butterfly computation unit 31 to the fifth butterfly computation unit 35 perform the computations shown in (Equation 7) to (Equation 11), respectively.

[0040]

(Equation 6)

[0041]

(Equation 7)

[0042]

(Equation 8)

[0043]

[Equation 9]

[0044]

[Equation 10]

Here, the variable names in the polynomial equations (Equation 7) to (Equation 11) will be described. The letter "b" at the beginning of the variable name indicates that the variable is data after the butterfly calculation in each stage. Also, the first subscript indicates whether it is real part data or imaginary part data, and if "R", the real part,
"I" indicates that it is an imaginary part. The second subscript indicates the number of stages of the butterfly operation after the data is calculated, and the numbers 1 to 5 are used. The third subscript indicates the array element number, i = 0
Any number from ~ 127 is used.

As described above, the first butterfly operation units 31-31
(Equation 7) to (Equation 11) by the fifth butterfly operation unit 35.
When the calculation is performed, the data b _R5i and the data b _I5i are obtained as a result. This data b _I5i is shown in FIG.
It corresponds substantially to the subband information S _j obtained by the conventional subband division calculation unit 52 shown in (3), but as shown in (Equation 3) to (Equation 5), i and ( i-16)
There is a phase shift corresponding to. Therefore, the phase shifter 4 corrects the phase shift by performing a rotation calculation as shown in (Equation 12) below.

[0047]

[Equation 11]

When the butterfly computing unit 3 executes the various rotation computations in the equations (7) to (11), the sine-cosine function stored in advance in the first sine-cosine function ROM 6 is used. The function value of is used. Further, when the phase corrector 4 executes the rotation calculation of the above (formula 12), the second sine / cosine function R
A sine / cosine function value stored in advance in the OM 7 is used.

As described above, by applying the FFT and executing the frequency analysis calculation (subband division calculation),
Data b ′ _5i corresponding to the subband information S _j can be obtained. However, since this data _b'5i is given as an array in the reverse order of bits, rearrangement is necessary.
Table 2 shows the rearranged data b ′ _5i and subband information S _j.
Shows the correspondence with.

[0050]

[Table 2]

As described above, in the sub-band division arithmetic circuit according to the first embodiment, the windowing arithmetic unit 1 performs multiplication processing based on (Equation 1), and the folding arithmetic unit 2
Thus, the addition processing based on (Equation 6) is performed. Furthermore, the butterfly computation unit 3 performs multiplication and addition / subtraction processing based on (Equation 7) to (Equation 11), and the phase correction unit 4 (Equation 1
Subband division of the audio signal is performed by performing the multiplication and addition processing based on 2). Table 3 shown below
Is a summary of the number of times these multiplications and additions and subtractions are performed.

[0052]

[Table 3]

As can be seen by comparing Table 3 with Table 1 above, the subband division arithmetic circuit of this embodiment can reduce the number of multiplications as compared with the conventional subband division arithmetic circuit. . Although the number of additions and subtractions has increased compared to the past, the calculation load is considerably larger than the addition and subtraction process, so the total calculation load is reduced compared to the past by reducing the number of multiplications. be able to.

Next, a second embodiment of the present invention will be described. The sub-band division arithmetic circuit according to the second embodiment is
By adopting the configuration as shown in FIG. 4, the calculation for phase correction, which is performed in the first embodiment, can be omitted.

That is, in the above-described first embodiment, the phase shift is corrected after performing the butterfly operation, whereas in the second embodiment, the phase shift is corrected before performing the butterfly operation. Offset amount corresponding to (i-16) in the above (Equation 3) (offset amount corresponding to phase shift)
By making corrections in advance,
It is not necessary to perform the phase correction after the butterfly calculation.

In FIG. 4, the original data X _{i '} (i' = 0 to 511) of the audio signal taken out at each time is subjected to the windowing operation based on (Equation 1) by the windowing operation unit 1. It The audio signal y _{i ′} for each time obtained by this is
It is input to the addition unit 9 in the folding calculation unit 8 to perform a predetermined addition process, and the result is stored in the memory 10.

The addition processing and the storage of the addition result in the memory 10 are controlled by the control unit 11.
That is, the control unit 11 is configured so that the preprocessing operation signal Y _i calculated for i = 0 to 127 by the adding unit 9 is stored in the memory 10 after being shifted by the offset amount corresponding to (i-16). Controlled by.

In this case, the corrected signal Y _i is Y ₀ to Y.
_The first i to fit into the ₁₂₇ sampling intervals
= 0 to 111, the operation shown in (Equation 13-1) is performed, and the signal obtained by this is the preprocessed operation signal Y ₁₆
Stored in the memory 10 as Y ₁₂₇ . Then i = 1
The calculation shown in (Equation 13-2) is performed for 12 to 127, and the signal obtained by this calculation is the preprocessing calculation signal Y _0.
~ Y ₁₅ are stored in the memory 10.

By correcting the offset amount in this way, the phase of the preprocessing operation signal Y _i which is the basis of the frequency analysis by the butterfly operation is shifted in advance on the time axis by an amount corresponding to (i-16). The same effect can be obtained.

[0060]

(Equation 12)

The preprocessing operation signal Y _i thus obtained by the folding operation unit 8 is then input to the butterfly operation unit 3 and the butterfly operation based on the above (Equation 7) to (Equation 11) is performed. By _performing this butterfly operation, the data b _R5i and the data b _I5i are obtained. As described above, in the present embodiment, the offset amount corresponding to the phase shift of (i-16) is corrected in advance. So
The phase of the data b _I5i after the frequency analysis by the butterfly operation has already been corrected. Therefore, the data b _I5i directly corresponds to the subband information S _j .

Therefore, according to the second embodiment, the first
It is possible to omit the 64 times of multiplication processing and the 32 times of addition processing (see Table 3) for phase correction that were performed in this embodiment, and it is possible to further reduce the overall calculation load.

Next, a third embodiment of the present invention will be described. The sub-band division arithmetic circuit according to the third embodiment is
The number of multiplication and addition / subtraction operations can be further reduced by deleting the operation of the portion having regularity from the value given as the bit reverse order after the butterfly operation.

The sub-band division arithmetic circuit of this embodiment is constructed as shown in FIG. That is, in this embodiment,
In addition to the configuration of the sub-band division arithmetic circuit according to the second embodiment described above, the arithmetic controller 12 and the table memory 1 are included.
3 is newly provided. The arithmetic control unit 12 uses the CP
It is configured by a microcomputer system including U, RAM and the like.

As described above, when the FFT is applied and the frequency analysis operation (subband division operation) is executed, the result obtained after this operation is given as an array in the bit reverse order as shown in FIG. As is apparent from FIG. 6, all the least significant bits in the first half of the array in the bit-reverse order are "0", and all the least significant bits in the latter half are "1". That is, FIG.
There is a regularity that the least significant bits of the upper half of the one-dot chain line shown therein are all "0" and all the least significant bits of the lower half are "1".

Further, when the audio signal coding technique by MPEG is applied, the range of j is (2) in (Equation 3).
In j + 1), j = 0 to 31. Therefore, the value required as the calculation result by the FFT is only an odd number from 0 to 63. Therefore, due to the regularity as described above, the calculation for the upper half of the one-dot chain line shown in FIG. 2 can be omitted.

As a method of finding the above-mentioned regularity, there is, for example, the following method. That is, the arithmetic control unit 12 tabulates the array in the bit reverse order in the table memory 13 based on the arithmetic expression for frequency analysis and the range of j. Then, the regularity is found by detecting the part where the bits do not change based on this table information. The operation control unit 12 controls the folding operation unit 8 and the butterfly operation unit 3 so as to omit a part of the operation corresponding to the detected regularity portion.

As a result, the folding calculation unit 8 performs the calculation shown in (Equation 14), and the butterfly calculation unit 3
In the first butterfly operation unit 31 in the above, the operation as shown in (Equation 15) is performed. When performing the operation of the lower half of the one-dot chain line shown in FIG. 2, originally, the first butterfly operation unit 31 originally performs 64 sets of subtraction and rotation operation, but here, the subtraction is performed by the folding operation unit 8. It is done like this. That is, the folding calculation unit 8 also performs the subtraction as shown in (Expression 14), and the first butterfly calculation unit 31 only performs the rotation calculation as shown in (Expression 15).

[0069]

(Equation 13)

The second butterfly operation unit 32 performs the operation of (Equation 8) only for i = 0 to 15, and the third butterfly operation unit 33 performs the operation of (Equation 9).
Calculation of i = 0 to 3, 16 to 19, 32 to 35, 48 to
Only for 51. Further, in the fourth butterfly computing unit 34, the computation of the above (Formula 10) is performed by i = 0 to 63.
Is performed only for multiples of 4, and in the fifth butterfly operation unit 35, the operation of (Equation 11) described above is performed only for even numbers of i = 0 to 63.

Table 4 shown below summarizes the number of times of multiplication and addition / subtraction performed in the subband division arithmetic circuit according to the third embodiment described above. As is clear from Table 4, according to the sub-band division arithmetic circuit of the present embodiment, the number of multiplications and additions / subtractions can be greatly reduced, and the arithmetic load can be further reduced.

[0072]

[Table 4]

Further, as described above, when the sub-band division arithmetic circuit of this embodiment is applied to MPEG, FF
Since the value required as the calculation result by T is only an odd number from 0 to 63, other calculations can be omitted.
That is, in the example shown in FIG. 6, the operation corresponding to the portion of which the value of the most significant bit, that is, the value determined by the operation of the fifth butterfly operation unit 35 is “1” can be omitted. Therefore, since the fifth butterfly operation unit 35 does not need the subtraction and the rotation operation, (Equation 1
Calculation as shown in 6) will be performed.

[0074]

[Equation 14]

As described above, when the sub-band division arithmetic circuit of this embodiment is applied to MPEG, not only the regularity of the least significant bit of the result obtained as an array in reverse bit order after the frequency analysis operation, but also the maximum A part of the calculation can be omitted depending on the regularity of the upper bits. Table 5 shows the total number of calculations in each block in this case.

[0076]

[Table 5]

Incidentally, the correspondence relation between the data b _I5i and the subband information S _j obtained by the above-mentioned calculations being performed by the folding calculator 8 and the butterfly calculator 3 under the control of the calculation controller 12. The table showing
It shows in Table 6.

[0078]

[Table 6]

Next, a fourth embodiment of the present invention will be described. As shown in FIG. 7, in the subband division arithmetic circuit according to the fourth embodiment, a judgment unit 14 for judging whether or not the original data X _{i ′} of the audio signal includes only the real number part.
And a designating unit 15 for designating one of the real number part or the imaginary number part of the subband information obtained by the butterfly operation, which is necessary as a solution.

When the original data X _{i ′} has only a real number part, the first butterfly operation unit 3 of the butterfly operation unit 3
The preprocessing operation signal Y _i input to 1 is also a signal of only the real part. Therefore, in the first butterfly computing unit 31,
Instead of (Expression 15) described above, the calculation shown in (Expression 17) below may be performed.

[0081]

(Equation 15)

Therefore, in the present embodiment, the determination unit 14 shown in FIG. 7 determines whether or not the original data X _{i ′} has only a real number part, and supplies the determination result to the arithmetic control unit 12.
When the determination unit 14 determines that the original data X _{i ′} has only a real number part, the calculation control unit 12 controls the first butterfly calculation unit 31 in the butterfly calculation unit 3 to calculate I am trying to perform such calculations. Table 7 shows a summary of the number of calculations in each block in this case.

[0083]

[Table 7]

Furthermore, when the subband information to be obtained as the final solution requires only one of the real number part and the imaginary number part, the fourth butterfly operation section 34 and the fifth butterfly operation section 35 obtain the required solution. It is sufficient to perform the calculation for

Therefore, for example, when only the solution of the real number part is required, that is, when the real number part is designated by the designation part 15, the calculation control part 12 controls
The fourth butterfly operation unit 34 performs the operation represented by (Equation 18), and the fifth butterfly operation unit 35 performs the operation represented by (Equation 19).

[0086]

[Equation 16]

That is, the calculation related to the imaginary part can be omitted. Table 8 shows a summary of the number of calculations in each block in this case.

[0088]

[Table 8]

As described above, according to the fourth embodiment, when the original data X _{i ′} of the audio signal includes only the real number part, or the data required as the solution has only one of the real number part and the imaginary number part. In some cases, unnecessary operations in each case can also be eliminated. Therefore, the above-mentioned first
˜Compared with the third embodiment, the number of multiplication and addition / subtraction operations can be further reduced.

According to the fourth embodiment, the number of operations that can be reduced based on the regularity of the result obtained after the frequency analysis operation is reduced, but the second butterfly operation unit 32 and the second butterfly operation unit 32 In the 3-butterfly calculation unit 33, when the rotation angle in the rotation calculation in (Equation 8) and (Equation 9) is 0, π / 2, the rotation calculation can be further omitted. The number of calculations in each block in this case is as shown in Table 9.

[0091]

[Table 9]

However, the above-mentioned rotation calculation does not require so many multiplications and additions / subtractions, so even if it is reduced, the effect is not so great. Rather, the regularity as a whole is deteriorated, so it is preferable not to reduce this rotation calculation.

The first to fourth embodiments have been described above, but in order to make it easy to understand the number of multiplications and additions / subtractions in each block in each embodiment, they are summarized in Table 10 below. I will describe it.

[0094]

[Table 10]

In the above description, the case where MPEG is used as the frequency analysis method has been described, but the present invention is not limited to this. For example, the present invention can be applied to the case of performing signal filtering processing.

Generally, when only the signal in a certain frequency band of the input signal is useful, a filtering process is performed to extract only the useful signal. The following filters are used in the filtering process. That is, an LPF (low-pass filter) that extracts only signals in the low-frequency region, an HPF (high-pass filter) that extracts only signals in the high-frequency region, a BPF (band-pass filter) that extracts only signals in the frequency region having a certain characteristic, etc. . In addition, FIR (finite impulse response) is used for digital filtering processing.
e) Filters and IIR (infinite impulse response) filters are widely used, but filtering can also be performed by the method shown in FIG.

In FIG. 8, first, the frequency analyzer 21 frequency-analyzes the input analysis source signal. next,
The gain multiplier 22 multiplies the signal of the analysis result output from the frequency analyzer 21 by a gain peculiar to the filter. Then, the signal combiner 23 combines the signals output from the gain multiplier 22 to perform the filtering process.

For example, in the case of filtering by BPF, it is meaningless to obtain the frequency component in the area where the gain value is small, because the gain multiplier 22 of FIG. 8 multiplies the value by "0". For this reason, when the BPF is used, it is only necessary to obtain the frequency component of the specific area determined by the filter characteristic. So B
By applying the technical means of the present invention to the frequency analyzer 21 to which the PF is applied, it is possible to reduce the operations other than the operation for obtaining the useful frequency component.

For example, the sample length for frequency analysis is N
= 512, and 64 to 1 in the subband after frequency analysis
Consider a case where only signals in the 27 areas are used as useful signals. In this case, 5.5125 KHz if the original signal is sampled at 44.1 KHz.
It suffices to analyze only the signal in the frequency band of 11.025 KHz.

Here, considering the bit-reverse order arrangement of the binary numbers of 64-127, it becomes as shown in FIG. As is apparent from FIG. 9, all the lower 3 bits of the bit-reverse order array are “100”, and there is a regularity that this part does not change. Therefore, by detecting this regularity, it is possible to reduce unnecessary butterfly operations in areas other than the useful frequency domain.

[0101]

As described above, according to the present invention, the butterfly operation of the fast Fourier transform, which requires a relatively small amount of operation, is applied to divide the signal into sub-bands. It is possible to reduce the number of multiplication operations, which has a heavy load, than in the conventional case. Therefore, the calculation load can be reduced, and the calculation processing speed as a whole can be improved.

Further, according to another feature of the present invention, an offset corresponding to the phase shift of the subband information obtained when the normal frequency analysis is performed without applying the butterfly operation before the butterfly operation is performed. Since the amount is corrected, the butterfly calculation can be performed on the signal whose phase shift has been corrected in advance, and the calculation of the phase correction after the butterfly calculation can be omitted. Therefore, it is possible to further reduce the number of calculations for performing sub-band division, reduce the calculation load, and further improve the calculation processing speed.

Further, according to another feature of the present invention, since the arithmetic control means for controlling so as to omit a part of the butterfly operation is provided, the unnecessary operation performed when the butterfly operation is simply applied. Is not performed, and only the butterfly operation for obtaining originally necessary subband information is required to be performed, and the number of operations for multiplication and addition / subtraction can be further reduced to reduce the operation load.

Further, according to another feature of the present invention, since all the butterfly operations are executed for the portion that deteriorates the regularity of the bit-reverse order array, the regularity deteriorates and the operation is rather complicated. Therefore, it is possible to prevent the inconvenience of becoming, and it is possible to reduce the calculation load.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a subband division arithmetic circuit which is a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining processing contents of butterfly calculation.

FIG. 3 is a block diagram showing a configuration of a butterfly computing unit.

FIG. 4 is a block diagram showing a configuration of a subband division arithmetic circuit which is a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a subband division arithmetic circuit which is a third embodiment of the present invention.

FIG. 6 is a diagram showing an example of an array of the results obtained after the butterfly operation in the reverse bit order.

FIG. 7 is a block diagram showing a configuration of a subband division arithmetic circuit which is a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration for performing filtering processing on a subband-divided audio signal.

FIG. 9 is a diagram showing another example of an array in a bit reverse order of a result obtained after the butterfly operation.

FIG. 10 is a block diagram showing a configuration of a conventional subband division arithmetic circuit.

FIG. 11 is a diagram showing a configuration of a subband division calculation unit in a conventional subband division calculation circuit.

[Explanation of symbols]

 1 Windowing Calculation Section 2 Folding Calculation Section 3 Butterfly Calculation Section 4 Phase Correction Section 5 Window Function ROM 6 First Sine / Cosine Function ROM 7 Second Sine / Cosine Function ROM 8 Folding Calculation Section 9 Addition Section 10 Memory 11 Control Part 12 Operation control part 13 Table memory 14 Judgment part 15 Designation part 21 Frequency analyzer 22 Gain multiplier 23 Signal synthesizer 31 First butterfly operation part 32 Second butterfly operation part 33 Third butterfly operation part 34 Fourth butterfly operation part 35 Fifth Butterfly Operation Unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G10L 7/06 H03H 17/02 B 8842-5J H04B 14/04 Z H04N 7/24

Claims (7)

[Claims] 1. A sub-band division arithmetic circuit for frequency-analyzing an input signal and dividing it into a plurality of sub-bands having different frequencies, wherein a fast Fourier transform butterfly operation is applied to the sub-band division processing of the input signal. A sub-band division arithmetic circuit characterized in that 2. A sub-band division arithmetic circuit for frequency-analyzing an input signal and dividing it into a plurality of sub-bands having different frequencies. A folding operation means for performing a folding operation on the signal output from the windowing operation means; and a multi-stage connected butterfly operation means for obtaining subband information by applying a butterfly operation to the signal output from the folding operation means And a phase for correcting the phase of the sub-band information output from the butterfly calculation means so as to compensate for the deviation from the phase of the sub-band information obtained when a normal frequency analysis is performed without applying the butterfly calculation. A sub-band division arithmetic circuit comprising: a correction arithmetic means. 3. A sub-band division arithmetic circuit for frequency-analyzing an input signal and dividing the input signal into a plurality of sub-bands having different frequencies. A folding operation means for performing a folding operation on the signal output from the windowing operation means; and a multi-stage connected butterfly operation means for obtaining subband information by applying a butterfly operation to the signal output from the folding operation means And the folding calculation means includes offset amount correction means for correcting the offset amount corresponding to the phase shift of the subband information obtained when normal frequency analysis is performed without applying the butterfly calculation. Sub-band division arithmetic circuit characterized by. 4. An operation control means is provided for controlling so as to omit a part of the butterfly operation corresponding to a regular portion in the bit-reverse order array of the result obtained after the butterfly operation. The subband division arithmetic circuit according to any one of claims 1 to 3. 5. A judgment means for judging whether or not the input signal of the frequency analysis source is a signal having only a real part, and a judgment means for judging that the input signal contains only a real part. 3. An arithmetic control unit for controlling so as to omit a butterfly operation performed based on the imaginary part of the input signal.
4. The subband division arithmetic circuit according to any one of 4 to 4. 6. A designating means for designating one of a real number part and an imaginary number part of the sub-band information obtained after the butterfly calculation, and one of a real number part and an imaginary number part is designated by the designating part. 6. The operation control means for controlling so as to omit the butterfly operation for obtaining the other information that is not designated when the operation is being performed. 6. Subband division arithmetic circuit. 7. The butterfly operation as set forth in claim 1, wherein when a part of the butterfly operation is omitted, when the regularity of the array in the bit reverse order obtained after the butterfly operation deteriorates, all the butterfly operations are executed. Or a subband division arithmetic circuit according to item 1.