JPH0736490A - Higher harmonic adding circuit - Google Patents

Abstract

PURPOSE:To provide the higher harmonic adding circuit which generates a higher harmonic from a band-limited signal source and adds it, and restores a deleted higher harmonic signal to improve the sound quality of a speech signal. CONSTITUTION:The speech signal 1 is delayed by a delay circuit 3 and applied to an adding circuit 12. An HPF 2 limits the band of the speech signal 1. A zero-cross detecting circuit 4 outputs a pulse train to control an electronic switch 6, and selects memories 8-1, 8-2,... 8-n in order. The frequency of the write clock signal 9 of the memory 8-1 is much higher than the speech signal frequency. The output of the zero-cross detecting circuit 4 is inputted to and delayed by a delay circuit 5 to control the electronic switch on the output side of the memories 80-1, 8-2,... 8-n, which are selected in order. The frequency of a read clock 10 is twice as high as the frequency at the time of storage and the time width of the input signal 1 is compressed to 1/2. The signal which is read out repeatedly twice has its amplitude adjusted by an attenuator 11 to obtain a higher harmonic frequency, which is added by the source signal 1 passed through the delay circuit 3 by an adding circuit 12 to obtain an output 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for an audio signal, and more particularly to a harmonic adding circuit for adding a harmonic component to a band-limited audio signal to restore the audio signal.

[0002]

BACKGROUND ART FIG. 5 is an example a and signal distribution in the distribution diagram of the signal source is 0 to F _m, the bandwidth is limited by the f ₀ by transmission system (i.e., is included in the signal source f ≧ f ₀
Component is not reproduced). The following are examples of specific frequencies in such a case. F ₀ = 9 KHz in medium wave AM (up to about 7 KHz in practice) f ₀ = 15 KHz in FM broadcasting f ₀ = 22 KHz in CD

[0003]

The lack of the f> f ₀ component due to such a limitation causes crispness of reproduced sound and loss of gloss of the sound. Therefore f _0> f> f ₀ / the square circuit is taken out from the received signal a second component scheme for generating the second harmonic wave has been proposed. In this method, the sinusoidal wave cosωt is added to the squaring circuit, and the output is 2cos ² ωt = cos 2ω
From cos2ωt on the right side from t + 1 with a filter,
It is generating harmonics.

[0004] Specifically, f ₀ /. 2 to 6
f ₀ is taken out by a filter and added to the squaring circuit to add f _{0 to} 2f
You can get ₀ . However, the above method has a problem that a sum component (intermodulation component) of two frequencies is easily generated in the case of a composite sound, resulting in a muddy sound of the second harmonic. In this case, the frequency of occurrence of the intermodulation component is reduced by narrowing the band of the band filter of the fundamental wave, but this has a disadvantage that the circuit configuration becomes complicated.

The present invention has been made in view of the above problems and inconveniences, and in order to improve the sound quality of a band-limited voice signal, the harmonic components of a band-limited signal source are extracted to generate a harmonic. It is an object of the present invention to provide a harmonic addition circuit that restores a harmonic signal deleted by band limitation by adding the signal to a band limited signal.

[0006]

In order to achieve the above-mentioned object, the harmonic addition circuit of the first invention comprises an extracting means for extracting a high frequency component of a band-limited audio signal and a zero crossing of the high frequency component. Switch control pulse generation means for generating a switch control pulse based on points, a plurality of storage means for storing the high frequency component at a first clock frequency and extracting at a second clock frequency, and extraction based on the switch control pulse First switching means for sequentially supplying the high frequency components from the means to the plurality of storage means, and second for sequentially supplying the respective high frequency components stored in the respective storage means to the combining means based on the switch control pulse. Switching means of
And a synthesizing means for synthesizing the band-limited audio signal and the high-frequency component supplied via the second switching means.

The harmonic adding circuit of the second invention comprises a first delay means for delaying the band-limited audio signal for a predetermined time, an extracting means for extracting a high frequency component from the band-limited audio signal, a switch control pulse generation means for generating a switch control pulse for each cycle of the zero crossing point of the frequency component, and stores the high-frequency component at a first clock frequency f _k, N times the frequency of the first clock frequency f _k Second
A plurality of storage means for taking out the high frequency components stored at the clock frequency of, and a first switching means for sequentially supplying the high frequency components from the extraction means to the plurality of storage means based on the cycle of the switch control pulse, and a switch. Second delay means for delaying the control pulse by a predetermined time, and second switching means for sequentially supplying the respective high frequency components stored in the respective storage means to the synthesizing means in the stored order based on the delayed switch control pulse. Means and a synthesizing means for synthesizing the band-limited audio signal and the high-frequency component supplied for each N cycles via the second switching means.

[0008]

With the above structure, the harmonic adding circuit of the present invention extracts the high frequency component of the voice signal whose band is limited by the extraction means, and the switch control pulse generation means based on the zero cross point of the high frequency component. To store the high frequency components at the first clock frequency, read the high frequency components at the second clock frequency, and the high frequency components from the extraction means based on the switch control pulse by the first switching means. Sequentially supplying to multiple storage means,
The second switching means sequentially supplies the respective high frequency components stored in the respective storage means to the combining means based on the switch control pulse. Then, the audio signal whose band is limited by the synthesizing unit and the high frequency component supplied through the second switching unit are synthesized.

According to a second aspect of the present invention, the voice signal whose band is limited by the first delay means is delayed for a predetermined time, the high frequency component is extracted from the voice signal whose band is limited by the extracting means, and the high frequency component is raised by the switch control pulse generating means. generates a switch control pulse for each cycle of the zero crossing point of the frequency component, and stores a plurality of storage means of high-frequency components in the first clock frequency f _k, N times the frequency of the first clock frequency f _k The high frequency component is extracted at the second clock frequency, the high frequency component from the extraction means is sequentially supplied to the plurality of storage means based on the cycle of the switch control pulse by the first switching means, and the second delay means switches the switch. The control pulse is delayed for a predetermined time, and each high frequency band stored in each storage means is based on the switch control pulse delayed by the second switching means. The components are sequentially supplied in the order stored in the synthesizing means. Then, the audio signal whose band is limited by the synthesizing means and the high frequency component supplied by N cycles each via the second switching means are synthesized.

[0010]

DETAILED DESCRIPTION FIG. 4 is an explanatory diagram of the basic principle of the harmonics addition circuit of the present invention, FIG. 4 (a) f> f _0/2 of the HPF
The output e _(t ) of the (high-pass filter) is shown in FIG.
Is de / dt> of the zero cross points of FIG.
The time of 0 is indicated by an arrow, and t = t ₁ , t ₂ , t ₃ , ...

In FIG. 4C, the section t ₂ -t ₁ (time width T ₁ ) is compressed to T _1/2 with the waveform of FIG. 4A (solid line portion in FIG. 4C). further repeated time width T _1/2 (broken line part in Figure 3 (c)). Next, section t in FIG.
₃ to compress the same for -t ₂ is repeated as T _2/2. Hereinafter, similarly _{t 4 -t 3, ..., T} 3/2 compresses Similarly for _{t n -t n-1, ...} , repeated as T _n-1/2. FIG. 4 (d) shows the amplitude of FIG.
A desired high frequency signal is added to the signal of (a).

FIG. 1 is a block diagram showing the configuration of an embodiment of a harmonic addition circuit based on the above-mentioned basic principle.
Is a voice signal, 2 is an HPF (high-pass filter) and corresponds to extraction means, 3 and 5 are delay circuits with a delay time of T ₀ , 4 is a zero-cross detection circuit and correspond to switch control means, and 6 is a memory A selection switch (electronic switch) corresponds to the second switching means, and a memory read switch (electronic switch) 7 corresponds to the second switching means, and 8-1, 8-2, ..., 8-n. Is memory, 9
Is a write clock signal (frequency f _k ), 10 is a read clock signal (frequency 2 f _k ), 11 is an attenuator, 12 is an adder circuit, and 13 is an output signal.

In FIG. 1, the audio signal 1 is added to the delay circuit 3 and the HP.
Add to F2. The delay circuit 3 delays the time T ₀ and adds it to the adder circuit 12. The HPF 2 limits the band of the audio signal 1. Note that the cutoff frequency f ₀ /
The change of 2 is as described above.

Zero-cross detection circuit 4 (details will be described later; FIG. 2)
4) outputs the pulse train of t ₁ , t ₂ , t ₃ , ... Of FIG. Then, the electronic switch 6 is controlled by the output pulse of the zero-cross detection circuit 4, and the memories 8-1, 8-2, ...
8-n are sequentially selected.

The frequency of the write clock signal 9 of the memory 8-1 is f _k, which is sufficiently higher than the audio signal frequency f. The memory 8-1 has, for example, T ₁ (t _{1 to} t _{1 in} FIG. 4A).
₂ ) Remember. Similarly, FIG.
(A) T ₂ (t _{2 to} t ₃ ) is stored, ..., Memory 8-n
To store the _{T n-1 (t n-} 1 ~t n) in FIG. 4 (a). The data is stored in the memory 8-1 next to the memory 8-n, but at this time, the previously stored contents of the memory 8-1 have already been read.

Further, the output of the zero-cross detection circuit 4 is input to the delay circuit 5 and delayed by the time T ₀ , and the memories 8-1, 8-
2, ..., 8-n are controlled to sequentially select the memories by controlling the electronic switches 7 (that is, the signal stored in the memory 8-1 is read at time T ₀ ). The frequency 2f _k of the read clock signal 10 and the frequency f _k of 2 when stored
That is, the time width T ₁ of FIG. 4A is compressed to T _1/2 as shown in FIG. 4C. It should be noted that the reading was repeated twice and the T _1/2 of the solid line and the broken line shown in FIG.
Play the length of. The same applies to the memories 8-2, ..., 8-n.

Therefore, the output of the electronic switch 7 is shown in FIG.
The signal has the waveform shown in. The amplitude of this signal is adjusted by the attenuator 11 and the harmonic component is added by the adder circuit 12 (delay circuit 3
And the original signal (delayed by T ₀ ) is added to obtain the output 13.
The reproduction clock of the read clock signal 10 is set to 3
If it is repeated three times as f _k , the additional signal can be the third harmonic.

FIG. 2 is a block diagram showing a detailed configuration example of the zero-crossing detection circuit 4 of FIG. 1, and FIG. 3 is an explanatory diagram of output signals of respective components. In FIG. 2, 14 is a limiter, 15 is a delay circuit having a delay time τ, 16 is a differential amplifier, and 17 is a rectifier circuit. In FIG. 2, FIG. 3 (a)
The limiter 14 outputs the output from the HPF 2 having a waveform as shown in
Then, as shown in FIG. 3B, a square wave showing only the polarity is set. The output of the limiter 14 is the minute delay circuit 1 having the delay time τ.
5 and differential amplifier 16. The output of the delay circuit 15 is added to the differential amplifier 16 and the output of the limiter 14 and the delay circuit 1
When the difference between the outputs of 5 is created, a signal having the waveform shown in FIG. When this difference signal is input to the rectifier circuit 17 and only the positive polarity is taken out, t = t ₁ , t ₂ , as shown in FIG.
A pulse train of t ₃ , ... Is obtained.

[0019]

As described above, according to the harmonic adding circuit of the present invention, the harmonic component lost due to the band limitation in the reproduction system of the band limited audio signal is compared with the harmonic component of the signal within the band limitation. By substituting the wave signal, it is possible to obtain a high-quality reproduced sound with good crispness.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a harmonic addition circuit of the present invention.

FIG. 2 is a block diagram showing a detailed configuration example of the zero-cross detection circuit of FIG.

FIG. 3 is an explanatory diagram of output signals of respective components of the zero-cross detection circuit of FIG.

FIG. 4 is an explanatory diagram of the basic principle of the harmonic addition circuit of the present invention.

FIG. 5 is an example of a distribution diagram of signal sources.

FIG. 6 is an example in which harmonics are added to a band-limited signal.

[Explanation of symbols]

2 high-pass filter (extracting means) 3,5 delay circuit 4 zero-cross detection circuit (switch control pulse generating means) 6 memory selection switch (first switch) 7 memory read switch (second switch) 8-1, 8-2 , 8-n memory (storage means) 12 adder circuit (synthesis means)

Claims (2)

[Claims] 1. An extracting means for extracting a high frequency component of a band-limited audio signal, a switch control pulse generating means for generating a switch control pulse based on a zero cross point of the high frequency component, and the high frequency component. A plurality of storage means for storing at a first clock frequency and extracting at a second clock frequency; and a first storage element for sequentially supplying the high frequency components from the extraction means to the plurality of storage means based on the switch control pulse. Switching means, second switching means for sequentially supplying the respective high frequency components stored in the respective storage means to the synthesizing means based on the switch control pulse, the band-limited audio signal and the second A harmonic addition circuit comprising: a combining unit configured to combine the high frequency components supplied via the switching unit. 2. A first delay means for delaying a band-limited audio signal for a predetermined time, an extracting means for extracting a high-frequency component from the band-limited audio signal, and a zero cross point 1 of the high-frequency component. a switch control pulse generation means for generating a switch control pulse per cycle, and stores the high-frequency component at a first clock frequency f _k, in a second clock frequency of N times the frequency of the first clock frequency f _k A plurality of storage means for extracting the stored high frequency components; a first switching means for sequentially supplying the high frequency components from the extraction means to the plurality of storage means based on a cycle of the switch control pulse; Second delaying the control pulse by the predetermined time
Delaying means, second switching means for sequentially supplying the respective high frequency components stored in the storing means to the combining means in the order stored, based on the delayed switch control pulse, and the band-limited And a synthesizing means for synthesizing the audio signal and the high-frequency component supplied for each N cycles via the second switching means, and a harmonic adding circuit.