JP3308668B2 - Harmonic addition circuit - Google Patents

Abstract

PURPOSE:To provide the higher harmonic adding circuit which generates a higher harmonic from a band-limited signal source and adds it, and restores a deleted higher harmonic signal to improve the sound quality of a speech signal. CONSTITUTION:The speech signal 1 is delayed by a delay circuit 3 and applied to an adding circuit 12. An HPF 2 limits the band of the speech signal 1. A zero-cross detecting circuit 4 outputs a pulse train to control an electronic switch 6, and selects memories 8-1, 8-2,... 8-n in order. The frequency of the write clock signal 9 of the memory 8-1 is much higher than the speech signal frequency. The output of the zero-cross detecting circuit 4 is inputted to and delayed by a delay circuit 5 to control the electronic switch on the output side of the memories 80-1, 8-2,... 8-n, which are selected in order. The frequency of a read clock 10 is twice as high as the frequency at the time of storage and the time width of the input signal 1 is compressed to 1/2. The signal which is read out repeatedly twice has its amplitude adjusted by an attenuator 11 to obtain a higher harmonic frequency, which is added by the source signal 1 passed through the delay circuit 3 by an adding circuit 12 to obtain an output 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for an audio signal, and more particularly to a harmonic addition circuit for restoring an audio signal by adding a harmonic component to a band-limited audio signal.

[0002]

BACKGROUND ART FIG. 5 is an example a and signal distribution in the distribution diagram of the signal source is 0 to F _m, the bandwidth is limited by the f ₀ by transmission system (i.e., is included in the signal source f ≧ f ₀
Are not reproduced). The following are examples of specific frequencies in such a case. F ₀ = 9 KHz for medium wave AM (actually up to about 7 KHz) f ₀ = 15 KHz for FM broadcasting f ₀ = 22 KHz for CD

[0003]

THE INVENTION Problems to be Solved] lack of f> f ₀ component due to such restrictions are the cause of the disappearance of the gloss of crisp good and the sound of the reproduced sound. Therefore f _0> f> f ₀ / the square circuit is taken out from the received signal a second component scheme for generating the second harmonic wave has been proposed. In this method, a sine wave cosωt is added to a squaring circuit, and an output 2cos ² ωt = cos2ω
The filter extracts cos2ωt on the right side from t + 1
Generates harmonics.

[0004] Specifically, f ₀ /. 2 to 6
f ₀ is extracted by a filter and added to a squaring circuit to add f _{0 to} 2f
You can get ₀ . However, the above method has a problem that a sum component (a cross modulation component) of two frequencies is easily generated in the case of a composite sound, and the second harmonic becomes muddy. In this case, the frequency of the intermodulation component is reduced by narrowing the band of the band filter of the fundamental wave. However, such a configuration has a disadvantage that the circuit configuration becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems and disadvantages. In order to improve the sound quality of a band-limited audio signal, a harmonic component of a band-limited signal source is extracted to generate a harmonic. It is another object of the present invention to provide a harmonic addition circuit for adding the signal to the band-limited signal and restoring the harmonic signal deleted by the band limitation.

[0006]

In order to achieve the above object, a harmonic addition circuit according to a first aspect of the present invention comprises extraction means for extracting a high-frequency component of a band-limited audio signal, and zero-crossing of the high-frequency component. Switch control pulse generation means for generating a switch control pulse based on points, a plurality of storage means for storing high-frequency components at a first clock frequency and extracting at a second clock frequency, and extracting based on the switch control pulses First switching means for sequentially supplying high frequency components from the means to the plurality of storage means, and second switching means for sequentially supplying high frequency components stored in each of the storage means to the synthesizing means based on a switch control pulse. Switching means;
A synthesizing unit for synthesizing the band-limited audio signal and the high-frequency component supplied via the second switching unit.

According to a second aspect of the present invention, there is provided a harmonic addition circuit comprising: first delay means for delaying a band-limited audio signal for a predetermined time; extraction means for extracting a high-frequency component from the band-limited audio signal; A switch control pulse generating means for generating a switch control pulse for each cycle of a zero cross point of a frequency component, storing a high frequency component at a first clock frequency f _k , and a frequency N times higher than the first clock frequency f _k Second
A plurality of storage means for retrieving high-frequency components stored at a clock frequency of: a first switching means for sequentially supplying high-frequency components from the extraction means to the plurality of storage means based on a cycle of a switch control pulse; Second delay means for delaying the control pulse for a predetermined time, and second switching for sequentially supplying the respective high-frequency components stored in each storage means to the synthesizing means in the order of storage based on the delayed switch control pulse. Means, and a synthesizing means for synthesizing the band-limited audio signal and the high-frequency component supplied every N cycles via the second switching means.

[0008]

With the above arrangement, the harmonic addition circuit of the present invention extracts the high frequency component of the audio signal whose band has been limited by the extraction means, and the switch control pulse generation means based on the zero cross point of the high frequency component by the switch control pulse generation means. And a plurality of storage means store the high-frequency component at the first clock frequency, read out at the second clock frequency, and extract the high-frequency component from the extraction means based on the switch control pulse by the first switching means. Sequentially supplied to a plurality of storage means,
The second switching means sequentially supplies the respective high-frequency components stored in the storage means to the synthesizing means based on the switch control pulse. Then, the audio signal whose band has been limited by the synthesizing unit and the high-frequency component supplied via the second switching unit are synthesized.

According to a second aspect of the invention, the audio signal band-limited by the first delay means is delayed for a predetermined time, a high-frequency component is extracted from the audio signal band-limited by the extraction means, and the high-frequency component is extracted by the switch control pulse generation means. A switch control pulse is generated for each cycle of the zero cross point of the frequency component, and the plurality of storage means store the high frequency component at the first clock frequency f _k , and store the high frequency component at N times the frequency of the first clock frequency f _k . The high-frequency component is extracted at the second clock frequency, the high-frequency component from the extracting means is sequentially supplied to the plurality of storage means based on the cycle of the switch control pulse by the first switching means, and the high-frequency component is switched by the second delay means. The control pulse is delayed by a predetermined time, and the high-frequency signal stored in each storage means is stored based on the switch control pulse delayed by the second switching means. The components are sequentially supplied in the order stored in the synthesizing means. Then, the audio signal whose band has been limited by the synthesizing unit and the high-frequency component supplied through the second switching unit every N cycles are synthesized.

[0010]

DETAILED DESCRIPTION FIG. 4 is an explanatory diagram of the basic principle of the harmonics addition circuit of the present invention, FIG. 4 (a) f> f _0/2 of the HPF
FIG. 4B shows the output e _(t ) of the (high-pass filter).
Is de / dt> of the zero cross points in FIG.
The time of 0 is indicated by an arrow, and t = t ₁ , t ₂ , t ₃ ,...

In FIG. 4C, the section t ₂ -t ₁ (time width T ₁ ) is compressed to T _1/2 by the waveform of FIG. 4A (the solid line in FIG. 4C). further repeated time width T _1/2 (broken line part in Figure 3 (c)). Next, the section t in FIG.
₃ to compress the same for -t ₂ is repeated as T _2/2. Hereinafter, similarly _{t 4 -t 3, ..., T} 3/2 compresses Similarly for _{t n -t n-1, ...} , repeated as T _n-1/2. FIG. 4D shows an attenuation of the amplitude of FIG.
A desired high-frequency signal is added to the signal of (a).

FIG. 1 is a block diagram showing the configuration of an embodiment of a harmonic addition circuit based on the above-described basic principle.
Is an audio signal, 2 is an HPF (high-pass filter) and corresponds to extraction means, 3 and 5 are delay circuits having a delay time T ₀ , 4 is a zero-cross detection circuit and corresponds to switch control means, and 6 is a memory. A selection switch (electronic switch) corresponds to the second switching means, and 7 is a memory readout switch (electronic switch) and corresponds to the second switching means, 8-1, 8-2, ..., 8-n. Is memory, 9
Is a write clock signal (frequency f _k ), 10 is a read clock signal (frequency 2f _k ), 11 is an attenuator, 12 is an addition circuit, and 13 is an output signal.

In FIG. 1, an audio signal 1 is supplied to a delay circuit 3 and an HP
Add to F2. The delay circuit 3 delays the time T ₀ and adds it to the addition circuit 12. The HPF 2 limits the band of the audio signal 1. Note that the cutoff frequency f ₀ /
2 is as described above.

A zero-cross detection circuit 4 (details will be described later; FIG. 2)
4) outputs a pulse train of t ₁ , t ₂ , t ₃ ,... In FIG. Then, the electronic switch 6 is controlled by the output pulse of the zero-cross detection circuit 4, and the memories 8-1, 8-2,.
8-n are sequentially selected.

The frequency of the write clock signal 9 for the memory 8-1 is _fk, which is sufficiently higher than the audio signal frequency f. The memory 8-1 for example FIG. 4 T ₁ of (a) (t ₁ ~t
₂ ) Remember. Similarly, FIG.
Stores T ₂ (t ₂ ~t ₃₎ of (a), ..., the memory 8-n
Stores T _n-1 (t _{n-1 to} t _n ) in FIG. After the memory 8-n, the data is stored in the memory 8-1. At this time, the contents of the memory 8-1 stored earlier have already been read.

Further, the output of the zero-cross detection circuit 4 is input to the delay circuit 5 and is delayed by the time T ₀ to store the data in the memories 8-1 and 8-.
2, ..., 8-n to control the electronic switch 7 on the output side of sequentially selecting memory (i.e., the signal stored in the memory 8-1 are read out to the time T _0). Second frequency f _k during storage is a frequency 2f _k of the clock signal 10 read
The time width T ₁ in FIG. 4A is compressed to T _1/2 as shown in FIG. 4C. The reading is repeated twice, and each of the solid line and the broken line T _1/2 shown in FIG.
Play length. The same applies to the memories 8-2,..., 8-n.

Accordingly, the output of the electronic switch 7 is shown in FIG.
The signal has the waveform shown in FIG. The amplitude of this signal is adjusted by the attenuator 11 and converted into a harmonic component by the addition circuit 12 (delay circuit 3).
The output 13 is obtained by adding the original signal (delayed by T ₀ in the above) to the original signal.
Also, the reproduction clock of the read clock signal 10 is set to 3
By repeating three times as f _k , the additional signal can be made the third harmonic.

FIG. 2 is a block diagram showing a detailed configuration example of the zero-crossing detection circuit 4 of FIG. 1, and FIG. 3 is an explanatory diagram of output signals of respective components. In FIG. 2, reference numeral 14 denotes a limiter, 15 denotes a delay circuit having a delay time τ, 16 denotes a differential amplifier, and 17 denotes a rectifier circuit. In FIG. 2, FIG.
The output from the HPF 2 having the waveform shown in FIG.
Thus, as shown in FIG. 3B, a square wave indicating only the polarity is obtained. The output of the limiter 14 is converted to a minute delay circuit 1 having a delay time τ.
5 and the differential amplifier 16. The output of the delay circuit 15 is added to the differential amplifier 16 and the output of the limiter 14 and the delay circuit 1
5 produces a signal having the waveform shown in FIG. When this difference signal is input to the rectifier circuit 17 and only the positive polarity is taken out, t = t ₁ , t ₂ ,
The pulse train of t ₃ ,... is obtained.

[0019]

As described above, according to the harmonic adding circuit of the present invention, the harmonic component lost due to the band limitation in the reproduction system of the band-limited audio signal is replaced by the harmonic component of the signal within the band limitation. By replacing the wave signal, a crisp high-quality sound reproduction can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a harmonic addition circuit according to the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration example of a zero-cross detection circuit in FIG. 1;

FIG. 3 is an explanatory diagram of output signals of respective components of the zero-cross detection circuit of FIG. 2;

FIG. 4 is an explanatory diagram of the basic principle of the harmonic addition circuit of the present invention.

FIG. 5 is an example of a distribution diagram of a signal source.

FIG. 6 is an example of adding a harmonic to a band-limited signal.

[Explanation of symbols]

2 High-pass filter (extraction means) 3, 5 Delay circuit 4 Zero-cross detection circuit (switch control pulse generation means) 6 Memory selection switch (first switch) 7 Memory read switch (second switch) 8-1, 8-2 , ..., 8-n memory (storage means) 12 adder circuit (synthesis means)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G10L 13/00

Claims (2)

(57) [Claims] An extraction unit configured to extract a high-frequency component of a band-limited audio signal; a switch control pulse generation unit configured to generate a switch control pulse based on a zero cross point of the high-frequency component; A plurality of storage means for storing at a first clock frequency and retrieving at a second clock frequency; and a first supply means for sequentially supplying a high-frequency component from the extraction means to the plurality of storage means based on the switch control pulse. Switching means; second switching means for sequentially supplying high-frequency components stored in each of the storage means to the synthesizing means based on the switch control pulse; and the band-limited audio signal and the second A combining means for combining high-frequency components supplied via the switching means, and a harmonic adding circuit. 2. A first delay unit for delaying a band-limited audio signal for a predetermined time; an extraction unit for extracting a high-frequency component from the band-limited audio signal; and one of zero cross points of the high-frequency component. A switch control pulse generating means for generating a switch control pulse for each cycle; storing a high frequency component at a first clock frequency f _k; and using a second clock frequency of N times the first clock frequency f _k. A plurality of storage means for extracting the stored high-frequency component; a first switching means for sequentially supplying the high-frequency component from the extraction means to the plurality of storage means based on a cycle of the switch control pulse; A second delaying the control pulse for the predetermined time;
Delay means, and second switching means for sequentially supplying the respective high-frequency components stored in each of the storage means to the synthesizing means in the order in which they are stored based on the delayed switch control pulse; and Synthesizing means for synthesizing the audio signal and the high frequency component supplied by N cycles via the second switching means.