JPH0736201U - Output instruction double use check device - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the time to check the double use of output instructions among program instructions. [Structure] Program memory 2 storing program instructions
Output instructions read from the output instruction selection circuit 4 according to the selection conditions of the output instruction set in the selection condition table 5 (for example, the lowest address of the output instruction), and the selected output instructions are stored in the stack storage circuit. 7, the stack search circuit 6 executes a check for double use for a group of output instructions stored in the stack storage circuit 7, and when there is double use, a warning circuit 20 warns.
When there is no double use, the selection condition is sequentially changed and the double use is checked for all output instructions. By setting the selection condition and selecting the output instruction, the number of times the output instruction is read is reduced and the check time is shortened.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a program instruction check device for a sequence controller, and more particularly to a dual use check device for output instructions in a program.

[0002]

[Prior art]

 Generally, if there are two or more output instructions with the same output address in the program executed by the programmable controller, it causes the malfunction of the programmable controller.Therefore, the output instruction in the program is executed before the programmable controller operates. It is known to check for double usage. Various conventional output instruction double use checking devices of this type are known.

An example of the processing procedure of this type of conventional output instruction double check device will be described. FIG. 2 shows a sequence program in which the sequence circuit is illustrated. FIG. 3 shows a list representation of the sequence program of FIG. In such a program, in order to check the double use of output instructions, the first step is to extract the output instruction at the front of the program. In the program example of FIG. 3, when the output instruction 1 is extracted, the double check device stores this output instruction "OUT 0000" in the internal memory. Next, using this output instruction as a base point, the program instruction after the base point is compared with the output instruction of the base point, and the double check device detects whether there is the same instruction as the output instruction of the base point. If the same instruction as the base output instruction is not in the program, the double-use checking device moves the base point to the next output instruction. In the example shown in Fig. 3, "OUT 0001" of output instruction 2 is the base point. In this way, the base points of the output instructions are sequentially moved, and the double check device repeatedly checks the double use of the output instructions until the base point reaches the end of the program.

[0004]

[Problems to be solved by the device]

However, for example, when checking the double use of 4096 output instructions in a sequence program with 8192 steps, the average number of read program instructions from the program is the number of read = 8192 + 4096 × 4096 ≈ 8192 + 16.8 There was a problem that it became very large as × 10 ⁶ ≈ 16.8 × 10 ⁶ (times), and it took time to check the double use of output instructions.

Therefore, an object of the present invention is to solve the above problems and to provide an output instruction double use check device capable of shortening the check time for double use of output instructions. .

[0006]

[Means for Solving the Problems]

 In order to achieve the above-mentioned object, the present invention provides a program memory for storing a sequence program, an output instruction detecting means for detecting an output instruction from the instructions read from the program memory, and a group of output instructions. The condition setting means for sequentially setting the selection conditions for selecting the output command in a predetermined fixed order, and the output updated every time the selection conditions by the condition setting means are switched, and the output selected by the selection conditions A stacking means for storing a usage state of the instruction; and a detecting means for detecting the double use of the output instruction by comparing the output instruction selected by the selection condition with the output instruction stored in the stacking means. It is characterized by that.

[0007]

[Action]

 In the present invention, the output instruction is selected from the program instructions according to the selection condition, and the detection means checks the use of the selected group of output instructions for double use. When there are no output instructions that are heavily used, the selection conditions are changed sequentially and a double usage check is performed for all output instructions, so the number of times the output instructions are read from the memory is reduced, thus reducing the check time. It can be shortened.

[0008]

【Example】

 An embodiment of the present invention will be described below in detail and specifically with reference to the drawings. In this embodiment, the area of addresses "0000" to "7777" (octal number) designated by the output instruction is allocated. In this embodiment, the number of read times of the program instruction can be determined by checking the output instruction having the predetermined lowest address number by paying attention to the lowest address of the assigned address. To reduce.

FIG. 1 shows an example of the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 2 is a program memory for storing a sequence program. A program counter 1 sets a read address of the program memory 2. The count value of the program counter 1 is sent to the program memory 2 by meeting the address bus a. The program memory 2 outputs the addressed program command to the data bus b. Reference numeral 3 is an output instruction detection circuit for detecting whether or not the program instruction is an output instruction. When the output command detection circuit 3 detects that the program command is an output command, it outputs a signal of level "H" indicating that there is an output command to the signal line c. An output instruction selection circuit 4 receives an output instruction signal through the signal line c and determines whether the output instruction at this time matches the selection condition indicated by the selection condition table 5. , Outputs an output command matching the selection condition to the bus g. Further, when the output instruction does not meet the selection condition, the output instruction selection circuit 4 outputs a signal of level "H", which means that there is no selection target, to the signal line f. When the output command matches the selection condition, a signal of level "H" indicating that there is a selection target is output to the signal line e 1.

Reference numeral 5 is a selection condition table, which outputs the number designated by the table pointer as a selection condition to the output instruction selection circuit. The output instruction selection circuit 4 selects an output instruction in which the number designated by the table pointer matches the lowest number of the instruction address of the output instruction. However, the output instruction selection circuit 4 outputs only the address number of the selected output instruction. Therefore, the memory capacity of the stack storage circuit 7 described later can be reduced. A stack storage circuit 7 stores the address portion in the output instruction selected by the output instruction selection circuit 4. A stack search circuit 6 searches the address portion stored in the stack storage circuit 7 using the stack area 8 (stack means), and is currently sent from the output instruction selection circuit 7. Then, it is checked whether or not the same address part exists in the stack area 8. Here, when there is the same address portion, it is assumed that the output instruction is used twice, and the signal of level "H" is output to the signal line i. Based on this signal, the warning circuit 20 gives a warning by sounding a warning sound or displaying a message. An address upper limit check unit 9 sends a program reset signal via the signal line q to reset the program counter 1 when the value of the program counter 1 reaches the final address of the program. When the program counter 1 has not reached the final address, the address upper limit check unit 9 outputs a signal of level "H" for incrementing the program counter 1 to the signal line p. Reference numeral 10 is a table pointer upper limit check unit, which detects whether or not the table pointer 5'has reached a predetermined upper limit, and when the table pointer 5'has reached the upper limit, a signal of level "H" is output to the signal line r. Output a signal. When the table pointer 5'has not reached the upper limit, a signal of level "H" is output to the signal line s. Reference numeral 11 is an address read conversion circuit, which is a circuit for converting a program address into a corresponding display pattern. A display unit 12 displays the program address converted into a display pattern.

Next, a check operation for double use of output instructions in such a configuration will be described. In FIG. 1, the sequence program instruction corresponding to the address set by the program counter 1 is output to the data bus b. The output command detection circuit 3 takes out the command code portion b'from the data bus b, judges whether it is an output command, and outputs a signal of level "H" to the signal line c when it is an output command, Sometimes, a signal of level "H" is output to the signal line d. When the output instruction selection circuit 4 receives the signal of c, it takes out the i / o address part (address number) b "from the data bus b. Furthermore, the selection condition table 5 outputs the table via the data bus h. The selection condition (the lowest address number) indicated by the pointer 5'is fetched, and it is determined whether or not the i / o address part b "of the output instruction is the selection target. When the i / o address part b "of the output command is to be selected, a signal of level" H "is output to the signal line e, and the selection condition part h is excluded from the i / address part b" on the data bus g. Output If the result is no, a signal of level "H" is output to the signal line f.

The stack search circuit 6, when receiving the signal e of the selection target ant, sequentially fetches the data of the data bus g and the data from the top of the stack area 8 to the stack pointer 8 ′ via the data bus k, The data on the data bus is compared with the data stored in the stack area 8 ', and if there is matching data, a signal indicating the double use is output to the signal line i. If not, to the signal line j. Output the signal without double use. The stack memory circuit 7 outputs the data of the data bus g to the data bus 1 and the transmission signal to the signal line m when receiving the signal j indicating that the double use is not used. After that, the transmission signal is further output to the signal line n 1. In the stack area 8, when the send signal m is received, the data of the data bus 1 is stored in the storage area indicated by the stack pointer 8'and the stack pointer 8'is incremented. Further, the stack pointer 8'is cleared to zero by the signal q from the address upper limit check 9. The OR circuit G1 outputs the signal "H" to the signal line o when it receives the signal "H" on any of the signal lines d, f, n. The address upper limit check unit 9 judges whether the address of the address bus a has reached the end of the sequence program in the program memory 2 when receiving the signal o, and when it has reached the end, it outputs a "H" signal to the signal line q. When it is not output, when it is not output, the "H" signal is output to the signal line p.

The selection condition table pointer upper limit check unit 10 determines whether the table pointer 5 ′ has reached the upper limit of the selection condition table 5 when receiving the signal q, and when it has reached the signal line r. The signal of level "H" is output to, and when not, the signal of level "H" is output to the signal line s. When the selection condition table 5 receives the signal s, the table pointer 5'is incremented. When receiving the signal p, the program counter 1 increments the address of the address bus a. When the program counter 1 receives the signal q, it outputs the head address of the program memory 2 to the address bus a. Since the display unit 12 always takes in the address of the address bus a via the address conversion circuit 11 and displays the program address on the display unit 12, the check status of the output instruction can be grasped.

Next, how the double check is performed for the program example of FIGS. 3 and 3 will be briefly described. Here, it is assumed that the selection condition table 5 stores the selection conditions of "0" to "7". When the program counter 1 counts "0", the program instruction "STR 0000" (see FIG. 3) is output from the program memory 2 to the data bus b. It is confirmed by the output command detection circuit 3 that this program command is not an output command, and a signal of level "H" is sent to the program counter 1 via the signal line d, the OR circuit G1, the address upper limit check unit 9 and the signal line p. Sent to. Then, the count value of the program counter 1 becomes "1", and the output instruction "OUT 0 000" (see FIG. 3) is output from the program memory 2 to the data bus b. When the output instruction detection circuit 3 confirms that this program instruction is an output instruction, the output instruction selection circuit 4 determines the lowest address "0" of this output instruction and the selection condition designated by the table pointer 5 '. The address portion "000" of this output instruction is compared and stored in the stack storage circuit 7. The stack search circuit 6 refers to the contents stored in the stack area 8 (nothing is stored at this time) and searches for the same address number as the address portion "000". As a result of this search, it is found that the same address number as that of the address portion "000" is not stored in the stack area 8. Therefore, a no signal is output to the signal line j and the stack storage circuit 7 is temporarily stopped. The stored address portion “000” is stored in the stack area 8. In the same procedure, the output instruction "OUT 0001" at the address 3 in FIG. 3 is detected by the output instruction detection circuit 3, but the current selection condition is that the lowest address number is "0". This output command "OUT 0001" is not sorted and is not stored in the stack area 8. In this way, only the output instruction having the lowest address number "0" is selected and compared with the output number stored in the stack area 8 to check the double use. Next, when the program counter 1 counts the final address of the program memory 2, the address upper limit check unit 9 resets the program counter 1, the table pointer 5'is incremented, and the selection condition is set to "1". Furthermore, the contents of the stack area 8 are cleared. In this way, the double use of the output instruction with the lowest address "1" is checked next. Similarly, when the check for double use of the output instructions up to the lowest address "7" is completed, the table pointer upper limit check unit 10 confirms the end of the check.

In this way, the double use check of the output instruction is performed. If the same output instruction is double used, the stack search circuit 6 detects the double use, and the warning circuit. 20 issues a warning. At this time, since the program address of the corresponding output command is displayed on the display unit 12, the operator can know the output command that is being used twice. Furthermore, since the contents of the stack area 8 are updated every time the selection conditions of this embodiment are switched, the memory capacity of the stack area 8 can also be saved.

In the present embodiment, when the numbers of program instructions and output instructions are made to correspond to those of the conventional example, the average number of read times of program instructions is read number = S (8192 + M × M / 2). S = number of sorts, for example, if output n = 1 instruction i / o address is 0000 (8) to 7777 (8) in octal notation, the number of sorts is When eight kinds of 0 to 7 are set, S = 8. M = size of the stack area 8 and the maximum number of output instructions for one sort type. As a result, M = the maximum number of all output instructions / S = 4096/8 = 512. Therefore, the average number of times of reading in this embodiment is 8 × (8192 + 512 × 512/2) ≈1.1 × 10 ⁶ times. Since the output instruction read count in the conventional example was 16.8 × 10 ^{6, the} output instruction read count in this example is 1.1 × 10 ⁶ / 16.8 × 10 ⁶ ≈ 1/15 in the conventional example. Clearly, the time required to check for double use of output instructions is significantly reduced.

[0017]

[Effect of device]

 As described above, according to the present invention, a program memory for storing a sequence program, an output instruction detecting means for detecting an output instruction from the instructions read from the program memory, and a group of output instructions. The condition setting means for sequentially setting the selection conditions for selecting the output command in a predetermined fixed order, and the output that is updated each time the selection conditions by the condition setting means are switched and is selected by the selection conditions. A stacking means for storing a usage state of the instruction; and a detecting means for detecting the double use of the output instruction by comparing the output instruction selected by the selection condition with the output instruction stored in the stacking means. , The output instruction with the lowest number in common is selected from the program instructions as the selection condition, and the double use check is performed for the selected output instruction. Since the number of times the output instructions are read is reduced, the double-use check time for output instructions can be significantly shortened, and the usage status of the output instructions selected by the selection conditions can be reduced. Since the stack means to be stored is updated every time the selection condition by the condition setting means is switched, there is an effect that the memory capacity can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of the configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a program ladder diagram of a conventional example.

FIG. 3 is an explanatory diagram showing a program of a conventional example.

[Explanation of symbols]

 1 Program counter 2 Program memory 3 Output instruction detection circuit 4 Output instruction selection circuit 5 Selection condition table 5'Table pointer 6 Stack search circuit 7 Stack storage circuit 8 Stack area 8'Stack pointer 9 Address upper limit check unit 10 Table pointer upper limit check unit 11 Address read / display conversion circuit 12 Display unit

Claims (2)

[Scope of utility model registration request] 1. A program memory for storing a sequence program, an output command detecting means for detecting an output command from the commands read from the program memory, and a group of output commands from the output commands. Condition setting means for sequentially setting the sorting conditions in a predetermined fixed order, and is updated each time the sorting conditions by the condition setting means are switched, and the use state of the output command sorted by the sorting conditions is stored. An output instruction comprising stack means and detection means for detecting double use of the output instruction by comparing the output instruction selected by the selection condition with the output instruction stored in the stack means. Double-use check device. 2. The apparatus according to claim 1, wherein the selection condition is that the lowest output number of the output command matches the number set by the condition setting means. Usage check device.