JPH0734589B2 - Video playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video disc player for reproducing a video signal from a signal recording medium such as an optical disc, and more particularly to a still disc,
The present invention relates to control of writing and reading of a memory circuit equipped to perform special reproduction such as double speed reproduction.

(Prior Art) Generally, there are two types of video disc players, a VHD system and an LV system. In a LV system video disc player, a laser beam directs a disc signal surface from an inner peripheral portion to an outer peripheral portion. The recorded signal is reproduced by tracing in a spiral shape by means of. Further, the LV type optical disc includes a CAV disc in which a video signal is recorded at a constant angular velocity every two fields per track and a CLV disc in which a linear velocity is constant.

In CLV discs, the sync signals recorded at equal intervals on spiral tracks are not aligned in a row in the disc radial direction, so during special playback, playback synchronization is performed before and after jumping tracks in the disc radial direction. The signals become discontinuous, causing color fading on the playback screen, disturbance of vertical synchronization, horizontal skew, and the like.

Therefore, there has been proposed a video disc player capable of reproducing a normal image by writing a video signal for one field into a video memory at the time of special reproduction of a CLV disc and then reading the signal from the memory at an appropriate timing. (JP-A-58-139577 (HO4N5 / 93)).

Generally, a video signal processing circuit having a video memory, for example, a time base collector for correcting a time base error of a VTR, or a frame for converting a sync signal of another station into a sync signal of its own in a TV broadcasting system. The synchronizer is equipped with a write address counter and a read address counter that are connected to separate oscillators to write and read signals to and from the video memory, and write address signals output from both counters. By supplying the read address signal and the read address signal to the address input terminal of the memory circuit, writing and reading are performed in separate cycles.

FIGS. 3 (a), (b) and (c) show the write and read operations. The write address counter displaces the write address W at a predetermined write cycle T ₁ as shown in FIG. 3 (a) and stores a series of video signals A, B, C ... Shown in FIG. 3 (b). Write to. Further, the read address counter displaces the read address R at a predetermined read cycle T ₂ as shown in FIG. 3 (a) and reads the video signal from the memory as shown in FIG. 3 (c). is there.

(Problems to be solved) However, in the conventional video disc player,
Like the time base collector or the frame synchronizer, since the write address counter and the read address counter that operate by separate clocks were equipped, the write cycle T ₁ and the read cycle T ₂ for the memory did not exactly match, For example, when the read cycle T ₂ is shorter than the write cycle T ₁ as shown in FIG. 3 (a), the write address W and the read address R intersect at the time indicated by X in the figure, and thereafter the memory address is changed to the memory. Writing cannot precede reading.

In the illustrated example, the writing of the video signal A in the 1-field period shown in FIG. 3B precedes the reading, but the video signal B is not read in the latter half of the time point X. Video signal A, which precedes writing and is one field before
Will be read.

Therefore, when the video signal B of FIG. 3 (b) is written in the memory as a still image signal when shifting from the normal reproduction mode to the still image mode, the screen is temporarily displayed when the video signal is read from the memory. There was a disorder. In particular, the problem is large when the video signal is violent and the video signal A and the video signal B shown in FIG. 3B are significantly different.

(Means for Solving the Problems) The present invention solves the above problems by performing signal writing and reading by the memory circuit (4) at the same cycle T ₀ .

In the video disc player according to the present invention, a circuit (12) for controlling writing / reading of the memory circuit (4).
In addition, a write address counter (7) and a read address counter (8) to which clock signals from the same supply source were connected were equipped.

(Operation) The write address counter (7) and the read address counter (8) receive the clock signal Q sent from the same supply source and generate the write address signal W and the read address signal R. Memory circuit (4)
Performs signal writing and reading at the same cycle T ₀ based on the address signal.

(Effects of the Invention) According to the video disc player of the present invention, the write address signal W and the read address signal R do not cross each other, and therefore, for example, when the normal reproduction mode is changed to the special reproduction mode such as still mode. , You can get a consistent screen.

(Embodiment) FIG. 1 shows a circuit configuration of a CLV type video disc player embodying the present invention.

A pickup device (2) for reproducing a video signal from an optical disc (1) is a well-known pickup having an optical system connected to a pickup conveying means (not shown),
It conveys in the disk radial direction and traces the signal surface.

In addition, the pickup device (2) is an electromagnetic drive device having a tracking coil for driving the magnet in the tracking direction, as well known, by providing a magnet in a movable part of the pickup or the like in order to make the pickup jump operation during special reproduction. (Not shown). As shown in FIG. 1, a jump control circuit (9) is connected to the driving device, and a jump pulse having a predetermined pulse width and a predetermined period is supplied during special reproduction.

The reproduction signal from the pickup device (2) is demodulated by the demodulation circuit (3) and then the video signal V _{1 for} one field is generated.
Are supplied to the memory circuit (4) whose write / read operation is controlled by the control circuit (12).

The output signal V ₂ of the output signal V ₁ and the memory circuit of the demodulation circuit (3) (4) is respectively connected to both inputs of the controlled changeover switch (10) by a switching control circuit (11).

The selector switch (10) is switched when the phases of the output signals V ₁ and V ₂ coincide with each other during special reproduction, and selects the output signal V ₂ of the memory circuit (4) during the jump operation,
After the jump is completed, the output signal V ₁ of the demodulation circuit (3) is selected at a proper time and supplied to the monitor device.

As is well known, the memory circuit (4) is configured by disposing an A / D converter and a D / A converter before and after the field memory.

The write / read control circuit (12) includes a write address counter (7) and a read address counter (8) to which a clock signal Q (for example, a frequency of about 10.74 MHz) is supplied from the same oscillator, and both counters (5). A selector (5) for time-division multiplexing both output terminals of (6) or selectively connecting one of the output terminals to the address input terminal of the memory circuit (4) and the selector (5). It comprises a timing control circuit (6) for switching control.

The write address counter (7) counts the clock signal Q while being reset by the reset signal P, and has a predetermined period T ₀ (for example, 262.5H or 262 which is one vertical synchronization period).
H) write address signal W is generated. The read address counter (8) counts the clock signal Q while self-resetting due to overflow, and generates the read address signal R having a predetermined cycle T ₀ .

Therefore, even when writing and reading are simultaneously performed on the memory circuit (4), the write address signal W and the read address signal R do not cross each other.

FIG. 2 shows the operation when slow playback is performed by the video disc player shown in FIG.

At the time of signal writing, the write command signal (reset signal P to the write address counter) shown in FIG. 2 (d) is input to the memory circuit (4), and at the same time, FIG. 2 (a).
The write address signal W having the cycle T ₀ shown in FIG. 2 is supplied, and the video signal (V ₁ , V ₁ ′ ...) In one field period shown in FIG. 2B is supplied to the field memory at the cycle S (S = 3T _0). ).

Further, the read address signal R of the period T _0, reading from the field memory, as shown in FIG. 2 (c) are repeated in cycles T _0, read image signal (V _2, V _2,
The slow playback screen is generated by V ₂ , V ₂ ′, V ₂ ′, ...).

In this case, since the write address W and the read address R do not intersect as shown in FIG. 2 (a), the reproduced screen is not disturbed.

The configuration of each part of the present invention is not limited to the above embodiment, and it is needless to say that various modifications can be made within the technical scope described in the claims.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a video disc player according to the present invention, FIG. 2 is an explanatory diagram showing a signal writing and reading operation to a memory circuit, and FIG. 3 is a diagram showing a read operation failure in a conventional circuit. It is a figure explaining. (4) …… Memory circuit, (10) …… Changeover switch (12) …… Write / read control circuit (7) …… Write address counter (8) …… Read address counter Q …… Clock signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shinya Okuno, 2-18, Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (56) Reference JP-A-63-3583 (JP, A)

Claims (1)

[Claims] 1. A signal reading means (2) for reproducing a video signal from a signal recording medium, and a memory circuit (4) in which one field of the reproduced video signal obtained from the reading means (2) is written as a still image signal. And a circuit (12) for controlling writing and reading to and from the memory circuit (4), wherein the writing and reading control circuit (1
2) comprises a write address counter (7) and a read address counter (8) for counting clock signals from the same supply source to generate write and read address signals respectively, and the memory circuit (4) A video reproducing apparatus characterized in that write and read operations are performed in the same cycle T ₀ based on an address signal.