JPH0734528B2 - Differential amplifier - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit configuration of a differential amplifier that has a wide gain-sharing band and can be used as an amplifier, a combining circuit, and the like even in a high frequency band. (Prior Art) FIG. 4 shows a configuration of a conventional single-ended differential amplifier. Here, 1 and 2 are input terminals, 3 is a connection point, 4 is an output terminal, 5 is an RF bypass capacitor, and Q1 to Q5 are FETs. Since this differential amplifier uses FETs (Q3, Q4) as a load, it operates at a relatively low voltage and can obtain high gain, and is therefore widely used in ICs and the like. The operation of this differential amplifier will be described below using the RF equivalent circuit of FIG. 4 shown in FIG. _{Here, g m1, g m2, g} m4 are respectively Q1, Q2, Q4 _{transconductance, Z d1, Z d2, Z} d3, Z
_d4 is the drain-source parasitic impedance of Q1, Q2, Q3 and Q4 respectively, G, S and D are the gate source and drain of the FET respectively, v _i1 and v _i2 are the input voltage of terminal 1 and terminal 2, respectively
₀ is the output voltage of terminal 4, v ₁ and v ₂ are the gate-source voltage of Q 1 and Q ₂ , respectively, and v ₅ is the drain-source (ground) of Q _5.
Voltage, v ₃₄ is the gate-source voltage of Q4. Q3, Q5
Is a constant current source and has a very high impedance. Terminal
The output impedance of the circuit connected to 1, terminal 2 is Q1, Q
Assuming that the impedance is sufficiently smaller than the gate-source impedance of ₂ , v ₁ , v ₂ , and v ₅ are given by equation (1). v ₁ = (v _i1 −v _i2 ) / 2 v ₂ ＝ (v _i2 −v _i1 ) / 2 …… (1) v ₅ = (v _i1 + v _i2 ) / 2 where v _i1 = v _i2 v ₁ = v _{2 and} v ₀ = 0.
When v _i1 = −v _i2 , v ₅ = 0, and the gates of Q1 and Q2
V ₁ = (v _i1 −v _i2 ) and v ₂ = (v _i2 −
v _i1 ) is added. First, the voltage v ₃ output to 3 by v ₁
Since Q1 is a source-grounded FET that loads Z _d1 and Z _d3 , it becomes the formula (2). v ₃ = −g _m1・ (1 / Z _d1 + 1 / Z _d3 ) ^-1・ (v _i1 −v _i2 ) / 2 ……
(2) v ₃ is input to the source follower circuit in which the source of Q ₄ is loaded with Z _d2 , and the voltage v ₀₁ is output to terminal 4. v ₀₁ =

[G _m4 / (g _m4 + 1 / Z _d2 + 1 / Z _d4 )] ・ v ₃ …
(3) On the other hand, v ₂ is a drain-grounded FET in which the drain of Q4 is grounded
It is applied between the gate and source of the source-grounded FET Q2 whose load is. See Q4 from Q2 Impedance is 1 / (g _m4
+ 1 / Z _d4 ), and the voltage v ₀₂ is output to 4. v ₀₂ = -g _m2

[Z _d2 1 / (g _m4 + 1 / Z _d4 )] ・ v ₂ …
(4) In general, g _m Z _d >> 1 in the frequency band of several GHz or less, so if g _m1 = g _m2 = g _m4 , then v ₀₁ = −g _m1 (1 / Z _d1 + _1/1 / Z _d2 ) · v ₁ v ₀₂ = −v ₂ = v ₁ and v ₀₁ >> v ₀₂ . Therefore, v ₀ is determined only by v ₁ = (v _i1 −v _i2 ) / 2 applied between the gate and source of Q1. Here, if the drain-source capacitances and conductances of Q1 and Q3 are C _ds , G _ds , and ω is the angular frequency, respectively, 1 / Z _d1 + 1 / Z _d2 = 2 (G _ds + jωC _ds ) ... (6) _Therefore, the absolute value of the gain G _a is given by the equation (7). As shown in Expression 7, in the conventional differential amplifier, the denominator of the gain expression includes the term ωC _ds , which has a frequency dependence, so that the gain decreases as the frequency increases. (Problems to be Solved by the Invention) FIG. 6 shows an example of characteristics calculated using parameters of a general microwave band FET. As shown in the figure, the gain decreases near the frequency over 500 MHz, and the gain slope increases at frequencies above 1 GHz. For this reason, this kind of conventional differential amplifier could not be used in the 1 GHz band. An object of the present invention is to solve the above-mentioned drawbacks and to provide a single-ended amplifier having a small gain slope even at a high frequency of 1 GHz or higher. (Means for Solving Problems) A feature of the present invention is a circuit for suppressing the influence of the drain-source capacitance C _ds of the FET, which is the cause of the operating frequency limit of the conventional single-ended differential amplifier. Is added to improve the gain slope characteristic of the amplifier, which is characterized in that the second electrode of the second transistor is connected to the first electrode of the first transistor and the first electrode of the second transistor is connected.
Two unit circuits (A,
B), and the second of the first transistor of each unit circuit
The electrodes are commonly used and are grounded in an alternating current manner through a current source, and the third electrode of the second transistor of each unit circuit (A, B) is used as the first electrode of the first transistor of one unit circuit (A). In a single-ended differential amplifier in which the third electrode of the first transistor of each unit circuit (A, B) is used as an input terminal and the second electrode of the second transistor of the unit circuit (B) is used as an output terminal, This is a differential amplifier in which a series circuit of a capacitor and a resistor is provided between the first electrode and the third electrode of the second transistor of the unit circuit (A). As the transistor, a normal bipolar transistor or FET can be used. The first electrode corresponds to the drain or collector, the second electrode corresponds to the source or emitter, and the third electrode corresponds to the base or gate. (Example) shall apply in FIGS Figure 1 is for explaining an embodiment of the present invention, 6 resistance (Z _L), 7 is Kiyapashita (C _L), the others are the same as in Figure 4. Here, 7 is a capacitor for preventing direct current from flowing through Z _L , and it is desirable that C _L has a sufficiently large value so that the impedance can be ignored at the operating frequency. This C _L makes the DC bias condition of this circuit the same as the conventional circuit. As shown in the first (2), the gain G _a in the absence of Z _L (Z _L = ∞) is Given in. Here, G _ds and C _ds are the drain-source conductance and capacitance of Q1 and Q3. In order to maintain a flat gain band up to a higher frequency, in the present invention, a resistor Z _L is added between the drain and source of Q1 and Q3 in terms of RF. As a result, the gain G _a ′ is given by equation (8). As Z _L becomes smaller, the frequency at which the effect of C _ds appears becomes higher, and good amplification characteristics with a small gain slope can be realized even at high frequencies of 1 GHz or higher. In order to verify the effect of Z _L described above, the second example of characteristic calculation of the circuit shown in FIG.
Shown in the figure. The FET used here is the same as that in FIG. 6, and Z _L << 1 / ω _{C ds} . As shown in the figure, flat and good characteristics are obtained even in the 3 GHz band. Although the case where the transistor is a FET has been described above, a bipolar transistor operates similarly. NPN
An example of using a transistor is shown in FIG. The principle of operation is the same as in the case of FIG. (Effects of the Invention) As described above, according to the present invention, the influence of the parasitic capacitance of the FET in the single-ended differential amplifier is removed, and the configuration is such that it can operate in the high frequency band of 1 GHz or higher. There is an advantage that it can be applied in a wide range. For example, amplification of the IF output of the microwave mixer, combination of two IF outputs of the microwave double-balanced mixer, and the like can be considered.

[Brief description of drawings]

1 is an embodiment of the present invention, FIG. 2 is a diagram showing calculated values of gain frequency characteristics of the circuit of FIG. 1, FIG. 3 is another embodiment of the present invention, and FIG. 4 is a conventional single end. Configuration of a differential amplifier, FIG. 5 is an RF equivalent circuit of the circuit of FIG. 4, and FIG.
It is a figure which shows the calculated value of the gain frequency characteristic of the circuit of the figure. 1,2 ... input terminal, 3 ... connection point, 4 ... output terminal, 5 ... bypass Kiyapashita, 6 ... resistance (Z _L), 7 ... Kiyapashita _{(C L), Q1~Q5 ... FET} , G, D, S … FET gate, drain, source, g _m1 , g _m2 , g _m4 … Q1, Q2, Q4 transconductance, Z _d1 , Z _d2 , Z _d3 , Z _d4 … Q1, Q2, Q3, Q4 drain source Parasitic impedance, v _i1 , v _i2 ... input terminal, v ₀ ... output terminal, v ₁ , v ₂ ... Q1, Q2 gate-source voltage, v ₅ ...
Q5 drain-source voltage, v ₃₄ … Q4 gate-source voltage.

Claims (1)

[Claims] 1. Two unit circuits (A) in which the first electrode of the first transistor is connected to the second electrode of the second transistor and the first electrode of the second transistor is AC grounded. , B), the second electrode of the first transistor of each unit circuit (A, B) is common, and is grounded in an alternating current manner through a current source. The third electrode of the two transistors is connected to the first electrode of the first transistor of one unit circuit (A), the third electrode of the first transistor of each unit circuit (A, B) is used as an input terminal, and the other unit is connected. In a single-ended differential amplifier using the second electrode of the second transistor of the circuit (B) as an output terminal, a capacitor is provided between the first electrode and the third electrode of the second transistor of the one unit circuit (A). Differential amplification characterized in that a series circuit with a resistor is provided vessel.