JPH0734470B2 - Field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a field-effect semiconductor device, here, a power MO.
S field effect transistor (hereinafter referred to as power MOS FET)
More specifically, the present invention relates to improvement of a high-breakdown-voltage power MOS FET with low on-resistance.

[Conventional technology]

In recent years, this kind of power MOS FET has been attracting attention as a switching element for electric power.

FIG. 2 shows an outline of a sectional structure schematically showing a power MOS FET having a general vertical D-MOS structure according to a conventional example.

That is, in the conventional configuration shown in FIG. 2, n ⁺
In this case, the shaped substrate 21 is generally about 10 ¹⁹ atom / cm ³
In such a slow diffusion speed Sb is used and the n n ⁺ is epitaxially grown on the shape the substrate 21 ^- -type epitaxial layer 22, Yotsute the blocking voltage V _B that is required in the device structure, its resistivity and The thickness is set, for example, in the device configuration of 500 V, the specific resistance is about 25 Ω-cm and the thickness is about
It is set to about 45 μm.

The p-type base layer 23 selectively formed on the main surface (second main surface) of the n ⁻ -type epitaxial layer 22 is a relatively shallow diffused second region portion forming the channel region 25. 23b and n formed on the surface of the p-type base layer 23
And a first region portion 23a formed relatively deeply to prevent latch-up of a parasitic transistor constituted by the ^{+ type} source layer 24, the p type base layer 23, and the n ^{− type} epitaxial layer 22. ing.

Then, on the channel region 25 formed between the n ^{+ -type} source layer 24 and the n ⁻ -type epitaxial layer 22, a gate electrode 27 is formed to cover the n ⁻ -type epitaxial layer 22 and via the gate insulating film 26. , The first region portion 23a of the p-type base layer 23 to n ⁺
The source electrode 28 straddles the n-type substrate 21 and the n ^{+ -type} substrate 21.
A drain electrode 29 is formed on the back surface of each.

Then, the power MO in the conventional example configured as described above
In the S FET, the source electrode 28 is grounded and the gate electrode 2
When a positive voltage is applied to 7 and the drain electrode 29, p
Channel region 25 in the form the base layer 23 is inverted to n ⁺ type, as indicated by a broken line e in the drawing, the inverted channel region 25 of n ⁺ -type source layer 24, and the n ^- -type epitaxial layer 2
Electrons flow through the drain electrode 29 through 2 to be in the ON state.

At this time, the on-resistance R _on of the element can be approximately represented by the following equation. _{That, R on = R ch + R} ac + R j + R Epi However, R _ch: the resistance of the channel region 25, R _ac: n ^- Akyamu Configuration resistance of the surface of the -type epitaxial layer 22, R _j: p-type base layer resistance of the n-type epitaxial layer 22 indicating the JFET effect sandwiched by 23, R _Epi: n ^- resistance -type epitaxial layer 22. Is.

Here, the resistors R _ch and R _ac can be reduced together by miniaturizing the unit cell of the MOS FET and increasing the channel length, and the resistors R _j can be reduced in the p-type base layer. Although it can be reduced by appropriately widening the interval between 23, the resistance R _Epi is determined by the relationship with the blocking voltage V _B , so in a high breakdown voltage element, it occupies most of the on resistance R _on. In this case, for example, in the device configuration of 500V and 1000V, the respective R _Epi / R _on are about 0.8 and 0.9.
However, how to reduce the resistance R _Epi is a major point for improving the characteristics of this type of high voltage MOS FET.

[Problems to be solved by the invention]

As described above, in the power MOS FET having the conventional configuration, when the breakdown voltage of the element increases, the on-resistance in the n ^{− type} epitaxial layer that defines the blocking voltage V _B increases, and the on-loss increases. Atsuta

Therefore, the purpose of this invention is
In view of these problems in MOS FETs, the resistance R _Epi in the n ^{− type} epitaxial layer is reduced to improve the characteristics of the device structure. This is to provide a high-voltage power MOS FET with low on-resistance, which is an effective semiconductor device.

[Means for solving problems]

To achieve the above object, a field-effect semiconductor device according to the present invention comprises an n ^{+ -type} substrate doped with P, and an n ⁻ -type epitaxial layer provided via a bonding surface between the substrate and the n − -type substrate. And a raised region for forming a gradual impurity concentration distribution between the substrate and the epitaxial layer, which is formed in the junction surface of the epitaxial layer, and selectively formed on the main surface of the epitaxial layer. A p-type base region including a first region portion that is a central portion and a second region portion that is provided on the periphery of the first region portion and has a depth to the bottom that is shallower than the first region portion, and each of these base regions. An n-type source region selectively formed on the surface of the substrate, a gate electrode formed on the surface of a second region portion sandwiched between each source region and the epitaxial layer via a gate insulating film, and each base. region A source electrode formed over the source region from the first region portion, in which a drain electrode formed on the substrate.

In addition, an n-type semiconductor layer is further formed in the surface of the epitaxial layer between the second region portions facing each other of each base region, and the second region portion in which the gate electrode is sandwiched between the source region and the semiconductor layer is formed. It is formed on the surface via a gate insulating film.

[Action]

Therefore, in the present invention, the on-resistance R in the element configuration is
_Since the layer thickness of the n ⁻ -type epitaxial layer that most affects _on is made sufficiently thin, this on-resistance R _on can be reduced as compared with the conventional example.

Further, regarding the resistance R _{j in} the region portion of the n-type semiconductor layer sandwiched between the p-type base layers, the interval between the p-type base layers is
When L _p is shortened, it becomes large due to the JFET effect, so that the same interval L _p needs to be wide, but since the same region portion is made of an n-type semiconductor layer having a relatively low resistance, The resistance L _j can be reduced by shortening the interval L _p, and at the same time, since the density of the MOS unit cells themselves can be increased, the resistance R _{ch of the} channel region can also be reduced.

On the other hand, with respect to the breakdown voltage of this element structure, the electric field of the depletion layer extending when a high voltage is applied is relaxed by the gentle slope of the impurity concentration distribution at the n ⁺ and n ⁻ junctions. Therefore, even if the layer thickness of the n ⁻ -type epitaxial layer is reduced, the blocking voltage V _B is not likely to be impaired.
As a result of these, it is possible to obtain a power MOS FET having a low on-resistance and a high device breakdown voltage.

〔Example〕

An embodiment of a field effect semiconductor device according to the present invention, a power MOS FET here, will be described in detail below with reference to FIG.

FIG. 1 is a sectional view schematically showing a schematic structure of a power MOS FET to which this embodiment is applied. In the structure of the embodiment of FIG. 1, the same symbols as those of the structure of the conventional example of FIG. Represents a part.

That is, even in the configuration of the embodiment shown in FIG.
In this case, the n ^{+ -type} substrate 11 is generally about 10 ¹⁹ to 10 ^20.
an n-type impurity such as large phosphorus the atom / cm ³ order of the diffusion coefficient, on the n ⁺ type substrate 11, n has a high resistivity of about 25~30Ω-cm ^- about 50μm to form epitaxial layer 22 The n ^{+ -type} substrate 11 is lifted to the n ⁻ -type epitaxial layer 22 side by about 25 μm to form the floating region 12 by forming the n ^{+ -type} substrate 11 and the n ^{+ -type} substrate 11 by heating the n ^{+ -type} substrate 11 to a thickness of about 25 μm. and n ^- give Yururu Ya kana impurity concentration distribution between -type epitaxial layer 22.

Next, the first region of each p-type base layer 23 is opposed to the second main surface of the n ⁻ -type epitaxial layer 22 by a depth of about 5 to 10 μm by an ion implantation method or a selective diffusion method. part
23a are selectively formed, and each first area portion 2
N between 3a ^- on the surface of the -type epitaxial layer 22, to form an n-type semiconductor layer 30 of a relatively low resistance One by the ion implantation or the like Toka selective diffusion method. In this case, each first area part
It shall apply prior to forming a 23a, n ^- -type epitaxial layer 22
The n-type semiconductor layer 30 may be formed on the surface of the substrate by an epitaxial growth method, an ion implantation method, a selective diffusion method, or the like.

Next, a gate insulating film 26 is formed on these, and a polysilicon layer which will later become a gate electrode 27 is selectively formed via this gate insulating film 26, and each polysilicon layer is used as a mask to form a mask. The second region portions 23b of the p-type base layer 23 are selectively formed. That is, in this case, the n-type semiconductor layer 30 is formed in each of these second region portions.
It will be sandwiched between 23b. Since each of these second region portions 23b later becomes the channel region 25, it is necessary to select the impurity concentration and the diffusion depth thereof in relation to the threshold voltage V _th , In that case, the value is within the range of 5 × 10 ^{13 to} 5 × 10 ¹⁴ cm ^-3 and the depth is 4
It may be about 6 μm.

Next, each of the p-type base layers 23 has a surface concentration of about 3 × 10 ²⁰ atom / cm ³ by the D-MOS method using the above-mentioned polysilicon layer as a mask. The n ^{+ type} source layer 24 is selectively formed to a depth of about 0.5 to 1 μm. Then, each second region portion 23b sandwiched between each of the n ^{+ type} source layers 24 and the n type semiconductor layer 30.
The surface portion of is the above-mentioned channel region 25, and the length of this channel region 25 is about 3 to 5 for a high breakdown voltage MOS FET.
It is about μm.

Further, each of the n ^{+ type} source layer 24 and the n ^{− type} epitaxial layer
A gate electrode 27 is formed on each of the channel regions 25 formed between the p-type base layer 23 and the channel region 25, and a gate electrode 27 is formed on the channel region 25 via the gate insulating film 26. 23a to the source electrode 28 across the n ^{+ type} source layer 24,
A drain electrode 29 is formed on the back surface of the n ^{+ -type} substrate 21, respectively.

Therefore, the power of this embodiment configured as described above
In the MOS FET, the thickness of the n ⁻ -type epitaxial layer 22 is reduced, that is, specifically, in the case of this embodiment,
It is set to about 15 to 20 μm, and when compared with the thickness of the same layer of about 35 to 40 μm in the case of the conventional example, the value of the resistance R _Epi is drastically reduced because it is thinned to about 1/2. It can be reduced. At this time, the floating region 12 is formed to have a thickness of about 25 to 30 μm. However, since the average specific resistance thereof is 1/10 or less of the specific resistance of the n ⁻ -type epitaxial layer 22, the resistance R _Epi is almost the same. This is no longer the case, and even with this, the resistance R _on can be reduced to about 20 to 30% when compared to the conventional example.

The second area portion 23b of the high resistance of the conventional example sandwiched between n each p-type base layer 23 ^- the form epitaxial layer 22, in the case of this embodiment, a relatively low resistance n-type semiconductor layer of Since it is formed by 30, the JFET effect in the same n-type semiconductor layer 30 is weakened, and when compared with the conventional example, the interval L _p between each p-type base layer 23 can be shortened, MO per unit area
The S unit cell density can be increased, and as a result, the values of the resistances R _j and R _ch can be improved to about 35-40%.

That is, as described above, according to the power MOS FET in the configuration of this embodiment, the value of the on-resistance R _on is improved by about 35 to 40% as compared with that of the configuration of the conventional example. You can do it.

Incidentally, in the above-mentioned examples, the element structure having a breakdown voltage of 500 V was described, but even with a high breakdown voltage element having a breakdown voltage of 500 V or more, the specific resistance and thickness of the n ^{− type} epitaxial layer corresponding to each breakdown voltage, By appropriately setting the specific resistance and thickness of the n-type semiconductor layer, and the thickness of the lifted region in the lifted region to the n ⁻ -type epitaxial layer, similar effects can be obtained. Further, in this embodiment, the case where the p-type is used as the first conductivity type and the n-type is used as the second conductivity type is described, but it goes without saying that reversing these conductivity types is also effective.

〔The invention's effect〕

As described above in detail, the field-effect-type semiconductor device according to the present invention includes an n ^{+ -type} substrate doped with P, and an n ⁻ -type epitaxial layer provided via a bonding surface with the substrate. , A floating region formed in the junction surface of this epitaxial layer and selectively facing the main surface of the epitaxial layer and a raised region for giving a gentle impurity concentration distribution between the substrate and the epitaxial layer, and its center A p-type base region including a first region portion that is a portion and a second region portion that is provided on the periphery of the first region portion and has a depth to the bottom that is shallower than the first region portion; An n-type source region selectively formed on the surface, and a gate electrode formed on the surface of a second region portion sandwiched between each source region and the epitaxial layer via a gate insulating film,
The base electrode is formed between the first region portion of each base region and the source region, and the drain electrode is formed on the substrate, and is between the mutually opposing second region portions of each base region. N within the surface of the epitaxial layer
Since the gate electrode is formed via a gate insulating film on the surface of the second region portion sandwiched between the source region and the semiconductor layer with further forming a semiconductor layer in the form, the largest on-resistance R _on in the device structure The on-resistance R _on can be reduced as compared with the conventional example by making the layer thickness of the affected epitaxial layer sufficiently thin, and the semiconductor layer sandwiched between the base layers has a relatively low resistance. Therefore, even if the distance L _p between these base layers is shortened, the resistance R _j can be reduced, the density of the MOS unit cells themselves can be increased, and the resistance R _{ch in the} channel region can be reduced. ,
In both the element structure and the breakdown voltage, the electric field of the depletion layer that extends when a high voltage is applied is relaxed by the gentle slope of the impurity concentration distribution at the junction, so The blocking voltage
V _B is not likely to be impaired, and as a result, it is possible to obtain a power MOS FET with low on-resistance and high element breakdown voltage, and it is also structurally relatively simple and easy to implement. It has the following features.

[Brief description of drawings]

FIG. 1 shows a power MOS to which an embodiment of the device of the present invention is applied.
FIG. 2 is a cross-sectional view schematically showing the general structure of the FET, and FIG. 2 is a cross-sectional view schematically showing the general structure of the same power MOS FET as the conventional example. 11 …… n ^{+ type} substrate, 12 …… floating region, 22 …… n ^{− type} epitaxial layer, 23 …… p type base layer, 24 …… n ^{+ type} source layer, 25 …… channel region, 26 …… Gate insulating film, 27 ……
Gate electrode, 28 ... Source electrode, 29 ... Drain electrode,
30 ... n-type semiconductor layer.

Claims (2)

[Claims] 1. An n ^{+ -type} substrate doped with P, an n ⁻ -type epitaxial layer disposed via a bonding surface of the substrate, and an n ⁻ -type epitaxial layer formed in the bonding surface of the epitaxial layer, A floating region for giving a gentle impurity concentration distribution between the substrate and the epitaxial layer, and a first region portion which is formed so as to selectively face the main surface of the epitaxial layer and is a central portion thereof. A p-type base region, which is provided on the periphery of the first region portion and includes a second region portion having a depth to the bottom that is shallower than the first region portion, and selectively formed on the surface of each base region. an n-type source region, a gate electrode formed on the surface of the second region portion sandwiched between each source region and the epitaxial layer via a gate insulating film, and a first region portion of each base region From Serial field effect semiconductor device having a source electrode formed over the source region and a drain electrode formed on the substrate. 2. An n-type semiconductor layer is further formed in the surface of the epitaxial layer between the second region portions facing each other in each base region, and a gate electrode is formed in the source region and the semiconductor layer. The field-effect semiconductor device according to claim 1, wherein the field-effect semiconductor device is formed on the surface of the sandwiched second region via a gate insulating film.