JPH0734223B2 - Display controller - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial field of application Conventional technology (Fig. 4) Problems to be solved by the invention Means for solving the problems (Fig. 1) Operation Example (a) ) Description of one embodiment (FIGS. 2 and 3) (b) Description of another embodiment [Effect of the invention] [Overview] A composite image signal of a composite screen obtained by reading out image data of a plurality of screen regions and then combining In the screen synthesis control method to obtain,
By using a memory having a page mode function, allocating a plurality of screen areas to the memory, and reading image data from each of the plurality of screen areas within one memory cycle, the screen contents can be independently controlled and the memory It was designed so that it would be less.

[Industrial application field]

The present invention relates to a display control device for displaying a composite screen having a plurality of bitmap format screen areas, and in particular, a composite image signal for a composite screen can be obtained even if a plurality of screen areas are allocated to one memory. The present invention relates to a display control device.

2. Description of the Related Art In recent years, devices such as engineering workstations (EWS) that display an image on a display device and perform desired processing while viewing the image have appeared.

In these devices, there is a demand for combining and displaying a plurality of images in response to a demand for advanced image processing.

[Conventional technology]

 FIG. 4 is an explanatory diagram of a conventional technique.

For example, consider an example in which a crosshair cursor CC is compositely displayed on an image PI.

Generally, the crosshair cursor CC is, as shown in FIG. 4 (A), a display (display device) 1 of a workstation.
Is used by the operator to indicate a point to be indicated on the screen, and forms a cross shape that almost fills the screen, and is moved by a cursor movement key of a keyboard (not shown).

In order to synthesize and display the image PI and the crosshair cursor CC, a method is known in which the crosshair cursor CC is directly written in the screen area 2a of one screen for writing the image PI in the memory 2.

Since the screen area 2a is a bitmap format, a composite image (video) signal of the image PI and the crosshair cursor CC can be obtained by simply reading the screen area 2a, and composite display can be performed on the display 1.

On the other hand, as shown in FIG. 4 (C), in addition to the screen area 2a of the image PI, a screen area 3a for one screen is provided for the crosshair cursor CC.
A method of preparing is also known. In this system, both screen areas 2a and 3a are read out, the read data is converted by PS converters (parallel-serial converters) 21 and 31, and then synthesized by an OR circuit 4 to obtain a synthesized video signal. Is.

[Problems to be solved by the invention]

In the conventional one shown in FIG. 4 (A), in the case of a high-speed moving object such as a cursor, the crosshair cursor is rewritten in the screen area 2a to realize the cursor movement.

Therefore, when the cursor is moved, the data saved in the save memory 20 at the position corresponding to the current cursor position in the screen area is first written in the screen area 2a, the cursor position is updated next, and this update is performed. The data of the screen area 2a at the different position is read and saved in the save memory 20, and then the logical sum of the read data and the cursor data is taken and the data of the logical sum is written in the screen area 2a.

That is, in order to mix the image PI and the cursor CC, which is another image, in one screen area 2a, the cursor CC is overwritten on the image PI and the image PI changes. Therefore, when moving the cursor CC, the overwriting is performed. Such processing is necessary to restore the image that has been erased.

Therefore, when rewriting one image (cursor) CC, complicated saving and restoring processes are required, and there is a problem that the moving process (rewriting process) of the cursor or the like cannot be speeded up.

On the other hand, in the method of FIG. 4 (C), since the cursor data exists in another screen area 3a, when rewriting, FIG. 4 (B)
No such processing is required.

However, when the screen areas 2a and 3a are set on the same memory surface, two read operations are required to read the two image data to be combined, which may delay the video rate of the display 1.

Therefore, the two screen areas 2a and 3a have different memory surfaces 2 and 3, respectively.
Is mapped (set) to both memories 2 and 3 at the same time.

Generally, as memory configuration, byte (8 bits) is read at 1 address, so 1 IC chip is 1 at 1 address.
Since only bits can be output, at least 8 chips are required as one memory.

For example, if a 256 Kbit IC chip is used, the memory 2, 3
Requires eight 256Kbit IC chips, 16 in total.

For this reason, there has been a problem that the physical quantity of the memory increases, resulting in an increase in cost and an increase in space.

It is an object of the present invention to provide a display control device that can reduce the amount of hardware of a memory and can store each image data independently.

[Means for solving problems]

 FIG. 1 is an explanatory view of the principle of the present invention.

In the figure, the same components as those shown in FIG. 4 are designated by the same symbols, and 2'is a page mode memory.
The first screen area 2a for one screen and the third screen area 2b for one screen are provided, and the image data data 1 from each of the screen areas 2a, 2b within one memory cycle using the page mode. The data 2 is read.

Reference numeral 22 is a PS converter.

[Action]

In order to solve the conventional problems, it is necessary to separate image data (image data and cursor data) and to perform address mapping on the same memory.

The present invention accomplishes this by utilizing the page mode of memory.

Generally, a dynamic memory gives a row address and a column address, determines the address, and manipulates data. However, as shown in FIG.
There is a memory capable of manipulating two data by giving two column addresses in the same cycle to one row address, which is called a page mode function memory.

Therefore, in the page mode memory 2 ', a plurality of screen areas 2
If a and 2b are provided and the column address 1 of one screen area 2a and the column address 2 of the other screen area 2b are given in one memory cycle, the image data of both screen areas 2a and 2b (data 1, data 2) Can be read in the same memory cycle, and a combined image (video) signal can be obtained by the logical sum of the two.

RAS and CAS are memory control signals, RAS is a row address strobe, and CAS is a column address strobe.

Therefore, it is possible to store a plurality of screen areas in one memory and read them simultaneously (same memory cycle).

〔Example〕

 (A) Description of an Embodiment FIG. 2 is a configuration diagram of an embodiment of the present invention.

In the figure, the same components as those shown in FIGS. 1 and 4 are designated by the same symbols, 5a is a memory control circuit, and RAS, CAS, and RAE (row address enable) within a memory cycle. , CAE (column address enable) 1/2, those that issue memory control signals for latch enable, PS conversion enable, and 5b is an address conversion circuit, which receives an absolute address from a CRT controller, which will be described later, and outputs a row address and a 2
Create one column address 1 and 2 and give address to memory 2'in synchronization with RAE, CAE1 / CAE2, 6 is CPU
(Processor) which accesses the memory 2'on request, 7 is a CRT (display) controller,
A unit which outputs a read absolute address in synchronization with the display, a CPU bus 8 for exchanging data, an address and a control signal, and a flip-flop 23 for latching the first data from the memory 2 ' To do.

In this embodiment, the screen area 2a for the image is the column address "0000" to "0FFF" of the memory 2 ', and the screen area 2b for the cursor is the column address "1000" of the memory 2'.
To "1FFF" are mapped.

When the CPU 6 accesses the image data or the cursor data, the screen areas 2a and 2b to be stored are mapped to different addresses of the memory 2 ', so if the corresponding address is directly read / written via the CPU bus 28. Good.

For example, to move the cursor, use the column address "10
Directly erase the cursor data in screen area 2b from address "00" to address "1FFF" and write directly to the updated cursor address.

Next, the read operation will be described with reference to the operation explanatory view of FIG.

CRTC7 acquires the CPU bus 8 by cycle stealing and supplies the absolute address to the address conversion circuit 5b.

At the same time, the memory control circuit 5a gives a row azoless enable signal RAE to the address conversion circuit 5b and outputs the row address to the memory 2 '.
Use the row address strobe RAS to determine the row address.

Next, the memory control circuit 5a uses the row address enable RAE.
Column address enable CAE1 is applied to the address conversion circuit 5b to output the column address (column 1) of the screen area 2a to the memory 2 ', and the memory 2'is determined by the column address strobe CAS of the memory control circuit 5a. The 8-bit parallel image data of the screen area 2a is output by the row address and the column address.

This image data is held by the latch enable signal provided to the flip-flop 23 by the memory control circuit 5a.

Next, the memory control circuit 5a uses the column address enable CA.
E2 is given to the address conversion circuit 5b, and the latch enable and column address enable CAE1 are turned off.

The address conversion circuit 5b outputs the column address (column 2) of the screen area 2b to the memory 2 ', and the memory 2'uses the row address determined by the column address strobe CAS of the memory control circuit 5a and the screen area according to this column address. Output 2b 8-bit parallel cursor data. At the same time, that is, when the 8-bit parallel image data and the cursor data are both determined, the memory control circuit 5a provides the PS conversion enable to the PS conversion circuits 21 and 22, so that both PS conversion circuits 21 and 22 are enabled. Outputs 8-bit serial image data and cursor data, performs a logical sum by the logical sum circuit 4 bit by bit, and outputs the result as a composite image signal, which is synchronized to form a video signal.

The memory 2'is periodically accessed so that the video signal is not interrupted, whereby the composite image of the contents of the screen areas 2a and 2b is displayed on the display 1.

In this way, using the page mode of the memory 2 ',
Data in the screen areas 2a and 2b can be read within one memory cycle and a video signal can be output by the logical sum of these.

(B) Description of Other Embodiments In the above embodiments, the combination of the image PI and the crosshair cursor CC is taken as an example, but one image and another image may be combined.

Since the memory with page mode can output at least two column addresses for one row address,
It is also possible to compositely display three or more screen areas by outputting three or more column addresses.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention, and these modifications are not excluded from the present invention.

[Effects of the Invention] As described above, according to the present invention, since a plurality of screen areas are mapped in the memory, the amount of hardware is significantly reduced as compared with the case where a memory is provided for each screen area. This has the effect of contributing to space saving and cost reduction.

In addition, since the memory with page mode is used, it is possible to map multiple screen areas to the same memory and operate the screen areas independently, and read the data of multiple screen areas in the same memory cycle. It is possible to output the synthesized image signal easily, and to update the screen area easily.

[Brief description of drawings]

 FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram for explaining an embodiment of the present invention, FIG. 3 is a diagram for explaining the operation of an embodiment of the present invention, and FIG. 4 is a diagram for explaining a conventional technique. In the figure, 1 ... Display, 2, 3 ... Memory, 2 '... Memory with page mode, 2a, 2b ... Screen area.

Claims (1)

[Claims] 1. An image area for a screen (2
a, 2b), a display control device for reading image data from each of the plurality of screen areas (2a, 2b) and synthesizing to obtain a synthesized image signal, a plurality of different addresses in one memory cycle. A memory (2 ') having a page mode function for reading the data of the above and provided with the plurality of screen areas, and the plurality of screen areas (2a, 2a) in the memory (2') during one memory cycle. 2b) memory controller (5a, 5b) for giving a plurality of different addresses, and a plurality of screen areas (2a, 2b) read from the memory (2 ') in one memory cycle. A display control device comprising: a synthesizing unit (21 to 23) that synthesizes respective image data to obtain the synthesized image signal.