JPH07336735A - Time division time switch lsi - Google Patents

Abstract

PURPOSE:To obtain a time division time switch realized in one-chip with high circuit integration density in which an operating speed of a memory is maintained at high speed in matching channel multiplex degree. CONSTITUTION:Serial information supplied from highways HWIN0-HWIN3 whose multiplex degree is m-channels is given to a serial parallel conversion circuit S/P and a multiplexer MUX, in which the speed is converted into a multiple of 4 and the resulting information is sequentially written in channel memories SPM0, SPM1 having number of addresses corresponding to all channel multiplex degree of mX4. Then the information read at random from the memories SPM0, SPM1 for time position rearrangement is given to a demultiplexer DMUX and a parallel serial conversion circuit P/S, in which the speed is converted into a multiple of 1/4 and the resulting information is distributed and outputted to the highways HWOUT0-HWOUT3 whose multiplex degree is m-channels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division time switch LSI provided in a communication path section of a time-division electronic exchange.

[0002]

2. Description of the Related Art There is a time division multiplex transmission line (highway) for transmitting a digital signal through a plurality of time division multiplexed digital lines. A time division switching system is used to arbitrarily exchange and connect the time division digital lines formed on such a highway. For example, a time division switching system uses a voice signal in a pass band (0.3 to 3.4 KH).
z), which is sampled at a frequency more than twice the frequency (for example, 8 KHz), the multi-channel information is time-division multiplexed on the highway, the time positions (time slots) are exchanged, or the same highway is used among a plurality of highways. Arbitrarily exchange digital circuits by spatially exchanging channels
Connecting. For such a time division exchange system, a time division time switch is used which performs time exchange / connection by exchanging highway time slots.

In the time division time switch of the time division exchange system, a speech path memory for writing the digital signals transmitted by the highway in the order of addresses and reading it randomly according to the time slot address of the other party to be connected, and this speech. A control memory is provided that supplies a random read address to the path memory.

A speech path memory and a control memory of such a time division time switch are described in, for example, “ISSC: International Sol” issued in February 1982.
id State Circuits Confere
No.) ”SESSION XVI pages 214-215
Page. Another example of the time division speech path switch VLSI is the IEICE English journal (IEI).
CE Transactions, Vol. E74, N
o. 11, pp1020-1027, November
1991).

[0005]

The time division switching system is provided with a relatively large number of time division time switches as described above. As the number of exchange channels increases, the speech path memory constituting these time division time switches must have a larger memory scale and a correspondingly higher operating speed. For example, in a 4K channel multiple time division time switch, the memory cycle frequency is 32.
In the 8K channel multiplex time division time switch, the frequency is doubled to 64 MHz, and in the 16K channel multiplex time division time switch, it is further doubled to 128 MHz. That is, assuming that the audio signal is sampled at 8 KHz per channel, the processing speed is 8 KHz x 4 K for exchanging information of 4 K channels transmitted by time division multiplexing.
(Channel) = 32 MHz, the processing speed is 8 KHz × 16 K (channel) = 128 M for exchanging information for 16 K channels transmitted by time division multiplexing.
This is because it is set to Hz.

At this time, for example, when a 16K channel multiplex time division time switch is configured by using a 4K channel multiplex time division time switch LSI, if only four such LSIs are used in terms of the storage capacity of the speech path memory, the respective LSIs are used. Operating frequency of speech path memory is 32MH
Since it is z, it is not possible to satisfy the required processing capacity, and it is possible to try to improve the apparent processing capacity by using 16 of them, but in that case, some additional It is necessary to consider various circuit configurations and
It has been clarified by the present inventor that it is difficult to realize it by increasing the space efficiency because individual LSIs must be arranged.

That is, with the recent progress in semiconductor miniaturization processing technology using CMOS, a 16K channel multiple time division time switch has been provided with high density so that it can be integrated into one chip. At the same time, the circuit technology of the above-mentioned memory mounted on the chip has been improved so that the memory can be operated at a high speed such as 128 MHz. The fact that the operation speed of the speech path memory is not doubled or quadrupled while maintaining the channel multiplicity or the switch multiplicity as much as necessary is not considered.
This means that it is necessary to prepare twice or four times the hardware amount of the memory, which is against the direction of higher density.

An object of the present invention is to realize a high-density time-division time switch on a single chip by keeping the operation speed of the memory high and increasing the density in proportion to the channel multiplicity of the time-division time switch. Especially.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the exchange of signals between LSIs is
Since it goes through the input / output circuit of the LSI and is performed through the wiring on the printed circuit board on which the LSI is mounted, it is not always possible to obtain high speed corresponding to the semiconductor microfabrication technology due to physical restrictions. Absent. For example, CM for communication
The maximum speed of signal exchange between the OS and LSI is about 50 MHz to 60 MHz. Therefore, for example, 16K channel multiplex time division time switch LS
Considering I, the processing speed of 128MHz
Cannot be directly used as the interface speed of the LSI. Even if such a high-speed interface time-division time switch LSI is designed, signals cannot be reliably exchanged, and the time-division time switch cannot be used well. In the present invention, by operating the inside of the LSI at a high speed for maintaining high density and adopting a low-speed interface between the LSI and an external signal, a time division time switch having a large multiplicity can be integrated into one chip. At the same time, we try to realize an easy-to-use LSI.

Specifically, a plurality of n highways each having a multiplicity of m channels can be connected, and the information input from the highways by time division multiplexing can be exchanged and output to a plurality of highways. A time-division time switch LSI integrated into one chip has a first speed conversion circuit for speed-converting information supplied from each of the plurality of highways by n times, and all channel multiplicity m × n of the n highways.
And a speech path memory for storing the information output from the first speed conversion circuit in a readable / writable manner in a memory cycle of a speed synchronized with the speed, and from the speech path memory. A second speed conversion circuit for speed-converting the information read in a predetermined order to 1 / n times and supplying it to n highways.

As another aspect, information of a plurality of channels sampled at a predetermined frequency f (eg, 8 KHz) is transmitted by time division multiplexing with channel multiplicity m (eg, 4 K channels). An input terminal and an output terminal can be coupled to a plurality of highways of a number n (for example, 4), and the positions of information supplied from the plurality of highways by time division multiplexing can be exchanged to output to a plurality of highways. The time-division time switch LSI is set to the multichannel multiplicity m × n of a plurality of highways of the above-mentioned parallel number n.
Has a number of addresses corresponding to (16K channels),
And the velocity determined by m × n × f (eg 128
MHz), a speech path memory that is read / written in a memory cycle, and a first speed conversion circuit that converts the information supplied from each of the plurality of highways to n times the speed and supplies the information to the speech path memory. A second speed conversion circuit for converting the speed of the information read from the communication path memory in a predetermined order by a factor of 1 / n and supplying the speed information to a plurality of highways of the parallel number n. The time-division time switch LSI configured by this has a channel multiplicity of channels or a switch multiplicity of 16K channels.

Considering that writing to the speech path memory is performed without interruption, in order to relatively easily realize parallel reading, a pair of the speech path memories described above are provided, and one speech path memory is mutually provided. It is advisable to provide a speech path memory control circuit for controlling the other speech path memory for reading during writing to.

In order to relatively easily switch the operation of the pair of speech path memories, a counter is provided which performs counting operation at a speed synchronized with the memory cycle of the speech path memory.
The count value output from the counter may be input to the speech path memory control circuit to generate a write address for the speech path memory and an operation switching control signal for the pair of speech path memories.

In order to easily realize random reading from the speech channel memory, a read / write operation is carried out in the same memory cycle as that of the speech channel memory having a number of addresses corresponding to the above-mentioned all-channel multiplicity m × n. Control memory and read address information for reading the information stored in the communication channel memory are controlled to be written in the control memory according to an instruction from the outside through a microcomputer interface and the count output from the counter. It is possible to employ a control memory control circuit in which the information read from the control memory with the value as the address is used as the read address of the communication path memory.

In order to write the random read address for the channel memory into the control memory in parallel with the read operation, the control memory is divided into two, and the control memory control circuit is connected from the microcomputer interface. According to the instruction of 1, the read control for one of the divided control memories may be made write-accessible to the other in parallel.

In order to eliminate the need for directly supplying a high frequency clock signal defining the memory cycle of the communication path memory or the like from the outside, a clock of a frequency defining the same speed as the information transmission speed on the highway. A phase-locked loop circuit for receiving a signal from the outside and generating a clock signal for the communication path memory or the like may be incorporated in the same chip.

[0019]

According to the above-mentioned means, the communication path memory and the control memory have addresses according to the multiplicity of all channels of the connectable highways, and have an operating speed that does not cause an empty cycle. A switch multiplicity corresponding to the total channel multiplicity is realized. In other words, the communication path memory and the control memory do not require a storage area larger than the storage capacity corresponding to the total channel multiplicity,
Only by using the entire storage area, high-speed access that realizes switch multiplicity corresponding to all channel multiplicity is performed. Therefore, the communication path memory and control memory built in the time-division time switch LSI can maintain high speed corresponding to the channel multiplicity or switch multiplicity therein, which increases the area of those memories which occupy more than half of the chip area. Achieve a single chip while suppressing.

Since the speed conversion is performed for the exchange of signals between the communication path memory and the outside of the chip, the speed of the interface with the outside of the chip is lower than that of the inside, and this is because the time-division time switch LSI is mounted. Guarantees a suitable frequency for exchanging signals via wiring on the board,
Improve the usability of time-division time switch LSI. At this time, the chip area is increased to some extent due to the introduction of the speed conversion circuit, but the area occupied by the memory is doubled.
It is far less than doubling.

Regarding the need for a clock signal for operating the memory, it is possible to directly draw the high-speed clock from pin 2 only by the clock concerned, but the same low-speed signal as the high-way signal. Introducing the clock of (1) and multiplying the clock signal frequency by the built-in phase locked loop circuit further improves the usability of the time division time switch LSI.

[0022]

FIG. 1 is a block diagram of a time division speech path switch LSI according to an embodiment of the present invention.

Time division speech path switch LSI of this embodiment
Is not particularly limited, but the pass band (0.3
Up to 3.4 KHz), for example, 8 KHz is sampled and treated, and the multi-channel information is time-division multiplexed on the highway, and the time positions (time slots) are exchanged, or the same between multiple highways. It is applied to a time division switching system in which digital channels are exchanged / connected arbitrarily by spatially exchanging the channels of, and time exchange / connection is performed by exchanging highway time slots. The time-division speech path switch LSI is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS or Bi-CMOS semiconductor integrated circuit technology, for example.

In FIG. 1, HWIN0, HWIN1, H
WIN2 and HWIN3 are input highways each having eight signal lines bundled, HWOUT0, HWOUT1 and HWOUT
2, HWOUT3 is an output highway in which eight signal lines are bundled. Although not particularly limited, each highway has a channel multiplicity (the number of multiplexed channels) of 4K channels, and information of a plurality of channels is serially transmitted through each signal line by time division multiplexing. Transmission speed is 32MHz (4K x 8K
Hz). Since one channel is composed of 8 bits, eight highways are bundled. The channel multiplicity of the input highways HWIN0 to HWIN3 as a whole is 16K channels, and the output highway HWOUT0
The channel multiplicity of the entire HWOUT3 is 16K channels. In other words, the time-division speech path switch LSI of this embodiment has an input highway having a multiplicity of all channels or a switch multiplicity of 16K channels.

P0 to P3 are the input highways HWIN
0 to HWIN3 is a group of input terminals (consisting of 32 input terminals in total), P4 to P7 are output highways H
An output terminal group (composed of 32 output terminals in total) coupled to WOUT0 to HWOUT3. Input terminal group P
0 to P3 are coupled to the input terminals of the input buffer BUFin, and the output terminal groups P4 to P7 are the output buffer BUFout.
Coupled to the output terminal of.

Four serial / parallel conversion circuits S / P are provided as a first speed conversion circuit for speed-converting the information supplied from the input highways HWIN0 to HWIN3 by time division multiplexing via the input buffer BUFin to four times. And a multiplexer MUX for sequentially selecting and outputting the outputs of the respective serial / parallel conversion circuits S / P. Each highway input signal is supplied to the serial / parallel conversion circuit S / P through the input buffer BUFin, and the supplied serial array signal is converted into a parallel array signal. Then multiplexer MUX
4 input highway signals are multiplexed in
It is twice as fast. Therefore, the signal frequency here is 4
It will be twice as fast.

FIG. 2 shows the input and output of one serial / parallel conversion circuit S / P as a representative. Information of 8 bits per channel is serially transmitted to each of the 8 signal lines forming one input highway. This state is as shown in the input signal of FIG. 2, and for example, data for one channel indicated by “11” to “18” is serially supplied via one signal line. The state of serial / parallel conversion constitutes one channel, as is clear from the conversion example of data “11” to “18” for one channel.
It is performed in serial data units of bits. The clock signal F is a 32 MHz clock signal, which is the transmission frequency in each highway. The serial / parallel conversion circuit S / P is operated in synchronization with the clock signal F of 32 MHz.

FIG. 3 shows an example of the input and output of the multiplexer MUX. The output selection operation by the multiplexer MUX is the transmission frequency (32 MH) on the highway.
Clock signal 4 with a frequency (128 MHz) four times that of z)
・ Defined by F. The state of the multiplex operation is, for example, the input signal “011” for the input highway HWIN0.
~ "018", "021" ~ "028", "031"
As is apparent from the multiplex operation for "-038", the operation is performed in units of 8-bit parallel data constituting one channel and in synchronization with the cycle of the clock signal 4 · F of 128 MHz.

In FIG. 1, SPM0 and SPM1 are speech path memories (also referred to as speech path memories),
The same thing is provided on two sides. Each of the speech path memories SPM0 and SPM1 has a number of addresses (that is, the number of words as an access unit) corresponding to the channel multiplicity of the entire input highway, and is 16K words in this embodiment. The storage capacity is not particularly limited, but 16K ×
It has 9 bits. 8 bits out of 9 bits are parallel information of 1 channel 8 bits multiplexed through the multiplexer MUX, and the remaining 1 bit is a parity bit for the 8 bits. Although the parity bit addition circuit is not shown in the figure, the multiplexer MU
It should be understood that it is provided at the output of X. The parity bit is not essential.

Speech path memories SPM0, SPM1
Is not particularly limited, but clocked static RA
It is composed of M. The clocked static RAM is a synchronous static RAM in which the operation of each memory cycle is synchronized with a clock signal, and its configuration is well known, so a detailed description thereof will be omitted, but in the present embodiment, a frequency of 128 MHz is used. The access cycle is determined by the clock signal C128M. Such operating frequencies of the speech path memories SPM0, SPM1 are matched with the multiplex operating frequency of the multiplexer MUX. Clock signal C128M that determines the access cycle of the speech path memories SPM0 and SPM1
Is a clock signal C supplied to a counter CNT described later.
It is the same as 128M, and is directly supplied from the dedicated external clock input terminal (the external terminal indicated by a circle to which C128M is supplied in the drawing). Although not particularly shown,
The clock signal C128M is differentially input from the outside.

As shown in FIG. 1, a speech path memory control circuit SPMINF and a counter CN for controlling access to the speech path memories SPM0 and SPM1.
T, control memories CME and CMO, a control memory control circuit CMINF, and a microcomputer interface MCINF.

The counter CNT is a frame synchronization signal C8K (frequency 8 KHz) of information transmitted on the highway.
And the 128 MHz clock signal C128M described above are input, and the clock signal C is synchronized with the frame synchronization signal C8K.
It is a binary counter that counts changes of 128M.
The number of bits depends on the speech path memories SPM0, SPM.
It is 14 bits corresponding to the number of words of PM1 (16K). The output count value of the counter CNT is supplied to the speech path memory control circuit SPMINF and used as a write address signal for the speech path memories SPM0 and SPM1. Therefore, the data output from the multiplexer MUX is the speech path memories SPM0 and SPM1 in a regular order in which the output of the counter CNT that counts the clock signal C128M is used as a write address signal.
And a write operation is performed. In the exchange operation, the exchanged data needs to be read even during writing, so that the speech path memories are SPM0 and SP.
Two identical M1 surfaces are provided, the write targets are switched alternately, and when one is being written, the data already written to the other can be read in parallel with the write operation.
For example, when performing a write operation with SPM0, SP
The read operation can be performed by M1, and when the writing of the entire one surface is completed, SPM0 is the next read target.
SPM1 is switched to the write target. It is understood that the switching control is performed, for example, every time the speech path memory control circuit SPMINF detects the carry of the most significant bit of the counter CNT. The speech path memory control circuit SPMINF includes speech path memories SPM0 and SPM.
An address signal and a read / write signal are supplied to 1 as separate signals S0 and S1. In this case, every time the speech path memory control circuit SPMINF detects the carry of the most significant bit of the counter CNT, the instruction of the read operation and the instruction of the write operation to the speech path memories SPM0 and SPM1 are switched. In synchronization with this, a selector SEL for selecting the output data of the speech path memories SPM0 and SPM1 is provided. A control signal S2 is supplied to the selector SEL from the speech path memory control circuit SPMINF to select an output from the speech path memory on the side where the read operation is instructed. It should be understood that, in the case of the present embodiment in which the parity bit is added to the output of the speech path memory, the parity check circuit is arranged at the output end of the selector SEL, although not shown.

The control memories CME and CMO hold rewritable random read addresses of the speech path memories SPM0 and SPM1. The control memories CME and CMO are not particularly limited,
Clocked static R as well as speech path memory
The access cycle is determined by a clock signal C128M which is composed of AM and has a frequency of 128 MHz. The control memories CMO and CME are divided into CME (even-numbered plane control memory) and CMO (odd-number plane control memory). The random read address for the exchange operation is 1 when the multiplicity is 16K.
Since 6K words are enough, control memory CM
The storage capacity of each of O and CME is 8K × 18 bits. If the two surfaces are combined, it has an address of 16K words. The 18-bit information per word includes 14-bit address information for accessing the speech path memory, and the rest is parity bits or function bits or spare bits.

Control memory control circuit CMINF
Controls the writing of read address information for reading the information stored in the speech path memories SPM0 and SPM1 into the control memories CME and CMO according to an instruction from the microcomputer interface MCINF, and outputs from the counter CNT. Control memory CME, CM with count value as address
The information read from O is supplied to the speech path memory control circuit SPMINF as a read address of the speech path memory. The output of the counter CNT is used as the read address for the control memories CMO and CME, and the read address is not particularly limited.
The NF alternately controls the read target between the control memories CME and CMO each time the logical value of the 14th bit of the 14-bit counter output is changed.

Microcomputer interface MC
The INF is connected to a microcomputer (not shown),
Address information of the speech path memory as data DATA, that is, information for channel exchange (exchange channel information)
Etc. is supplied, and it is supplied to the control memory C
An address ADDR for writing to MO and CME, a read / write control signal R / W to control memories CMO and CME, and various strobe signals STB-n such as chip selection and data strobe are given. The control memory control circuit CMINF to which they are supplied is
In parallel with read control for one of the divided control memories CME and CMO, the other is controlled to be write accessible. That is, the control memory control circuit C
MINF is a microcomputer interface MC
The write operation is allowed when the control memory of the address ADDR supplied via the ITF is not in the read operation. In this way, the exchange channel information given by the microcomputer (not shown) is written in the control memories CME and CMO. In that state, the control memories CMO and CME always regularly counter CN.
The read signal is alternately read by the address signal of T, and the random exchange channel information is transmitted to the speech path memory SPM0,
It continues to be given as the read address signal of SPM1.

The information read from the speech path memories SPM0 and SPM1 according to the random exchange channel information and selected by the selector SEL is the demultiplexer DMU.
Supplied to X. The demultiplexer DMUX performs the reverse operation of the multiplexer MUX, and distributes a 1-channel 8-bit parallel signal to four parallel signal groups in the same unit. The distributed 1-channel 8-bit parallel signals are respectively supplied to the parallel / serial conversion circuit P / S, and in contrast to the serial / parallel conversion circuit S / P, the 1-channel 8-bit parallel signals are converted into a serial array. It is distributed and supplied to any of the eight signal lines. Parallel / serial conversion circuit P /
The data serially converted by S passes through the output buffer BUFout via each of the eight signal lines and is output to the output highway HW.
It is supplied to OUT0 to HWOUT3. The demultiplexer DMUX and the parallel / serial conversion circuit R / S constitute a second speed conversion circuit for speed-converting the information read from the speech path memories SPM0 and SPM1 to 1/4. The information stored in the speech path memory by multiplexing the signals of the four input highways is supplied to the output highways in that it is distributed to four parallel signal groups corresponding to the four output highways HWOUT0 to HWOUT3. Signal frequency is 128MHz to 32MH
will be returned to z. The selector SEL and the demultiplexer DMUX are 128 MHz clock signals 4
・ Synchronous operation to F, 32 parallel / serial conversion circuit P / S
It is operated in synchronization with the clock signal F of MHz.

The clock signal 4.F is the same as the clock signal C128M, and the clock signal F is understood to be a clock signal obtained by dividing the clock signal C128M by four. Circuits that receive them S / P, MUX, SEL,
The operation of DMUX and P / S is speech path memory SPM.
The speech path memory control circuit SPMINF controls the read / write operations for 0 and SPM2. RST is a reset signal for the time division time switch LSI.

FIG. 4 shows a block diagram of another embodiment of the present invention. In the embodiment shown in FIG. 1, the speech path memory SPM is used.
0, SPM1 and the control memory CM0, CM1 receives a clock signal C128M of 128 MHz which defines the same speed as the operating speed directly, but in the present embodiment, a clock signal C32M of 32 MHz which is the same as the signal speed of the highway is externally received. , And a phase-locked loop (Phase Lock) that multiplies this by four times.
The difference is that an ed loop circuit PLL is provided and its output is used. Other configurations are the same as those in FIG. 1, and thus detailed description thereof will be omitted.

According to the above embodiment, the following operational effects are obtained. Serial / parallel conversion circuit S / P and multiplexer MU
The first speed conversion circuit composed of X forms an 8-bit parallel signal in which the information transmitted from each of the four input highways at a speed of 32 MHz is multiplexed on the output side for four highways, and the signal frequency at that portion is set. 4 times faster to 128 MHz, and the second speed conversion circuit composed of the demultiplexer DMUX and the parallel / serial conversion circuit P / S performs an operation reverse to that of the first speed conversion circuit, and finally becomes 4 An 8-bit serial signal is distributed at a rate of 32 MHz to each of the output highways of the book. In other words, speech path memory SPM
0, SPM1 and control memory CME, CMO are 4
It has an address (16K words) according to the total channel multiplicity (16K channels) of the input highway of the book, and responds to the total channel multiplicity with an operating speed of 128 MHz that does not cause an empty cycle for it. A switch multiplicity (16K channels) is realized. Speech path memory SPM0, SPM1 and control memory C
The ME and CMO do not require a storage area having a storage capacity larger than the storage capacity corresponding to the total channel multiplicity, and perform high-speed access that realizes switch multiplicity corresponding to the total channel multiplicity only by using the entire storage area. You can

Therefore, the speech path memories SPM0 and SPM1 built in the time division time switch LSI of this embodiment.
The control memories CME and CMO can maintain high speed corresponding to the channel multiplicity or the switch multiplicity. This suppresses an increase in the area of those memories that occupy more than half of the chip area, and realizes one chip.

Since the speed conversion is performed for the exchange of signals between the speech path memories SPM0 and SPM1 and the outside of the chip, the speed of the interface with the outside of the chip is lower than that of the inside, which is a time division time switch LSI.
(EN) A frequency suitable for exchanging signals via wiring on a mounting board on which is mounted is improved, and usability of a time-division time switch LSI is improved. At this time, the chip area is increased to some extent due to the introduction of the speed conversion circuit, but the area occupied by the memory is much smaller than the area occupied by the memory.

By introducing the same low-speed clock as the highway signal and multiplying the clock signal frequency by the built-in phase locked loop circuit PLL, the usability of the time division time switch LSI can be further improved.
By adopting the phase-locked loop circuit PLL, the interface speeds of the LSIs for both data and clock signals can all be the same speed such as 32 MHz, which is advantageous in that it is easier to use.

As is clear from the above, the speech path memories SPM0, SPM1 and the control memory CM are shown.
E, CMO is the highest frequency of the system 128MHz
It is possible to operate in a high-speed time-division time switch LSI with a multiplicity of 16 K channels or more, since the interface with the highway can be connected with a signal having a frequency such as 32 MHz, which is several times slower than that. Also, the interface speed can be kept below a certain value, and an easy-to-use LSI can be provided.

A pair of speech path memories SPM0, SP
By providing a pair of M1s and providing a speech path memory control circuit SPMINF for controlling the other speech path memory for reading while writing to one speech path memory mutually, writing to the speech path memory is performed without interruption. In consideration of this, reading in parallel with this can be realized relatively easily.

Based on the output of the counter CNT which performs the counting operation at a speed synchronized with the memory cycles of the speech path memories SPM0 and SPM1, the write address for the speech path memories and the operation switching control signals (S0, S1) for the pair of speech path memories are provided. By adopting the speech path memory control circuit SPMINF which generates a), it is possible to relatively easily perform the operation switching for the pair of speech path memories.

A control memory CME having a number of addresses corresponding to all channel multiplicity and being read / written in the same memory cycle as the speech path memory,
A CMO is provided, the read address information of the speech path memory is externally controlled to be written in the control memories CME, CMO, and the count value output from the counter CNT is used as an address in the control memories CME, C.
By adopting the control memory control circuit CMINF which uses the information read from the MO as the read address of the speech path memory, random reading from the speech path memory can be easily realized.

Control memory CM divided into two planes
By adopting E and CMO and making read access to one of the divided control memories in parallel and making the other write accessible, the operation of writing a random read address for the speech path memory into the control memory becomes the read operation. Can be done in parallel.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes. For example, the number of connected highways, the speed conversion ratio, the operating frequency of the communication channel memory, the switch multiplicity to be achieved by one chip, etc. are not limited to the above-described embodiment, and can be appropriately determined. Further, the communication path memory and the control memory are not limited to the configuration having two surfaces as in the above embodiment. Generation of a random read address for the communication channel memory is not limited to that using the control memory, and it may be configured using a logic circuit or may directly receive a random read address from the outside. Further, the time division time switch LSI according to the present invention may be formed on the same chip together with other circuits, for example, a microcomputer.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the communication path memory and the control memory built in the time division time switch LSI can maintain high speed corresponding to the channel multiplicity or the switch multiplicity therein, and these memories occupy more than half of the chip area. An increase in area can be suppressed and a single chip can be realized. Since the speed conversion is performed for the exchange of signals between the channel memory and the outside of the chip, the speed of the interface with the outside of the chip is lower than that of the inside,
As a result, a frequency suitable for exchanging signals via the wiring on the mounting board on which the time division time switch LSI is mounted can be guaranteed, and the usability of the time division time switch LSI is improved. Therefore, it is possible to operate at the maximum speed of the communication path memory and the control memory while keeping the signal interface speed of the LSI at a practically easy-to-use speed, and suppress the increase in the area of these memories, which occupies more than half of the chip area. This makes it possible to realize a large-capacity time-division time switch LSI on a single chip, which is economically effective.

By installing a phase-locked loop circuit in the external clock receiving system so that a high-speed clock internally multiplied with respect to the external clock can be obtained,
The interface speed as SI can be unified, and the usability of the time division time switch LSI can be further improved.

With the above effects, a large-capacity time division time switch having a switch multiplicity of 16 K channels or more can be realized in an easy-to-use form, so that it is possible to realize a time division exchange system which is both easy to realize and economical. it can.

[Brief description of drawings]

FIG. 1 is a block diagram of a time division speech path switch LSI according to an embodiment of the present invention.

FIG. 2 is a time chart showing an input and an output of one serial / parallel conversion circuit.

FIG. 3 is a time chart showing an example of inputs and outputs of a multiplexer.

FIG. 4 is a block diagram of a time division speech path switch LSI according to another embodiment of the present invention using a phase locked loop circuit.

[Explanation of symbols]

 HWIN0-WIN3 Input highway HWOUT0-HWOUT3 Output highway S / P serial / parallel conversion circuit MUX multiplexer SPM0, SPM1 speech path memory SEL selector DMUX demultiplexer P / S parallel / serial conversion SPMINF speech path memory control circuit CMINF control memory control circuit MCINF Microcomputer interface CNT counter CME even-sided control memory CMO odd-sided control memory C128M 128MHz clock signal C8K frame synchronization clock signal C32M 32MHz system clock signal PLL phase-locked loop circuit

Front page continuation (72) Inventor Yoichi Sato 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Yasuo Mikami Totsuka, Yokohama, Kanagawa Prefecture 216 Totsuka-cho, Tokyo Incorporated company Hitachi, Ltd. Information and Communication Division (72) Inventor Satoshi Shinagawa 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd.

Claims (10)

[Claims] 1. A single chip capable of connecting n highways each having a multiplicity of m channels, and capable of exchanging channel positions of information input from the highways by time division multiplexing and outputting the information to a plurality of highways. And a first speed conversion circuit for speed-converting information supplied from each of the plurality of highways by n times, and a total channel multiplicity m × n of the n highways. And a speech path memory for storing the information output from the first speed conversion circuit in a readable / writable manner in a memory cycle of a speed synchronized with the speed, and from the speech path memory. 1 for the information read in a predetermined order
And a second speed conversion circuit for converting the speed to / n times and supplying it to n highways. 2. A speech path memory control circuit comprising a pair of said speech path memories, and controlling the other speech path memory for reading while writing to one speech path memory with each other. The time division time switch LSI according to claim 1, characterized in that 3. A counter for performing a counting operation at a speed synchronized with a memory cycle of the speech channel memory, wherein the speech channel memory control circuit inputs a count value output from the counter to the speech channel memory. 3. The time-division time switch LSI according to claim 2, which generates a write address and an operation switching control signal for a pair of speech path memories. 4. A control memory, which has a number of addresses corresponding to said all-channel multiplicity m × n and is read / written in the same memory cycle as said speech channel memory, and stored in said speech channel memory. The read address for reading the information is controlled to be written in the control memory according to the instruction from the microcomputer interface, and the information read from the control memory is the read address of the communication channel memory using the count value output from the counter as an address. 4. The time-division time switch LSI according to claim 3, further comprising a control memory control circuit. 5. The control memory is divided into two,
5. The control memory control circuit according to an instruction from a microcomputer interface, which enables write access to one of the divided control memories in parallel with read control of the other control memory. Divided time switch LSI. 6. A phase-locked loop circuit for externally receiving a clock signal having a frequency defining the same speed as the information transmission speed on the highway and generating a clock signal having a frequency defining the memory cycle of the communication channel memory. The time division time switch LS according to any one of claims 1 to 5, wherein the time division time switch LS is provided.
I. 7. A clock signal input terminal for directly receiving a clock signal of a frequency defining a memory cycle of the speech path memory from outside the LSI, as claimed in any one of claims 1 to 5. A time-division time switch LSI described in the item. 8. The channel memory has a multiplicity of all channels m.
8. The time-division time switch LSI according to claim 1, wherein xn has a storage capacity corresponding to 16K channels or more. 9. An input terminal and an output terminal are connected to a plurality of highways of a parallel number n, in which information of a plurality of channels sampled at a predetermined frequency f is transmitted by time division multiplexing with multiplicity m of each channel. A time-division time switch LSI, which is made into one chip and is capable of being combined, and is capable of exchanging positions of information supplied by time-division multiplexing from the plurality of highways and outputting the information to a plurality of highways. Highway multi-channel multiplicity m
The number of addresses corresponding to × n is provided, and m × n × f
And a first speed conversion for converting the information supplied from each of the plurality of highways into n times the speed and supplying the same to the communication path memory. The circuit and the information read from the above-mentioned speech path memory in a predetermined order
A second speed conversion circuit for converting the speed to / n times and supplying it to a plurality of highways of parallel number n, and a counter for performing a counting operation at a speed determined by the above m × n × f. A channel memory control circuit for inputting a count value to generate a write address for the channel memory, and a number of addresses corresponding to the total channel multiplicity m × n, and determined by m × n × f A control memory which is read / write operated in a speed memory cycle, and read address information for reading the information stored in the communication channel memory is controlled to be written in the control memory according to an instruction from the outside, and the counter is operated from the counter. The information read from the control memory with the output count value as the address is used as the read address of the communication path memory. Time division switching LSI when, characterized in that comprising comprises a control memory control circuit that, the. 10. A pair of said speech path memories, wherein said speech path memory control circuit counters a switching control signal for controlling the other speech path memory for reading while writing to one speech path memory mutually. The control memory is divided into two, and the control memory control circuit can write access to one of the divided control memories in parallel with the read control of one of the divided control memories according to an instruction from the outside. 10. The time divisional time switch LSI according to claim 9, characterized in that