JPH07336556A - Pll circuit - Google Patents

Abstract

PURPOSE:To generate a stable system clock signal by selecting a voltage controlled oscillator VCO automatically generating an oscillated frequency signal optimum to a video signal received based on result of 1, 4, 16 field discrimination. CONSTITUTION:A 1-field discrimination means 10 receives a skew detection signal from a skew detection means 7, a V system signal from a V system signal generating means 9, and a system clock signal from a VCO changeover means 5 and generates a direction discrimination signal representing the direction of skew and a 1-field discrimination signal representing the number of skews. A 4-field discrimination means 11 provides the output of a 4-field discrimination signal based on the direction of skew and the number of skews for a 4-field period. A 16-field discrimination means 12 receives the 4-field discrimination signal from the means 11 and the V system signal from the means 9 to generate a direction discrimination signal representing the direction of skew received for a 16-field period. A VCO changeover control section 13 controls the means 5 based on the discrimination signal of each field discrimination means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing technique for converting a video signal into a digital signal and processing the digital signal, and more particularly to an additional circuit of a PLL circuit for stabilizing a system clock.

[0002]

2. Description of the Related Art Conventionally, a PLL circuit used in a television generates a system clock signal which is synchronized with a horizontal synchronizing signal. Therefore, as shown in FIG.
, Phase comparison circuit 2, low-pass filter unit 3, VC
A horizontal synchronization signal (H) is obtained by dividing a system clock (CKs) signal oscillated by the VCO by dividing the frequency-divided signal (Hck / n), which is composed of O4, the frequency dividing circuit 5, and the skew detecting means 6.
sync), so that it is in phase with, for example, VTR
The skew of the video signal including the skew generated when the head is switched like the video signal is detected, the frequency divider circuit is reset by the detected signal, and the phase comparison is not performed in the horizontal sync signal portion where the skew is generated. The system clock is controlled so that the cycle of the system clock is not disturbed. However, there are video signals having different horizontal frequencies such as NTSC and PAL, and in order to cope with them, a plurality of VCOs are prepared and the VCO suitable for the input video signal is selected. I need to switch.

[0003]

In order to meet the above-mentioned need, the present invention prepares a plurality of VCOs and automatically selects and switches the VCO suitable for an input video signal.
The purpose is to provide an LL circuit.

[0004]

In order to solve the above problems, the present invention separates a horizontal sync separation circuit for separating a horizontal sync signal from an input video signal and a horizontal sync signal (Hsync) of the sync separation circuit. Frequency division signal (Hcks /
n) a plurality of phase comparison circuits that compare the phases, a plurality of low-pass filters that output the low-frequency components of the output signal Scomp) from the phase comparison circuits, and a system clock pulse based on the output voltage (Vlf) of the low-pass filters. (CK
and a plurality of voltage controlled oscillators (hereinafter referred to as VCOs) that generate s) and a VCO that switches and outputs the plurality of VCOs.
Switching means, a frequency dividing circuit for dividing the output from the VCO switching means and resetting with a signal (Ssc) from the skew detecting means, and a skew detecting means for detecting the disturbance of the cycle of the horizontal synchronizing signal. , Inputting the output of the skew detecting means, monitoring the occurrence state of the skew for one field period and determining whether to switch the plurality of VCOs, and inputting the output of the skew detecting means A four-field determination means for monitoring the occurrence state of the skew during the four-field period and determining whether or not to switch the plurality of VCOs, and an output of the four-field determination means are input, and the skew occurrence state for the sixteen-field period is input. 16 field determination means for monitoring whether or not to switch the plurality of VCOs, and the 1 field determination means, 4 field determination means. Based on the signals from the field determination means and the 16-field determination means, a VCO switching control section for switching and controlling the VCO switching means, a vertical synchronization separation circuit for separating a vertical synchronization signal from an input video signal, and the vertical synchronization signal. And V-system signal generating means for generating various field signals to be input to each of the field determining means from a horizontal synchronizing signal and the like.

[0005]

With the above-described structure, the PLL circuit of the present invention generates the optimum oscillation frequency for the input video signal based on the 1-field determination result, 4-field determination result, and 16-field determination result. The VCO to be activated is automatically selected and switched.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of a PLL circuit according to the present invention. In the figure, 1
Is a horizontal sync separation circuit that separates a horizontal sync (Hsync) signal from an input video signal. Reference numerals 2a and 2b denote phase comparison circuits for comparing the phases of the horizontal synchronizing signal (Hsync) and the frequency-divided signal (Hcks / n) from the frequency dividing circuit 6 described later. Reference numerals 3a and 3b denote low-pass filter units that cut off high-frequency components of the comparison signal (Scmp) from the phase comparison circuit 2. Reference numerals 4a and 4b denote voltage controlled oscillators (VCOA, VCOB), which correspond to the output voltage (Vlf) from the low pass filter 3 and which are VCOA4.
a is a system clock (CKs with a lower oscillation frequency
1) is generated, and the VCOB 4b is generating the system clock (CKs2) signal having a higher oscillation frequency. Reference numeral 5 is a VCO switching means, which is controlled by a VCO switching control unit 13 which will be described later to control VCOA 4a and VCOB 4b.
To output the system clock (CKs) signal. A frequency dividing circuit 6 divides the system clock (CKs) signal from the VCO switching means 5 into 1 / n. Reference numeral 7 denotes a skew detecting means, which is a horizontal sync (Hsync) from the horizontal sync separation circuit 1 with reference to the system clock (CKs) signal from the VCO switching means 5.
The skew (discontinuity signal) of the signal is detected, and the skew detection (Ssc) signal is output. Reference numeral 8 denotes a vertical sync separation circuit, which is a vertical sync signal (Vsync
c) is separated. Reference numeral 9 denotes a V system signal generating means, which is the vertical synchronization (Vsync) signal and the horizontal synchronization signal (Hsync).
From c) and the like, signals necessary for the field determining means and the like described later are generated.

Reference numeral 10 is a one-field determination means, which is a skew detection (Ssc) signal from the skew detection means 7 and V.
V system (Su / d, Svgp) signal from the system signal generating means 9 and system clock (C from the VCO switching means 5)
Ks) signal is input and a direction determination (Sup, Sdwn) signal indicating the direction of skew input in one field period and 1 indicating the number of skews input in one field period are input.
The field determination (S1f) signal is generated. Reference numeral 11 denotes a 4-field determination means, which inputs a skew detection (Ssc) signal, a V system (Svgp, Su / d, Sf4) signal, and a system clock (CKs) signal, and determines the direction and number of skews during a 4-field period. 4 field determination (Su
ps, Sdwns) signal is output. Reference numeral 12 denotes a 16-field determination means, which inputs the 4-field determination (Sups, Sdwns) signal from the 4-field determination means 11 and the V-system (Sf4, Sf16) signal from the V-system signal generation means 9 for a 16-field period. A direction determination (Sup, Sdwn) signal indicating the direction of the skew to be input to is generated. Reference numeral 13 denotes a VCO switching control unit, which is based on the determination signal output from each of the field determination means.
Control signals (Supc, Sdw) for controlling the switching means 5
nc) signal is being output.

FIG. 2 is a circuit block diagram showing an embodiment of the skew detecting means 7. In the figure, 71 is H
An AND circuit 71a, a 10-bit counter 61b that counts the system clock (CKs) signal, an 8-value decoding circuit 71c, and 79 by a gate pulse generating means.
One-value decoding circuit 71d and JK flip-flop 71
and an H gate pulse (Shgp) signal and an H gate pulse edge (Shge) signal (in this embodiment, an 8-level decode (Sd8) signal) for extracting a horizontal synchronization (Hsync) signal by a predetermined width. In addition, the direction of skew is detected from the MSB signal of the 10-bit counter 61b (S
u / d) signal is output. Reference numeral 72 denotes a gate means, which is composed of a D flip-flop, extracts a horizontal synchronization (Hsync) signal by the H gate pulse (Shgp) signal from the gate pulse generation means 71, and outputs a gate (Shs).
g) Outputting a signal. Reference numeral 73 denotes a skew pulse generating means, which is ANDed with two D flip-flops 73a and 73b.
It is composed of a circuit 73c and a NAND circuit 73d, and an H gate pulse edge (Shge) signal from the H gate pulse generating means 71 and a gate (Sh from the gate means 72).
The sg) signal and the system clock (CKs) signal are input to generate the skew detection (Ssc) signal.

FIG. 3 is a circuit block diagram showing an embodiment of the one-field determination means 10. In the figure, reference numeral 101 denotes a first OR circuit, which takes out a skew detection (Ssc) signal generated during a period excluding the Vgate pulse (Svgp). Reference numeral 102 denotes a NOA circuit, which inputs a signal from the first OR circuit 101 and a 1-field determination (S1f) signal from a second OR circuit described later to perform NOR gate. Reference numeral 103 is a 5-bit up / down counter, which counts up or down from the initial value 8 to count both the skew in the up direction and the skew in the down direction in one field period. 104 is a 15-value decoding circuit,
The 15 values of the output signal of the counter 103 are decoded and an up direction determination (Sup) signal is output. 105
Is a one-value decoding circuit, which decodes one value of the output signal of the counter 103 and outputs a down direction determination (Sdwn) signal. Reference numeral 106 denotes a second OR circuit, which ORs the output signals of the decoding circuits 104 and 105 to obtain 1
The field determination (S1f) signal is output.

FIG. 4 is a circuit block diagram showing an embodiment of the 4-field judging means 11. In the figure, reference numeral 111 denotes a first OR circuit, which takes out a skew detection (Ssc) signal generated during a period excluding the Vgate pulse (Svgp). Reference numeral 112 is a second OR circuit, which is the first OR circuit.
It takes the OR of the signal from the circuit 111 and the Q output of the D flip-flop circuit 113 described later. Reference numeral 113 denotes a D flip-flop circuit, which is the MSB signal (Su / d) signal of the counter forming the frequency dividing circuit 6 and the second OR.
The signal from the circuit 112, the system clock (CKs) signal, and the pulse (Sf4) for every four fields are input and Q is input.
From the output, a skew detection (S'ups) signal in the up direction for four field periods is generated and output. Reference numeral 114 denotes a first AND circuit, which is the D flip-flop circuit 11
The skew detection (S'ups) signal in the up direction from the Q output of 3 and the Q'output signal of the D flip-flop circuit 116, which will be described later, are ANDed to obtain the skew determination (Sups) signal in the up direction. It is outputting.
Reference numeral 115 denotes a third OR circuit, which is the first OR circuit 111.
Signal and Q of the D flip-flop circuit 116 described later.
It is taking output and or. Reference numeral 116 is a D flip-flop circuit, which is the MSB signal (Su / d) signal of the counter forming the frequency dividing circuit 6 and the third OR circuit 115.
Signal and system clock (CKs) signal and a pulse (Sf4) for every 4 fields are input and 4 from the Q output.
Skew detection in the down direction in the field period (S'dw
ns) signal is generated and output. 117 is the second A
In the ND circuit, the skew detection (S'dwns) signal in the down direction for four field periods from the Q output of the D flip-flop circuit 116 and the Q'output signal of the D flip-flop circuit 113 are ANDed to determine the down direction. The skew determination (Sdwns) signal is output.

FIG. 5 is a block diagram showing an embodiment of the 16-field determination means 12. In the figure, 121 is O
The R circuit takes the OR of the up-direction skew determination (Sups) signal and the down-direction skew determination (Sdwns) signal from the 4-field determination means 11. 122
Is a 3-bit up / down counter, and is the OR circuit 12
1 signal, (Sups) signal, (Sf4) signal, and (Sf16) signal are input, and up or down count is performed from the initial value of 4 to count both the skew in the up direction and the skew in the down direction for 16 field periods. ing. Reference numeral 123 is a seven-value decoding circuit, which is the counter 122.
Output signal is decoded to determine 7 value up direction (Su
p) It outputs as a signal. Reference numeral 124 is a one-value decoding circuit, which decodes the output signal of the counter 122 to 1
The value is output as a down direction determination (Sdwn) signal.

FIG. 6 is a block diagram showing an embodiment of the Vgate pulse generating means 91. In the figure, 911 is a 9-bit counter which counts the horizontal synchronizing signal (Hsync) in one field period. A 17-value decoding circuit 912 decodes the output signal of the 9-bit counter 911 and outputs a 17-value. 913 is 24
A ternary decoding circuit decodes the output signal of the 9-bit counter 911 and outputs 243 values. 914
Is a JK flip-flop circuit, which toggles at the timing of the system clock (CKs) according to the output signal of the decoding circuit and Vgate pulse (Svgp) from the Q output.
, And a Vgate pulse (S'vgp) is output from the Q'output.

FIG. 7 shows field clear signal generating means 92.
It is a block diagram which shows one Example. In the figure, 92
Reference numeral 1 denotes a 4-field pulse generator, which is composed of two T flip-flop circuits 921a and 921b and an AND circuit 921c, receives the Vgate pulse (S'vgp), and has a field width of 4 fields (Sf).
4) is generated. Reference numeral 922 denotes a first AND circuit, which inputs a signal obtained by inverting the signal from the 4-field pulse generation unit 921 and a vertical synchronization (Vsync) signal through an inverter 926a, takes an AND, and outputs a 4-field pulse (Sfp4) signal. is doing. 923 is a NAND
In the circuit, the signal from the 4-field pulse generator 921 and the Vgate pulse (S′vgp) are fed to the inverter 92.
The inverted signal is input through 6b to take a NAND. Numeral 924 is a 16-filled pulse generator, and two T flip-flop circuits 924a and 924b and an AND circuit 9
24c, the 4-field signal from the NAND circuit 923 is input to generate a pulse (Sf16) having a 4-field width in 16 filled cycles. Numeral 925 denotes a second AND circuit, which inputs the 4-field pulse (Sfp4) signal from the first AND circuit 922 and the 16-field pulse from the 16-field pulse generator 924, takes the AND, and outputs the 16-field pulse. (Sfp1
6) The signal is being output.

FIG. 8 is a block diagram showing an embodiment of the VCO switching controller and VCO switching means. In the figure, reference numeral 131 denotes a first AND circuit, which includes a down direction skew detection (Sdwn) signal output from the 1-field determination means 10 and the 16-field determination means 12 and a T described later.
The AND is taken with the Q output signal of the flip-flop circuit 134. Reference numeral 132 denotes a second AND circuit, which takes a down direction determination (Sup) signal output from the 1-field determination means 10 and the 16-field determination means 12 and a Q'output signal of a T flip-flop circuit 134 described later, and. . 133 is a first OR circuit,
It takes the OR of the output signal of the circuit. Reference numeral 134 denotes a T flip-flop circuit, which receives the signal from the OR circuit 133 and
1-field determination by the 1-field determination means 10 (S
1f) signal is input and down control is performed from the Q output (Sdwn
The c) signal and the up control (Supc) signal are output from the Q'output. Reference numeral 51 is a third AND circuit, which gates the system clock (CKs1) signal from the VCOA 4a by the down control (Sdwnc) signal. Reference numeral 52 denotes a fourth AND circuit, which is the VCOB4b.
The system clock (CKs2) signal is gated by the up control (Supc) signal. Reference numeral 53 is a second OR circuit, which includes the third AND circuit and the fourth A circuit.
The signal from the ND circuit is ORed and output.

The operation of the above arrangement will be described below. As a normal operation of the PLL circuit, the horizontal synchronization (Hsync) signal separated from the input video signal and the system clock signal (CKs) are divided into 1 / n (H
ckc / n) signal is compared with the phase, and the error voltage (Vlf) obtained by removing the high frequency component of the error signal is used for VCO4.
Are controlled so that the phases of the horizontal synchronization (Hsync) signal and the system clock (CKs) signal match. When a skew occurs in the horizontal synchronization (Hsync) signal, the skew detection means 7 outputs a skew detection (Ssc) signal. The skew detection (Ssc) signal is controlled by resetting the frequency dividing circuit 6 so that phase comparison is not performed in the horizontal synchronizing signal portion in which the skew is generated so that the cycle of the system clock is not disturbed. . Also, 1
The field determination means 10 inputs the skew detection (Ssc) signal from the skew detection means 7 and determines that a predetermined number (7 in this embodiment) or more skews in the same direction are detected within one field period. As an output, an up direction determination (Sup) signal or a down direction determination (Sdwn) signal is output. The 4-field determination means 11 inputs the skew detection (Ssc) signal from the skew detection means 7, detects the change in the skew direction within the 4-field period, and inputs the determination result to the 16-field determination means 12. There is. In the 16-field determination means 12, the 4
If the same determination result of the field determination means 11 is a predetermined number of times (4 times in this embodiment) in the 16-field period, the up direction determination (Sup) signal or the down direction determination (Sup) signal for switching to the direction to be detected. Sdwn) signal is being output. In the VCO switching control unit, the above 1
Up control (Sup) based on the up direction determination (Sup) or down direction determination (Sdwn) signal from the field determination unit 10 or 16 field determination unit 12.
c) signal or a down control (Sdwnc) signal is generated and the VCO switching means 5 is controlled to switch to the VCOA 4a or VCOB 4b.

The operation of the block diagram of FIG. 1 has been described above. Next, the operation of each means of the present invention will be described. First, the operation of the skew detecting means 7 will be described with reference to the timing chart shown in FIG. 10-bit counter 61
b counts the system clock (CKs) signal,
An 8-level decode (Sd8) signal is generated from the value decode circuit 71c, and the (Sd8) signal and the 791-value decode circuit 7 are generated.
H from the 791-value decode (Sd791) signal from 1d
A gate pulse (Shgp) is generated. In the gate circuit 72, the horizontal synchronization (Hsync) signal is extracted by the H gate pulse (Shgp) and gated (Shsg).
Generating a signal. Now, assuming that the interval between H3 and H4 of the horizontal synchronization (Hsync) signal becomes wide, the gate (S
As shown in the figure, the hsg) signal is a horizontal synchronization (Hsyn) signal.
H4 and H5 in c) cannot be extracted by the H gate pulse (Shgp) and remain at H level. In the D flip-flop circuit 73a of the skew pulse generating means 73, when the 8-level decode (Sd8) signal is at the H level, the gate (Shsg) signal is latched at the rising timing of the system clock (CKs) signal and the D output is latched by the Q output. (S
d1) The signal is output. Further, in the D flip-flop circuit 73b, when the 8-level decode (Sd8) signal is at the H level, the D latch (Sd1) signal is latched at the rising timing of the system clock (CKs) signal and Q
A D latch (Sd2) signal is output from the output. AN
The D circuit 73c AND gates the D latch (Sd1) signal and the D latch (Sd2) signal, and NAND gates the gate signal and the horizontal synchronization (Hsync) signal with the NAND circuit 73d to obtain the horizontal synchronization (Hsync) signal H5. Is extracted and used as a skew detection (Ssc) signal.

Next, the operation of the 1-field determination means 10 will be described with reference to the timing chart shown in FIG. In the first OR circuit 101, the Vgate pulse (Svgp) corresponding to the head switching period of the VTR is calculated from the skew detection (Ssc) signal generated by the skew detection means 7.
The signal period is removed. The Vgate pulse (S
vgp) Skew detection (Ss) that occurs outside the signal period
The c) signal is input to the CKEN terminal of the 5-bit up / down counter 103 through the NOR circuit 102, and the skew direction determination (Su / d) signal which is the MSB signal of the 10-bit counter 71b is input to the U / D switching terminal. , Counting up or down from the initial value 8. Now, as shown in FIG. 10, skew detection (Ssc)
Signal is (Su / d) = 0, that is, horizontal synchronization (Hsync)
When the period of the signal is longer than the H gate pulse (Shgp) signal, the 5-bit up / down counter 103 counts down from the initial value 8 and the 7-pulse up-direction skew detection (Ssc) signal is input during one filled period. Then, the output of the 5-bit up / down counter 103 is 1
Becomes a value, and the down direction judgment (Sd
wn) signal is being output. Further, when the 7-pulse down-direction skew detection (Ssc) signal is input during one filled period, the output of the 5-bit up / down counter 103 becomes 15 values, and the 15-value decoding circuit outputs the up-direction determination (Sup) signal. Is output. When the (Sdwn) signal or the (Sup) signal is input from the second OR circuit, the 1-field determination (S1f) signal is output. The up / down counter 103 is initialized by a vertical synchronization (Vsync) signal.

Next, the operation of the 4-field judging means 11 will be described with reference to the timing chart shown in FIG. Also in this case, as in the case of the 1-field determination means 10, the first OR circuit 111 removes the Vgate pulse (Svgp) signal period corresponding to the head switching period of the VTR from the skew detection (Ssc) signal generated by the skew detection means 7. There is. The D flip-flop 113 detects that at least one skew detection (Ssc) signal in the up direction, which is detected during periods other than the Vgate pulse (Svgp) signal period, is input during the 4-field period, and the D flip-flop 116 detects the 4-field period. It is detected that at least one down-direction skew detection (Ssc) signal to be detected is input during the Vgate pulse (Svgp) signal period. Now, when only the skew detection (Ssc) signal in the up direction is detected during the 4-field determination period, as shown in FIG. 11A, the first AND circuit 114 outputs H during the determination period after the detection. Level (S
The second AND circuit 117 outputs the L level (SdwnsL) signal from the second AND circuit 117.
In addition, when a skew detection (Ssc) signal in the up direction and the down direction is detected during the 4-field determination period, FIG.
As shown in 1-b, from the first AND circuit 114, the H level (SupsH / L) signal is output from the second AND circuit 1 until the up direction is detected and the down direction is detected.
After detecting the down direction from 17, the H level (SdwnsH) signal is output during the determination period.

Next, the operation of the 16-field determination means 12 will be described with reference to the timing chart shown in FIG. In the 16-field determination means 12, the up-direction skew determination (Sups) from the 4-field determination means 11 is performed.
Signal or down direction skew determination (Sdwns) signal is detected by the 7-value decoding circuit as an up-direction determination (Sup) signal or 1-value decoding circuit The direction determination (Sdwn) signal is output. When the detection is not performed three times or more in the same direction in the 12-field period, the up-direction determination (Sup) signal or 1 from the 7-value decoding circuit is used as the switching signal to the direction in which the detection is performed when the same direction is detected three or more times in the 16-field period. The value decoding circuit outputs a down direction determination (Sdwn) signal. The (Sups) signal shown in FIG. 12 shows an example in which the up direction is detected three times in the 12 field period, and the (Sups) signal shows an example in which the up direction is detected three times in the 16 field period.

Next, the operation of the V system signal generating means 9 will be described. 13 is a timing chart for explaining the operation of the Vgate pulse generating means 91, and FIG. 14 is a timing chart for explaining the operation of the field clear signal generating means 92. As shown in FIG. 13, the Vgate pulse generating means 91 generates a pulse having a width of ± 16H from the leading edge of the vertical synchronization (Vsync) signal, and Vgate is generated.
As the pulse, (S'vgp) is output from the (Svgp) Q 'output from the Q output of the JK flip-flop 914. In the field clear signal generating means 92, as shown in FIG.
As shown in, the Vgate pulse (S'vgp) from the Vgate pulse generating means 91 and the vertical synchronization (Vsy)
signal of 1 field width and 4 field cycle (Sf4) signal, 4 field cycle (Sf4) signal of the same width as the vertical synchronization (Vsync) signal, and 16 field cycle (Sf16) signal of 4 field width. And a (Sfp16) signal having the same width as the vertical synchronization (Vsync) signal and 16 field cycles.

Next, the VCO switching control unit 13 and the VC
The operation of the O switching means 5 will be described. In the VCO switching control unit 13, the up direction determination (Sup) from the 1-field determination unit and the 16-field determination unit 12 is performed.
Signal and the down direction determination (Sdwn) signal and the 1-field determination (S1f) signal, for example, when the down direction determination (Sdwn) signal is input, for switching from the Q output of the T flip-flop circuit 134. The down control (Sdwnc) signal is set to the H level, and the up control (Sup) from the Q'output of the T flip-flop circuit 134 is performed.
c) The signal is set to L level and input to the VCO switching means 5, and the VCO switching means 5 passes the system clock (CKs1) from the VCO 1 that oscillates a low frequency.

In the above, the judgment result of the 4-field judging means 11 is inputted to the 16-field judging means 12 and
An embodiment in which the skew state in the field or 16 field period is monitored and the VCO switching means is controlled based on the determination result has been described, but as shown by the dotted line in FIG.
The VCO switching means may be controlled based on the determination result of the 4-field determination means 11.

[0023]

As described above, the PL according to the present invention
According to the L circuit, the skew generated at the head switching position of the VTR is detected and detected, and the frequency dividing circuit is reset so that phase comparison is not performed, and the skew occurs at a time other than the period corresponding to the VTR head switching position. The skew is also detected, and it is determined whether the occurrence of the skew is caused by the oscillation frequency of the VCO being high or low by measuring the direction and the number of the skews generated in one field period 1. Field determination means,
A four-field determination means for detecting and determining a change in the skew direction in the four-field period and a sixteen-field determination means for determining the number of skews in the same direction determined in the four-field period in the sixteen-field period. Since the VCO having an appropriate oscillation frequency is automatically switched based on the determination result, it is possible to generate a stable system clock signal even when a video signal having a different horizontal frequency is input as in the NTSC system, the PAL system and the like. .

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a circuit block diagram showing an embodiment of a skew detecting means.

FIG. 3 is a circuit block diagram showing an embodiment of a 1-field determination means.

FIG. 4 is a circuit block diagram showing an embodiment of a 4-field determination means.

FIG. 5 is a block diagram showing an example of 16-field determination means.

FIG. 6 is a block diagram showing an embodiment of Vgate pulse generating means.

FIG. 7 is a block diagram showing an embodiment of a field clear signal generating means.

FIG. 8 is a block diagram showing an embodiment of a VCO switching control unit and VCO switching means.

FIG. 9 is a timing chart explaining the operation of the skew detecting means.

FIG. 10 is a timing chart for explaining the operation of the 1-field determination means.

FIG. 11 is a timing chart explaining the operation of the 4-field determination means.

FIG. 12 is a timing chart explaining the operation of the 16-field determination means.

FIG. 13 is a timing chart for explaining the operation of the Vgate pulse generating means.

FIG. 14 is a timing chart for explaining the operation of the field clear signal generating means.

FIG. 15 is a block diagram showing a conventional PLL circuit.

[Explanation of symbols]

 1 Horizontal Sync Separation Circuit 2 Phase Comparison Circuit 3 Low Pass Filter 4 Voltage Controlled Oscillator (VCO) 5 VCO Switching Means 6 Dividing Circuit 7 Skew Detection Means 8 Vertical Sync Separation Circuit 9 V System Signal Generating Means 10 1 Field Judging Means 11 4 Fields Judgment means 12 16 Field judgment means 13 VCO switching control section

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display area H04L 7/033

Claims (11)

[Claims] 1. A horizontal synchronization separating circuit for separating a horizontal synchronizing signal from an input video signal, a horizontal synchronizing signal (Hsync) of the synchronizing separating circuit, and a frequency dividing signal (Hcks) of a frequency dividing circuit.
/ N) for comparing the phases, a low-pass filter for outputting the low-pass component of the output signal (Scomp) from the phase-comparison circuit, and a system clock (CKs) by the output voltage (Vlf) of the low-pass filter. A voltage controlled oscillator (hereinafter referred to as VCO) that generates a signal, a plurality of combination means of the phase comparison circuit, the low-pass filter, and the VCO are provided, and a VCO switching means that switches and outputs the plurality of combination means, and the VCO switching means. The output of the signal is divided, and the signal (Ss
the frequency dividing circuit reset in c), the skew detecting means for detecting the disturbance of the cycle of the horizontal synchronizing signal,
The output of the skew detecting means is inputted, the one-field judging means for judging whether or not the plurality of combining means are switched by monitoring the occurrence state of the skew for one field period, and the output of the skew detecting means are inputted. 4 field determination means for monitoring the occurrence state of skew for 4 field periods and inputting the result to 16 field determination means,
The 16-field determining means, the 1-field determining means, and the 16-field determining means, which inputs a signal from the 4-field determining means, monitors a skew occurrence state in a 16-field period and determines whether to switch the plurality of VCOs, A VCO switching control unit that controls switching of the VCO switching unit based on a signal from the field determination unit, a vertical synchronization separation circuit that separates a vertical synchronization signal from an input video signal, the vertical synchronization signal and a horizontal synchronization signal, etc. And a V-system signal generating means for generating various field signals to be inputted to the respective field determining means. 2. A horizontal synchronization separation circuit for separating a horizontal synchronization signal from an input video signal, a horizontal synchronization signal (Hsync) of the synchronization separation circuit, and a frequency division signal (Hcks) of a frequency division circuit.
/ N), a phase comparison circuit for comparing the phases, a low-pass filter for outputting the low-frequency component of the output signal Scomp) from the phase comparison circuit, and an output voltage (V
lf), a voltage controlled oscillator (hereinafter referred to as VCO) that generates a system clock pulse (CKs), a plurality of combination means of the phase comparison circuit, the low-pass filter, and the VCO are provided, and the VCO that outputs by switching the plurality of combination means. The output from the switching means and the VCO switching means is frequency-divided, and the signal (Ss
the frequency dividing circuit reset in c), the skew detecting means for detecting the disturbance of the cycle of the horizontal synchronizing signal,
The output of the skew detecting means is input, the 1-field determining means for determining whether or not to switch the plurality of VCOs by monitoring the occurrence state of the skew in the 1-field period, and the output of the skew detecting means are input, The skew generation state of 16 field periods is input by inputting the 4 field determination means for monitoring the skew generation state of 4 field periods to determine whether to switch the plurality of VCOs and the output of the 4 field determination means. Monitor and monitor the VCOs
16-field determination means for determining whether or not to switch, and a VCO switching control section for switching-controlling the VCO switching means based on signals from the 1-field determination means, 4-field determination means and 16-field determination means, It is composed of a vertical sync separation circuit for separating a vertical sync signal from an input video signal, and a V-system signal generating means for generating various field signals to be inputted to each field judging means from the vertical sync signal and the horizontal sync signal. PLL circuit characterized in that. 3. The skew detecting means is an H gate pulse (Shg) having a pulse width of a predetermined number of clocks from the system clock (CKs) signal from the VCO switching means.
p) and an H gate pulse edge of 1 clock width (Shgp
e) H gate pulse generation means for generating a signal, gate means for gated the horizontal synchronization (Hsync) signal by the H gate pulse (Shgp) from the H gate generation means, and gate from the gate means (Shsg) Signal, the H gate pulse edge (Shgpe) signal, the system clock (CKs) signal, and the horizontal synchronization (Hsyn)
3. The PLL circuit according to claim 1, further comprising: c) a skew pulse generating means for inputting a signal to generate a skew detection (Ssc) signal. 4. The H gate pulse generation means AND gates an MSB signal from a clock counter that counts a skew detection (Ssc) signal and a system clock (CKs) signal from the skew pulse generation means.
An ND circuit and a clock counter that inputs a signal from the AND circuit and counts a system clock (CKs) signal, and a predetermined low value of the signal from the clock counter are decoded to generate an H gate pulse edge (Shgp).
e) A low-value decoding circuit that outputs a signal, a high-value decoding circuit that decodes a predetermined high value, a signal from the low-value decoding circuit, a signal from the high-value decoding circuit, and a system clock (CKs) signal are input. 4. A PL according to claim 3, wherein the PL circuit comprises a JK flip-flop circuit that outputs an H gate pulse (Shgp) signal.
L circuit. 5. The skew pulse generating means is the H
H gate pulse edge (S
hgpe) signal and the H gate (Sh
sg) signal and a system clock (CKs) signal as input, a first D flip-flop circuit, a signal from the first D flip-flop circuit, and an H gate pulse edge (Shgpe) signal from the H gate pulse generating means. And a second D flip-flop circuit for inputting a system clock (CKs) signal, an AND circuit for AND-gate the signal from the second D flip-flop circuit and the signal from the first D flip-flop circuit, The signal from the AND circuit and the horizontal synchronization (Hs
yc) signal is NAND gated to detect skew (Ss
4. The PLL circuit according to claim 3, wherein the PLL circuit comprises a NAND circuit for outputting a signal c). 6. The skew detection (Ssc) from the skew detection means is performed by the one-field determination means by a Vgate pulse (Svgp) having a width of ± 16H of a negative vertical synchronizing signal output from the V-system signal generation means. ) A first OR circuit for OR-gate a signal, a NOR circuit for NOR-gate an output signal from the first OR circuit and a signal from the second OR circuit, a signal from the NOR circuit and the frequency dividing circuit. UP / DW which is the MSB signal of the counter to be formed
N (Su / d) signal and the system clock (CKs)
An up-down counter section for inputting a signal to up-count or down-count, an UP value decoding section for decoding an up-level value of the output of the up-down counter section, a DWN value decoding section for decoding a down-level value, and Decode output from UP value decoding unit (S
3. The PLL circuit according to claim 1, wherein the PLL circuit is configured by the second OR circuit that OR-gates the up) signal and the decode output (Sdwn) signal from the DWN value decoding unit. 7. The four-field determining means detects a skew (Ssc) from the skew detecting means by a Vgate pulse (Svgp) having a width of ± 16H of a negative vertical synchronizing signal output from the V-system signal generating means. ) A first OR circuit for OR gate the signal, a second OR circuit for OR gate the output signal of the first OR circuit and the signal from the Q output of the first D flip-flop circuit, and the first O circuit.
A third OR circuit that OR-gates the output signal of the R circuit and the signal from the Q output of the second D flip-flop circuit, and the MSB signal of the counter that forms the signal from the second OR circuit and the frequency dividing circuit. UP / DWN (Su / d) signal, the system clock (CKs) signal, and the pulse (Sf) for every four fields output from the V-system signal generating means.
Enter 4) to detect skew in the up direction (Sups)
A signal from the first D flip-flop circuit that generates a signal, the signal from the third OR circuit, and a signal opposite in polarity to the UP / DWN signal that is the MSB signal of the counter that forms the frequency dividing circuit, and the system clock ( CKs) signal and a pulse (S) for every four fields output from the V system signal generating means.
Input f4) to detect skew in the down direction (Sdwn
s) A second D flip-flop circuit that generates a signal, and a first AN that AND-gates the Q output of the first D flip-flop and the Q ′ output of the second D flip-flop.
2. A D circuit and a second AND circuit that AND-gates the Q'output of the first D flip-flop and the Q output of the second D flip-flop. PLL circuit. 8. The 16-field determination means detects skew in the up direction from the first AND circuit (Su).
ps) signal and the sixth O to OR gate the skew detection (Sdwns) signal in the down direction from the second AND circuit.
R circuit, the signal from the sixth OR circuit and the first A
An up-down count unit for inputting a signal from the ND circuit, a pulse (Sf4) for every 4 fields and a pulse (Sf16) for every 16 fields output from the V-system signal generating means, and up-counting or down-counting;
8. The UP value decoding section for decoding the up level value of the output of the up / down counter section, and the DWN value decoding section for decoding the down level value, according to claim 1 and claim 7. PLL circuit. 9. The V-system signal generation means includes a count unit for inputting the horizontal synchronization signal (Hsync), a system clock (CKs) signal and a vertical synchronization signal (Vsync), and a predetermined output of the counter unit. Vgat including an L-value decoding unit that decodes a low value, an H-value decoding unit that decodes a predetermined high value, and a JK flip-flop
Vgate pulse (Svgp,
3. The PLL circuit according to claim 1, wherein the PLL circuit outputs S'vgp). 10. The V-system signal generating means includes the Vga.
Vgate pulse (Svgp) from te pulse generation means
Of two T flip-flops for inputting, and a first AND circuit for AND-gates the outputs of the first and second T flip-flops, and the output signal of the AND circuit for vertical synchronization (V
The second A that AND-gates the inverted signal of the sync) signal.
An ND circuit, an inverted signal that inverts the Vgate pulse (Svgp), a NAND circuit that NAND gates the signal from the first AND circuit, two stages of T flip-flops that input the output signal of the NAND circuit, and 1 Step 2
A third AND circuit that AND-gates the output of the T flip-flop in the second stage, an output signal of the AND circuit and a second A circuit.
Fourth AN for AND gateing output signal from ND circuit
3. A pulse (Sf4) for every 4 fields and a pulse (Sf16) for every 16 fields are output from a field clear signal generating means constituted by a D circuit. PLL circuit. 11. The VCO switching means includes two decode outputs (UP detection signal (Sup) and DWN detection signal (Sdw) from the decoding section of the one-field determination means.
n)) respectively, and the Q of the T flip-flop,
A first AND circuit and a second AND circuit that AND gates with the Q'output, a first OR circuit that inputs or OR gates the output signals of the two AND circuits, the output signal of the OR circuit, and the one field The T flip-flop for inputting the output signal (S1f) from the second OR circuit of the judging means, the Q output signal from the T flip-flop, and the first VCO output signal (CKs1) of the plurality of VCOs are ANDed. A third AND circuit that gates, a fourth AND circuit that AND gates the Q ′ output signal from the T flip-flop and the second VCO output signal (CKs2) of the plurality of VCOs, and the third AND circuit. 3. The PLL according to claim 1 or 2, wherein the PLL is constituted by a second OR circuit that OR-gates the output signal of the AND circuit and the output signal of the fourth AND circuit. Road.