JPH07334254A - Voltage stahbilizing circuit - Google Patents

Abstract

PURPOSE:To provide the voltage stabilizing circuit which can reduce an overshoot voltage without sacrificing current capacitance and oscillation tolerance. CONSTITUTION:This circuit is provided with a reference voltage generating circuit 12 for generating a reference voltage REF from an input voltage VIN, differential amplifier 11 provided with a differential pair and a current mirror load so as to supply the reference voltage REF to the differential pair as one input, stabilized voltage output circuit 13 for outputting a voltage VOUT stabilized corresponding to the output of the differential amplifier 11 while being supplied the input voltage VIN, voltage dividing circuit 14 for dividing the stabilized voltage VOUT and supplying it to the differential pair as the other input, and diode D1 for fixing the output of the differential amplifier 11 at a prescribed potential until the voltage stabilizing operation is started by the differential amplifier 11 and the stabilized voltage output circuit 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage stabilizing circuit using a differential amplifier.

[0002]

2. Description of the Related Art A conventional structure of a voltage stabilizing circuit of this type is shown in FIG. This voltage stabilizing circuit includes NPN type transistors Q1 and Q2 and PNP type transistors Q3 and Q4.
And a differential amplifier 11 including a current source I1, a constant voltage diode (Zener diode) ZD, and a resistor R1 connected in series to the constant voltage diode (Zener diode) ZD.
And a reference voltage generating circuit 12 for generating an NPN-type transistor Q whose operation is controlled according to the output of the differential amplifier 11 and which outputs a stabilized voltage VOUT from the input voltage VIN.
5, a PNP type transistor Q6, Q7, a stabilized voltage output circuit 13 composed of a resistor R2 and a current source I2, and a voltage divider circuit 14 composed of resistors R4 and R5 for dividing the stabilized voltage VOUT. Therefore, the reference voltage VREF is input to the base of the transistor Q1 of the differential amplifier 11, and the division voltage in the voltage division circuit 14 is the same as that of the transistor Q1.
It is input to the base of 2. In the figure, C1 is a bypass capacitor, C2 is an output stabilization bypass capacitor, and C3 is a phase compensating capacitor, that is, an oscillation preventing capacitor.

The circuit of FIG. 3 constitutes a non-inverted amplifier circuit, and an output voltage V generated at the collector of the transistor Q7.
OUT is given by the following equation. VOUT = {(R3 + R4) / R4} × VREF ... 1

[0004]

The problem with the conventional circuit shown in FIG. 3 is that VOU when the power (VIN) is turned on.
It is raised that the overshoot voltage of T is large.
If the overshoot voltage exceeds the absolute maximum rating of the device connected to the node of the output voltage VOUT, it may lead to deterioration of the device, and the overshoot voltage should be as small as possible.

FIG. 4 shows the state of the overshoot voltage at the output voltage VOUT of the circuit of FIG. The mechanism of overshoot voltage generation will be described below with reference to FIGS. 3 and 4. In the circuit of Figure 3, power supply (VIN)
Before is turned on, VOUT is 0V. Simultaneously with the input of VIN, the transistor Q7 is in a fully charged state, and the charging of the capacitor C2 is started with the peak current I7. At this time, the current amplification factors of the transistors Q6 and Q7 are set to hFE6,
Assuming that hFE7, the peak current I7 is given by the following equation.

I7 = I2 × hFE6 × hFE7 ... 2 The state at this time is T = T0 to T1 in FIG.
In the period of, the inclination θ when the capacitor C2 is charged is θ
= I7 / C2. In FIG. 4, when VOUT reaches a predetermined voltage value VREG when T = T1, the state shifts from the full charge state to the voltage regulation (voltage stabilizing operation) state, but the voltage regulation actually starts. A delay time TD is required until T = T2.

Now, the base potentials of the transistor Q5 in FIG. 3 in the periods of T = T0 to T1 and T = T2 are VREF-VBE1 and VIN-VBE7-VBE6 +, respectively.
It becomes VBE5. However, transistors Q1, Q5, Q
6, the base-emitter voltage of V7 is VBE1, VBE5
, VBE6 and VBE7, and the collector-emitter voltage during the saturation operation of the transistor Q1 is set to almost zero.
That is, during the delay time TD, the base of the transistor Q5 undergoes a potential fluctuation of the potential difference ΔV given by the following equation.

ΔV = (VIN−VBE7−VBE6 + VBE5) − (VREF−VBE1) ... 3 Here, the base-emitter voltages of the respective transistors are equal. V
It becomes REF. Further, the value of the delay time TD is determined by the value of the capacitor C3 for phase compensation and the value of the current source I1 in FIG. 3, and is given by the following equation.

TD = (C3 × ΔV) / I1 ... 4 That is, in FIG. 3, the overshoot voltage VOV obtained by subtracting VREG from the peak voltage VP is expressed by the following equation.

VOV = θ × TD = (I7 × C3 × ΔV) / (C2 × I1) ... 5 As can be seen from the above formula 5, the overshoot voltage VOV
In order to reduce C, it is conceivable to reduce the current capacity of the voltage stabilizing circuit indicated by I7 or reduce C3. However, in the former case, there is a problem that the performance as a stabilized power source is lowered by reducing the current capacity. Further, in the latter case, the oscillation margin becomes small, which causes a problem that oscillation easily occurs. Therefore, it is desired to reduce the overshoot voltage VOV without sacrificing the current capacity and the oscillation allowance.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the overshoot voltage without sacrificing the current capacity and oscillation margin of the voltage stabilizing circuit. It is to provide a voltage stabilizing circuit.

[0012]

A voltage stabilizing circuit according to the present invention comprises a reference voltage generating means for generating a reference voltage from a voltage to be stabilized, a differential pair consisting of a pair of NPN type transistors, and a pair of PNP type. And a current amplifying load including a transistor, and the reference voltage is supplied to the differential pair as one input, and the voltage to be stabilized is supplied to stabilize the output in accordance with the output of the differential amplifier. Stabilized voltage output means for outputting the stabilized voltage, voltage dividing means for dividing the stabilized voltage and supplying it to the differential pair as the other input, the differential amplifying means and the stabilized voltage output And a potential fixing means for fixing the output of the differential amplifying means to a predetermined potential during the period until the voltage stabilizing operation by the means is started.

[0013]

By fixing the output of the differential amplifying means to the predetermined potential by the potential fixing means, the difference between the output potentials of the differential amplifying means before and after the voltage stabilizing operation is started is reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a first embodiment circuit of the present invention. This example circuit includes a differential amplifier 11, a reference voltage generation circuit 12, and a stabilized voltage output circuit as in the conventional circuit of FIG.
13 and a voltage dividing circuit 14 are provided, and a diode D1 as a potential fixing means is newly added.

The differential amplifier 11 is composed of NPN type transistors Q1 and Q2, PNP type transistors Q3 and Q4, and a current source I1. Both transistors Q above
The emitters of 1 and Q2 are commonly connected, and the current source I1 is connected between this common emitter and the low potential side of the input voltage VIN. The collectors of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively. The emitters of the transistors Q3 and Q4 are commonly connected to the high potential side of the input voltage VIN, and the base and collector of the transistor Q3 are short-circuited. That is, in the differential amplifier 11, the pair of NPN type transistors Q1 and Q2 form a differential pair, the pair of PNP type transistors Q3 and Q4 form a current mirror load, and the collectors of the transistors Q4 and Q1 are common. The connection point is an output node.

The reference voltage generating circuit 12 is composed of a resistor R1 and a constant voltage diode (Zener diode) ZD connected in series between the high potential side and the low potential side of the input voltage VIN, and the series connection point. To generate a reference voltage VREF. The reference voltage VREF is input to the base of the transistor Q1 in the differential amplifier 11.

The stabilized voltage output circuit 13 includes an NPN type transistor Q5, PNP type transistors Q6 and Q7,
It is composed of a resistor R2 and a current source I2. That is,
Transistor Q4 which is the output node of the differential amplifier 11
The base of the transistor Q5 is connected to the common connection point of the collectors of Q1 and Q1. The collector of the transistor Q5 is connected to the high potential side of the input voltage VIN, and the current source I2 is connected between the emitter and the low potential side of the input voltage VIN. The base of the transistor Q6 is connected to the emitter of the transistor Q5. A resistor R2 is connected between the emitter of the transistor Q6 and the high potential side of the input voltage VIN, and the collector is connected to the low potential side of the input voltage VIN. The base of the transistor Q7 is connected to the emitter of the transistor Q6.
The emitter of the transistor Q7 is connected to the high potential side of the input voltage VIN, and the collector is connected to the node of the output voltage VOUT.

The voltage dividing circuit 14 is composed of two resistors R4 and R5 connected in series between the node of the output voltage VOUT and the low potential side of the input voltage VIN.
4, the reference voltage VREF of the output voltage VOUT according to the value of R5
The gain for is set. Also, both resistors R4 and R5
A division voltage corresponding to the resistance ratio is obtained at the serial connection point of. This divided voltage is input to the base of the transistor Q2 in the differential amplifier 11.

Diode D1 as the potential fixing means
Are connected between the base and the emitter of the NPN type transistor Q5 in the stabilized voltage output circuit 13 in the direction opposite to the PN junction between the base and the emitter.

In the embodiment circuit of FIG. 1, C1 is a bypass capacitor, C2 is a bypass capacitor for stabilizing output, and C3 is a capacitor for phase compensation.
In the circuit having such a configuration, VOUT is 0V before the power (VIN) is turned on. Next, at the same time as turning on VIN, the transistor Q7 becomes fully charged,
Charging of the capacitor C2 is started via the transistor Q7. The output voltage Vout is VREG in FIG.
Until it reaches the base voltage (reference voltage VREF) of the transistor Q1 in the differential amplifier 11,
Since the base voltage of 2 is lower, the transistor Q1 is turned on. At this time, the potential of the output node of the differential amplifier 11, that is, the base potential of the transistor Q5 will be set to the difference between the voltage of the constant voltage diode ZD and the base-emitter voltage of the transistor Q1 as in the conventional circuit. However, since the diode D1 is connected between the base and emitter of the transistor Q5, its potential is set by the paths of the transistors Q7, Q6 and the diode D1. That is, the transistor Q5
Has a base potential fixed to VIN-VBE7-VBE6-VF. However, VF is the forward voltage of the diode D1.

On the other hand, VOUT reaches a predetermined voltage value VREG, and then the full charge state shifts to the voltage regulation (voltage stabilizing operation) state. The base potential of the transistor Q5 in this voltage regulated state becomes VIN-VBE7-VBE6 + VBE5 as in the case of the conventional circuit.

In the circuit of this embodiment, the base of the transistor Q5 in the full charge state and the voltage regulated state is ΔV = (VIN-VBE7-VBE6 + VBE5)-(VIN-VBE7-VBE6-VF) ... 6. The applied potential difference ΔV, that is, the potential variation of VBE5 + VF is received.

If the forward voltage of the diode is equal to the base-emitter voltage VBE of each transistor, then the above equation 6 is ΔV = 2VBE. That is, ΔV is conventionally VIN-VREF, but it becomes 2VBE in the circuit of this embodiment. Generally, the reference voltage VREF in the reference voltage generation circuit 12 is set to a value sufficiently smaller than the input voltage VIN. For example, when VIN is 10V, VRE is set.
If F is set to 1V, Δ in the conventional circuit
The value of V = VIN-VREF becomes 9V. On the other hand, VBE
Is about 0.7V, and the value of ΔV = 2VBE in this embodiment circuit is about 1.4V.
It is sufficiently smaller than V. Since the overshoot voltage VOV is proportional to ΔV as shown in the above equation 5, the overshoot voltage VOV can be reduced in this embodiment circuit without sacrificing the current capacity and oscillation margin.

FIG. 2 shows a second embodiment circuit of the present invention. In the circuit of this embodiment, two diodes D11, D12 connected in series between the high potential side of the input voltage VIN and the output node of the differential amplifier 11 are used as the potential fixing means. . In the case of this embodiment circuit,
In the fully charged state until the output voltage Vout reaches VREG in FIG. 4, the base potential of the transistor Q5 is fixed at VIN-2VF. However, VF is the forward voltage of each of the diodes D11 and D12. Therefore, in the circuit of this embodiment, the base of the transistor Q5 in the full charge state and the voltage regulated state has a potential difference ΔV given by ΔV = (VIN−VBE7−VBE6 + VBE5) − (VIN−2VF). Will be subject to fluctuations. Here, similar to the above, if the base-emitter voltage of each transistor is the same and is represented by VBE, and the forward voltage of the diode is equal to VBE, the above equation 7 is ΔV = VBE. That is, conventionally, ΔV is VIN
What was −VREF is V in the embodiment circuit of FIG.
BE, and the overshoot voltage VOV can be further reduced as compared with the embodiment of FIG.

In the embodiment circuit of FIG. 2, the case where the potential fixing means is composed of two diodes connected in series has been described, but this is the case where the potential fixing means in which two or more diodes are connected in series is used. Of course, you may use it.

[0026]

As described above, according to the present invention,
The overshoot voltage can be reduced without sacrificing the current capacity and oscillation allowance as the voltage stabilizing circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is a waveform diagram for explaining the operation of the conventional circuit of FIG.

[Explanation of symbols]

11 ... Differential amplifier, 12 ... Reference voltage generating circuit, 13 ... Stabilized voltage output circuit, 14 ... Voltage dividing circuit, D1, D11, D12 ... Diodes as potential fixing means.

Claims (4)

[Claims] 1. A reference voltage generating means for generating a reference voltage from a voltage to be stabilized, a differential pair including a pair of NPN type transistors, and a current mirror load including a pair of PNP type transistors. Differential amplifying means for supplying a voltage to the differential pair as one input, and stabilized voltage output means for supplying a voltage to be stabilized and outputting a stabilized voltage according to the output of the differential amplifying means. A period until the voltage stabilizing operation is started by the voltage dividing means for dividing the stabilized voltage and supplying it to the differential pair as the other input, and the differential amplifying means and the stabilized voltage output means. And a potential fixing means for fixing the output of the differential amplifying means to a predetermined potential. 2. The NPN type first transistor, wherein the stabilized voltage output means has a collector connected to a node of the voltage to be stabilized and an output of the differential amplification means is supplied to a base, and the first transistor. Current source connected between the emitter of the transistor and the node of the ground potential, the emitter of the voltage node to be stabilized via a resistor, and the collector of the first transistor connected to the ground potential node. A second PNP-type transistor whose base is connected to the emitter, a emitter connected to the node of the voltage to be stabilized, a collector connected to the node of the stabilized voltage, and a base connected to the emitter of the second transistor 2. The voltage stabilizing circuit according to claim 1, wherein the voltage stabilizing circuit comprises a PNP-type third transistor that has been formed. 3. The potential fixing means comprises a diode connected between the base and the emitter of the first transistor in a direction opposite to the PN junction between the base and the emitter. Voltage stabilization circuit. 4. The potential fixing means is composed of two or more diodes connected in series between the node of the voltage to be stabilized and the output of the differential amplifying means. Voltage stabilization circuit.